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Электронный компонент: PHT8N06LT

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Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHT8N06LT
Logic level FET
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
SYMBOL
PARAMETER
MAX.
UNIT
level field-effect power transistor in a
plastic envelope suitable for surface
V
DS
Drain-source voltage
55
V
mounting. The device features very
I
D
Drain current
7.5
A
low on-state resistance and has
P
tot
Total power dissipation
1.8
W
integral zener diodes giving ESD
T
j
Junction temperature
150
C
protection. It is intended for use in
R
DS(ON)
Drain-source on-state
80
m
DC-DC
converters
and
general
resistance
V
GS
= 5 V
purpose switching applications.
PINNING - SOT223
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
3
source
4
drain (tab)
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DS
Drain-source voltage
-
-
55
V
V
DGR
Drain-gate voltage
R
GS
= 20 k
-
55
V
V
GS
Gate-source voltage
-
-
13
V
I
D
Drain current (DC)
T
sp
= 25 C
-
7.5
A
I
D
Drain current (DC)
On PCB in Fig.2
-
3.5
A
T
amb
= 25 C
I
D
Drain current (DC)
On PCB in Fig.2
-
2.2
A
T
amb
= 100 C
I
DM
Drain current (pulse peak value)
T
sp
= 25 C
-
40
A
P
tot
Total power dissipation
T
sp
= 25 C
-
8.3
W
P
tot
Total power dissipation
On PCB in Fig.2
-
1.8
W
T
amb
= 25 C
T
stg
, T
j
Storage & operating temperature
-
- 55
150
C
ESD LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
C
Electrostatic discharge capacitor
Human body model
-
2
kV
voltage
(100 pF, 1.5 k
)
d
g
s
4
1
2
3
January 1998
1
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHT8N06LT
Logic level FET
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
R
th j-sp
From junction to solder point
Mounted on any PCB
12
15
K/W
R
th j-amb
From junction to ambient
Mounted on PCB of Fig.17
-
70
K/W
STATIC CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 0.25 mA
55
-
-
V
voltage
T
j
= -55C
50
-
-
V
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 1 mA
1.0
1.5
2.0
V
T
j
= 150C
0.6
-
-
V
T
j
= -55C
-
-
2.3
V
I
DSS
Zero gate voltage drain current
V
DS
= 55 V; V
GS
= 0 V;
-
0.05
10
A
T
j
= 150C
-
-
100
A
I
GSS
Gate source leakage current
V
GS
=
5 V
-
0.02
1
A
T
j
= 150C
-
-
5
A
V
(BR)GSS
Gate source breakdown voltage I
G
=
1 mA
10
-
-
V
R
DS(ON)
Drain-source on-state
V
GS
= 5 V; I
D
= 5 A
-
65
80
m
resistance
T
j
= 150C
-
-
148
m
DYNAMIC CHARACTERISTICS
T
mb
= 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
g
fs
Forward transconductance
V
DS
= 25 V; I
D
= 5 A; T
j
= 25C
4
-
-
S
Q
g(tot)
Total gate charge
I
D
= 7 A; V
DD
= 44 V; V
GS
= 5 V
-
11.2
-
nC
Q
gs
Gate-source charge
-
2.2
-
nC
Q
gd
Gate-drain (Miller) charge
-
5
-
nC
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
-
500
650
pF
C
oss
Output capacitance
-
110
135
pF
C
rss
Feedback capacitance
-
60
85
pF
t
d on
Turn-on delay time
V
DD
= 30 V; I
D
= 7 A;
-
10
15
ns
t
r
Turn-on rise time
V
GS
= 5 V; R
G
= 10
;
-
30
50
ns
t
d off
Turn-off delay time
-
30
45
ns
t
f
Turn-off fall time
T
j
= 25C
-
30
40
ns
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= -55 to 175C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I
DR
Continuous reverse drain
T
sp
= 25C
-
-
7.5
A
current
I
DRM
Pulsed reverse drain current
T
sp
= 25C
-
-
40
A
V
SD
Diode forward voltage
I
F
= 5 A; V
GS
= 0 V
-
0.85
1.1
V
t
rr
Reverse recovery time
I
F
= 5 A; -dI
F
/dt = 100 A/
s;
-
38
-
ns
Q
rr
Reverse recovery charge
V
GS
= -10 V; V
R
= 30 V
-
0.2
-
C
January 1998
2
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHT8N06LT
Logic level FET
AVALANCHE LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
W
DSS
Drain-source non-repetitive
I
D
= 2.5 A; V
DD
25 V;
-
-
30
mJ
unclamped inductive turn-off
V
GS
= 5 V; R
GS
= 50
; T
sp
= 25 C
energy
January 1998
3
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHT8N06LT
Logic level FET
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
sp
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
sp
); conditions: V
GS
5 V
Fig.3. Safe operating area. T
sp
= 25 C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-sp
= f(t); parameter D = t
p
/T
Fig.5. Typical output characteristics, T
j
= 25 C.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(I
D
); parameter V
GS
0
20
40
60
80
100
120
140
Tmb / C
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
1.0E-06
0.0001
0.01
1
100
0.01
0.1
1
10
100
Zth/ (K/W)
t/s
0.5
0.2
0.1
0.05
0.02
D =
t
p
t
p
T
T
P
t
D
0
20
40
60
80
100
120
140
Tmb / C
ID%
Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
0
2
4
6
8
10
0
10
20
30
40
10
VGS = 5.0 V
4.6
4.0
3.6
3.2
3.0
2.6
2.4
7
6
Drain current, ID (A)
Drain-source voltage, VDS (V)
1
10
100
0.1
1
10
100
VDS/V
RDS(ON) = VDS/ID
DC
ID/A
tp =
1 us
10us
100 us
1 ms
10ms
100ms
5
10
15
20
25
70
75
80
85
90
95
100
105
110
115
RDS(ON)/mOhm
4
4.2
4.4
4.6
4.8
5
ID/A
January 1998
4
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHT8N06LT
Logic level FET
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Fig.8. Typical transconductance, T
j
= 25 C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
); I
D
= 5 A; V
GS
= 5 V
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
0
1
2
3
4
5
0
5
10
15
20
ID/A
VGS/V
Tj/C =
150
25
BUK98xx-55
-100
-50
0
50
100
150
200
0
0.5
1
1.5
2
2.5
Tj / C
VGS(TO) / V
max.
typ.
min.
0
5
10
15
20
5
6
7
8
9
10
11
12
13
14
15
Transconductance, gfs (S)
Drain current, ID (A)
0
0.5
1
1.5
2
2.5
3
1E-05
1E-05
1E-04
1E-03
1E-02
1E-01
Sub-Threshold Conduction
2%
typ
98%
BUK98XX-55
-100
-50
0
50
100
150
200
0.5
1
1.5
2
2.5
Tmb / degC
Rds(on) normalised to 25degC
a
0.01
0.1
1
10
100
0
.1
.2
.3
.4
.5
.6
.7
.8
.9
1
Thousands pF
VDS/V
Ciss
Coss
Crss
January 1998
5
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHT8N06LT
Logic level FET
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 7 A; parameter V
DS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
sp
); conditions: I
D
= 2.5 A
Fig.16. Avalanche energy test circuit.
0
2
4
6
8
10
12
0
1
2
3
4
5
6
VDS/V
QG/nC
VDS = 14V
VDS = 44V
20
40
60
80
100
120
140
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
0
0.5
1
1.5
2
0
10
20
30
40
IF/A
VSDS/V
Tj/V =
150
25
L
T.U.T.
VDD
RGS
R 01
VDS
-ID/100
+
-
shunt
VGS
0
W
DSS
=
0.5
LI
D
2
BV
DSS
/(
BV
DSS
-
V
DD
)
January 1998
6
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHT8N06LT
Logic level FET
PRINTED CIRCUIT BOARD
Dimensions in mm.
Fig.17. PCB for thermal resistance and power rating for SOT223.
PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35
m thick).
36
60
9
10
4.6
18
4.5
7
15
50
January 1998
7
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHT8N06LT
Logic level FET
MECHANICAL DATA
Dimensions in mm
Net Mass: 0.11 g
Fig.18. SOT223 surface mounting package.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to surface mounting instructions for SOT223 envelope.
3. Epoxy meets UL94 V0 at 1/8".
6.7
6.3
3.1
2.9
4
1
2
3
2.3
1.05
0.85
0.80
0.60
4.6
3.7
3.3
7.3
6.7
B
A
0.10
0.02
13
16
max
1.8
max
10
max
0.32
0.24
(4x)
B
M
0.1
A
M
0.2
January 1998
8
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHT8N06LT
Logic level FET
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1998
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
January 1998
9
Rev 1.100