Document Outline
- FEATURES
- SYMBOL
- QUICK REFERENCE DATA
- GENERAL DESCRIPTION
- PINNING
- SOT404
- SOT429 (TO247)
- LIMITING VALUES
- AVALANCHE ENERGY LIMITING VALUES
- THERMAL RESISTANCES
- ELECTRICAL CHARACTERISTICS
- SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS
- MECHANICAL DATA
- MOUNTING INSTRUCTIONS
- MECHANICAL DATA
- DEFINITIONS
- LIFE SUPPORT APPLICATIONS
Philips Semiconductors
Product specification
PowerMOS transistors
PHB11N50E, PHW11N50E
Avalanche energy rated
FEATURES
SYMBOL
QUICK REFERENCE DATA
Repetitive Avalanche Rated
Fast switching
V
DSS
= 500 V
Stable off-state characteristics
High thermal cycling performance
I
D
= 10.9 A
Low thermal resistance
R
DS(ON)
0.55
GENERAL DESCRIPTION
N-channel, enhancement mode field-effect power transistor, intended for use in off-line switched mode power supplies,
T.V. and computer monitor power supplies, d.c. to d.c. converters, motor control circuits and general purpose switching
applications.
The PHW11N50E is supplied in the SOT429 (TO247) conventional leaded package.
The PHB11N50E is supplied in the SOT404 surface mounting package.
PINNING
SOT404
SOT429 (TO247)
PIN
DESCRIPTION
1
gate
2
drain
1
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DSS
Drain-source voltage
T
j
= 25 C to 150C
-
500
V
V
DGR
Drain-gate voltage
T
j
= 25 C to 150C; R
GS
= 20 k
-
500
V
V
GS
Gate-source voltage
-
30
V
I
D
Continuous drain current
T
mb
= 25 C; V
GS
= 10 V
-
10.9
A
T
mb
= 100 C; V
GS
= 10 V
-
6.9
A
I
DM
Pulsed drain current
T
mb
= 25 C
-
44
A
P
D
Total dissipation
T
mb
= 25 C
-
156
W
T
j
, T
stg
Operating junction and
- 55
150
C
storage temperature range
d
g
s
1
3
tab
2
2
3
1
1 It is not possible to make connection to pin 2 of the SOT404 package.
December 1998
1
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistors
PHB11N50E, PHW11N50E
Avalanche energy rated
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
E
AS
Non-repetitive avalanche
Unclamped inductive load, I
AS
= 10.9 A;
-
707
mJ
energy
t
p
= 0.2 ms; T
j
prior to avalanche = 25C;
V
DD
50 V; R
GS
= 50
; V
GS
= 10 V
E
AR
Repetitive avalanche energy
2
I
AR
= 10.9 A; t
p
= 2.5
s; T
j
prior to
-
18
mJ
avalanche = 25C; R
GS
= 50
; V
GS
= 10 V
I
AS
, I
AR
Repetitive and non-repetitive
-
10.9
A
avalanche current
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction
-
-
0.8
K/W
to mounting base
R
th j-a
Thermal resistance junction
SOT78 package, in free air
-
60
-
K/W
to ambient
SOT429 package, in free air
-
45
-
K/W
SOT404 package, pcb mounted, minimum
-
50
-
K/W
footprint
ELECTRICAL CHARACTERISTICS
T
j
= 25 C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 0.25 mA
500
-
-
V
voltage
V
(BR)DSS
/ Drain-source breakdown
V
DS
= V
GS
; I
D
= 0.25 mA
-
0.1
-
%/K
T
j
voltage temperature
coefficient
R
DS(ON)
Drain-source on resistance
V
GS
= 10 V; I
D
= 5.5 A
-
0.47
0.55
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 0.25 mA
2.0
3.0
4.0
V
g
fs
Forward transconductance
V
DS
= 30 V; I
D
= 5.5 A
4
6.5
-
S
I
DSS
Drain-source leakage current V
DS
= 500 V; V
GS
= 0 V
-
1
25
A
V
DS
= 400 V; V
GS
= 0 V; T
j
= 125 C
-
60
500
A
I
GSS
Gate-source leakage current V
GS
=
30 V; V
DS
= 0 V
-
10
200
nA
Q
g(tot)
Total gate charge
I
D
= 11 A; V
DD
= 400 V; V
GS
= 10 V
-
75
100
nC
Q
gs
Gate-source charge
-
7
12
nC
Q
gd
Gate-drain (Miller) charge
-
39
55
nC
t
d(on)
Turn-on delay time
V
DD
= 250 V; R
D
= 22
;
-
11
-
ns
t
r
Turn-on rise time
R
G
= 5.6
-
38
-
ns
t
d(off)
Turn-off delay time
-
92
-
ns
t
f
Turn-off fall time
-
40
-
ns
L
d
Internal drain inductance
Measured from tab to centre of die
-
3.5
-
nH
L
d
Internal drain inductance
Measured from drain lead to centre of die
-
4.5
-
nH
(SOT429 package only)
L
s
Internal source inductance
Measured from source lead to source
-
7.5
-
nH
bond pad
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
-
1326
-
pF
C
oss
Output capacitance
-
182
-
pF
C
rss
Feedback capacitance
-
96
-
pF
2 pulse width and repetition rate limited by T
j
max.
December 1998
2
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistors
PHB11N50E, PHW11N50E
Avalanche energy rated
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS
T
j
= 25 C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
I
S
Continuous source current
T
mb
= 25C
-
-
10.9
A
(body diode)
I
SM
Pulsed source current (body
T
mb
= 25C
-
-
44
A
diode)
V
SD
Diode forward voltage
I
S
= 11 A; V
GS
= 0 V
-
-
1.2
V
t
rr
Reverse recovery time
I
S
= 11 A; V
GS
= 0 V; dI/dt = 100 A/
s
-
630
-
ns
Q
rr
Reverse recovery charge
-
6.9
-
C
December 1998
3
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistors
PHB11N50E, PHW11N50E
Avalanche energy rated
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
mb
); conditions: V
GS
10 V
Fig.3. Safe operating area. T
mb
= 25 C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Fig.5. Typical output characteristics.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance.
R
DS(ON)
= f(I
D
); parameter V
GS
0
20
40
60
80
100
120
140
Tmb / C
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
PHP11N50E
0.001
0.01
0.1
1
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
1E+01
pulse width, tp (s)
Transient Thermal Impedance, Zth j-a (K/W)
D = 0.5
0.2
0.1
0.05
0.02
Single pulse
tp
D = tp/T
T
P
t
D
0
20
40
60
80
100
120
140
Tmb / C
ID%
Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
PHP11N50E
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
Drain-Source Voltage, VDS (V)
Drain Current, ID (A)
4 V
4.2 V
4.4 V
4.6 V
Tj = 25 C
VGS = 10 V
4.8 V
5 V
PHP11N50E
0.1
1
10
100
10
100
1000
Drain-Source Voltage, VDS (V)
Peak Pulsed Drain Current, IDM (A)
d.c.
100 ms
10 ms
RDS(on) = VDS/ ID
tp = 10 us
1 ms
100 us
PHP11N50E
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0
1
2
3
4
5
6
7
8
Drain Current, ID (A)
Drain-Source On Resistance, RDS(on) (Ohms)
VGS = 10 V
4.2V
4.6V
4.8V
5V
Tj = 25 C
4 V
4.4V
December 1998
4
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistors
PHB11N50E, PHW11N50E
Avalanche energy rated
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
); parameter T
j
Fig.8. Typical transconductance.
g
fs
= f(I
D
); parameter T
j
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
); I
D
= 5.5 A; V
GS
= 10 V
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 0.25 mA; V
DS
= V
GS
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
PHP11N50E
0
2
4
6
8
10
12
14
16
18
20
0
1
2
3
4
5
6
7
Gate-source voltage, VGS (V)
Drain current, ID (A)
VDS > ID X RDS(ON)
Tj = 25 C
150 C
-60
-40
-20
0
20
40
60
80
100
120
140
Tj / C
VGS(TO) / V
4
3
2
1
0
max.
typ.
min.
PHP11N50E
0
2
4
6
8
10
12
0
5
10
15
20
Drain current, ID (A)
Transconductance, gfs (S)
VDS > ID X RDS(ON)
Tj = 25 C
150 C
0
1
2
3
4
VGS / V
ID / A
1E-01
1E-02
1E-03
1E-04
1E-05
1E-06
SUB-THRESHOLD CONDUCTION
typ
2 %
98 %
-60
-40
-20
0
20
40
60
80
100 120 140
Tj / C
Normalised RDS(ON) = f(Tj)
2
1
0
a
PHP11N50E
10
100
1000
10000
0.1
1
10
100
Drain-source voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
Ciss
Coss
Crss
December 1998
5
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistors
PHB11N50E, PHW11N50E
Avalanche energy rated
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); parameter V
DS
Fig.14. Typical switching times; t
d(on)
, t
r
, t
d(off)
, t
f
= f(R
G
)
Fig.15. Normalised drain-source breakdown voltage;
V
(BR)DSS
/V
(BR)DSS 25 C
= f(T
j
)
Fig.16. Source-Drain diode characteristic.
I
F
= f(V
SDS
); parameter T
j
Fig.17. Maximum permissible non-repetitive
avalanche current (I
AS
) versus avalanche time (t
p
);
unclamped inductive load
Fig.18. Maximum permissible repetitive avalanche
current (I
AR
) versus avalanche time (t
p
)
PHP11N50E
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
20
40
60
80
100
120
Gate charge, QG (nC)
Gate-source voltage, VGS (V)
VDD=400V
200V
100 V
ID = 11A
Tj = 25 C
PHP11N50E
0
2
4
6
8
10
12
14
16
18
20
0
0.2
0.4
0.6
0.8
1
1.2
Drain-Source Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
Tj = 25 C
150 C
PHP11N50E
0
50
100
150
200
250
300
350
400
450
0
10
20
30
40
50
Gate resistance, RG (Ohms)
Switching times, td(on), tr, td(off), tf (ns)
td(on)
td(off)
tr
tf
VDD = 250V
RD = 22 Ohms
PHP12N50E
0.1
1
10
100
1E-06
1E-05
1E-04
1E-03
1E-02
Avalanche time, tp (s)
Non-repetitive Avalanche current, IAS (A)
125 C
VDS
ID
tp
Tj prior to avalanche = 25 C
-100
-50
0
50
100
150
0.85
0.9
0.95
1
1.05
1.1
1.15
Tj, Junction temperature (C)
Normalised Drain-source breakdown voltage
V(BR)DSS @ Tj
V(BR)DSS @ 25 C
PHP12N50E
0.01
0.1
1
10
100
1E-06
1E-05
1E-04
1E-03
1E-02
Avalanche time, tp (s)
Maximum Repetitive Avalanche Current, IAR (A)
125 C
Tj prior to avalanche = 25 C
December 1998
6
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistors
PHB11N50E, PHW11N50E
Avalanche energy rated
MECHANICAL DATA
Dimensions in mm
Net Mass: 1.4 g
Fig.19. SOT404 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
Fig.20. SOT404 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
11 max
4.5 max
1.4 max
10.3 max
0.5
15.4
2.5
0.85 max
(x2)
2.54 (x2)
17.5
11.5
9.0
5.08
3.8
2.0
December 1998
7
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistors
PHB11N50E, PHW11N50E
Avalanche energy rated
MECHANICAL DATA
Dimensions in mm
Net Mass: 5 g
Fig.21. SOT429; pin 2 connected to mounting base.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for SOT429 envelope.
3. Epoxy meets UL94 V0 at 1/8".
5.3
4.0
21
max
15.5
min
1
2.2 max
0.4
2.5
0.9 max
5.3 max
3.5
16 max
5.45
seating
plane
5.45
M
o
max
15.5
max
3.2 max
2
3
1.1
3.5
1.8
7.3
max
December 1998
8
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistors
PHB11N50E, PHW11N50E
Avalanche energy rated
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1998
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
December 1998
9
Rev 1.000
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