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Электронный компонент: PMWD18UN

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PMWD18UN
Dual N-channel
TrenchMOSTM ultra low level FET
Rev. 02 -- 23 February 2004
Product data
M3D647
1.
Product profile
1.1 Description
Dual common drain N-channel enhancement mode field-effect transistor in a plastic
package using TrenchMOSTM technology.
1.2 Features
1.3 Applications
1.4 Quick reference data
2.
Pinning information
s
Surface mounted package
s
Low profile
s
Very low threshold
s
Fast switching.
s
Portable appliances
s
PCMCIA cards
s
Battery management
s
Load switching.
s
V
DS
30 V
s
I
D
7.8 A
s
P
tot
2.3 W
s
R
DSon
21.5 m
.
Table 1:
Pinning - SOT530-1 (TSSOP8), simplified outline and symbol
Pin
Description
Simplified outline
Symbol
1,8
drain (d)
SOT530-1 (TSSOP8)
2,3
source1 (s1)
4
gate1 (g1)
5
gate2 (g2)
6,7
source2 (s2)
MBK885
Top view
1
4
8
5
mbl600
d
d
g1
s1
g2
s2
Philips Semiconductors
PMWD18UN
Dual N-channel
TrenchMOSTM ultra low level FET
Product data
Rev. 02 -- 23 February 2004
2 of 12
9397 750 12706
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
3.
Ordering information
4.
Limiting values
[1]
Single device conducting
Table 2:
Ordering information
Type number
Package
Name
Description
Version
PMWD18UN
TSSOP8
Plastic thin shrink small outline package; 8 leads
SOT530-1
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
V
DS
drain-source voltage (DC)
25
C
T
j
150
C
-
30
V
V
DGR
drain-gate voltage (DC)
25
C
T
j
150
C; R
GS
= 20 k
-
30
V
V
GS
gate-source voltage
-
12
V
I
D
drain current (DC)
T
sp
= 25
C; V
GS
= 4.5 V;
Figure 2
and
3
[1]
-
7.8
A
T
sp
= 100
C; V
GS
= 4.5 V;
Figure 2
[1]
-
5
A
I
DM
peak drain current
T
sp
= 25
C; pulsed; t
p
10
s;
Figure 3
[1]
-
32
A
P
tot
total power dissipation
T
sp
= 25
C;
Figure 1
[1]
-
2.3
W
T
stg
storage temperature
-
55
+150
C
T
j
junction temperature
-
55
+150
C
Source-drain diode
I
S
source (diode forward) current (DC)
T
sp
= 25
C
[1]
-
1.9
A
I
SM
peak source (diode forward) current T
sp
= 25
C; pulsed; t
p
10
s
[1]
-
7.6
A
Philips Semiconductors
PMWD18UN
Dual N-channel
TrenchMOSTM ultra low level FET
Product data
Rev. 02 -- 23 February 2004
3 of 12
9397 750 12706
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
V
GS
4.5 V
Fig 1.
Normalized total power dissipation as a
function of solder point temperature.
Fig 2.
Normalized continuous drain current as a
function of solder point temperature.
T
sp
= 25
C; I
DM
is single pulse
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
03aa17
0
40
80
120
0
50
100
150
200
(%)
Tsp (
C)
Pder
03aa25
0
40
80
120
0
50
100
150
200
Tsp (
C)
Ider
(%)
P
der
P
tot
P
tot 25 C
(
)
-----------------------
100%
=
I
der
I
D
I
D 25 C
(
)
-------------------
100%
=
003aaa258
10-2
10-1
1
10
102
10-1
1
10
102
VDS (V)
ID
(A)
DC
100 ms
10 ms
Limit RDSon = VDS
/ ID
1 ms
1 s
100
s
tp = 10
s
Philips Semiconductors
PMWD18UN
Dual N-channel
TrenchMOSTM ultra low level FET
Product data
Rev. 02 -- 23 February 2004
4 of 12
9397 750 12706
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5.
Thermal characteristics
5.1 Transient thermal impedance
Table 4:
Thermal characteristics
Symbol Parameter
Conditions
Min Typ Max
Unit
R
th(j-sp)
thermal resistance from junction to solder point
Figure 4
-
-
55
K/W
R
th(j-a)
thermal resistance from junction to ambient
mounted on a printed-circuit board;
minimum footprint
-
100 -
K/W
Fig 4.
Transient thermal impedance from junction to solder point as a function of pulse duration.
003aaa259
10-1
1
10
102
10-4
10-3
10-2
10-1
1
10
102
tp (s)
Zth(j-sp)
(K/W)
single pulse
= 0.5
0.2
0.1
0.05
0.02
tp
tp
T
P
t
T
=
Philips Semiconductors
PMWD18UN
Dual N-channel
TrenchMOSTM ultra low level FET
Product data
Rev. 02 -- 23 February 2004
5 of 12
9397 750 12706
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
6.
Characteristics
Table 5:
Characteristics
T
j
= 25
C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V
(BR)DSS
drain-source breakdown voltage
I
D
= 250
A; V
GS
= 0 V
T
j
= 25
C
30
-
-
V
T
j
=
-
55
C
27
-
-
V
V
GS(th)
gate-source threshold voltage
I
D
= 1 mA; V
DS
= V
GS;
Figure 9
0.45
0.7
-
V
I
DSS
drain-source leakage current
V
DS
= 30 V; V
GS
= 0 V
T
j
= 25
C
-
-
1
A
T
j
= 150
C
-
-
100
A
I
GSS
gate-source leakage current
V
GS
=
10 V; V
DS
= 0 V
-
-
100
nA
R
DSon
drain-source on-state resistance
V
GS
= 4.5 V; I
D
= 5 A;
Figure 7
and
8
T
j
= 25
C
-
18
21.5
m
T
j
= 150
C
-
31
37
m
V
GS
= 1.8 V; I
D
= 4.5 A;
Figure 7
and
8
-
24
35
m
V
GS
= 2.5 V; I
D
= 5 A;
Figure 7
and
8
-
20
23.5
m
Dynamic characteristics
Q
g(tot)
total gate charge
I
D
= 4 A; V
DD
= 16 V; V
GS
= 4.5 V;
Figure 13
-
24.7
-
nC
Q
gs
gate-source charge
-
2.2
-
nC
Q
gd
gate-drain (Miller) charge
-
6.4
-
nC
C
iss
input capacitance
V
GS
= 0 V; V
DS
= 16 V; f = 1 MHz;
Figure 11
-
1526 -
pF
C
oss
output capacitance
-
210
-
pF
C
rss
reverse transfer capacitance
-
160
-
pF
t
d(on)
turn-on delay time
V
DD
= 10 V; I
D
= 1 A; V
GS
= 4.5 V; R
G
= 6
-
15
-
ns
t
r
rise time
-
21
-
ns
t
d(off)
turn-off delay time
-
57
-
ns
t
f
fall time
-
26
-
ns
Source-drain diode
V
SD
source-drain (diode forward) voltage I
S
= 5 A; V
GS
= 0 V;
Figure 12
-
0.87
1.2
V
t
rr
reverse recovery time
I
S
= 5 A; dI
S
/dt =
-
100 A/
s; V
R
= 30 V;
V
GS
= 0 V
-
55
-
ns
Q
r
recovered charge
-
21
-
nC
Philips Semiconductors
PMWD18UN
Dual N-channel
TrenchMOSTM ultra low level FET
Product data
Rev. 02 -- 23 February 2004
6 of 12
9397 750 12706
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
T
j
= 25
C
T
j
= 25
C and 150
C; V
DS
I
D
R
DSon
Fig 5.
Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 6.
Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
T
j
= 25
C
Fig 7.
Drain-source on-state resistance as a function
of drain current; typical values.
Fig 8.
Normalized drain source on-state resistance
factor as a function of junction temperature.
003aaa260
0
1
2
3
4
5
0
0.2
0.4
0.6
0.8
1
VDS (V)
ID
(A)
1 V
1.1 V
1.2 V
VGS = 1.3 V
1.8 V
4.5 V
003aaa261
0
2
4
6
8
10
0
0.5
1
1.5
2
VGS (V)
ID
(A)
Tj = 150
C
25
C
003aaa262
0
40
80
120
160
0
1
2
3
4
5
ID (A)
RDSon
(m
)
2.5 V
1.1 V
1.2 V
1.3 V
4.5 V
VGS = 1.8 V
03aa27
0
0.5
1
1.5
2
-60
0
60
120
180
Tj (
C)
a
a
R
DSon
R
DSon 25
C
(
)
------------------------------
=
Philips Semiconductors
PMWD18UN
Dual N-channel
TrenchMOSTM ultra low level FET
Product data
Rev. 02 -- 23 February 2004
7 of 12
9397 750 12706
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
I
D
= 1 mA; V
DS
= V
GS
T
j
= 25
C; V
DS
= 5 V
Fig 9.
Gate-source threshold voltage as a function of
junction temperature.
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
V
GS
= 0 V; f = 1 MHz
T
j
= 25
C and 150
C; V
GS
= 0 V
Fig 11. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values.
Fig 12. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values.
03aj65
0
0.2
0.4
0.6
0.8
1
-60
0
60
120
180
Tj (
C)
VGS(th)
(V)
min
typ
03aj64
10-6
10-5
10-4
10-3
0
0.2
0.4
0.6
0.8
1
VGS (V)
ID
(A)
min
typ
003aaa263
10
102
103
104
10
1
10
102
VDS (V)
C
(pF)
Ciss
Coss
Crss
003aaa264
0
1
2
3
4
5
0
0.2
0.4
0.6
0.8
1
VSD (V)
IS
(A)
25
C
Tj = 150
C
Philips Semiconductors
PMWD18UN
Dual N-channel
TrenchMOSTM ultra low level FET
Product data
Rev. 02 -- 23 February 2004
8 of 12
9397 750 12706
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
I
D
= 4 A; V
DD
= 16 V
Fig 13. Gate-source voltage as a function of gate charge; typical values.
003aaa265
0
1
2
3
4
5
0
10
20
30
QG (nC)
VGS
(V)
Philips Semiconductors
PMWD18UN
Dual N-channel
TrenchMOSTM ultra low level FET
Product data
Rev. 02 -- 23 February 2004
9 of 12
9397 750 12706
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
7.
Package outline
Fig 14. SOT530-1 (TSSOP8).
UNIT
A1
A
max.
A2
A3
bp
L
HE
Lp
w
y
v
c
e
D
(1)
E
(2)
Z
(1)
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
mm
0.15
0.05
0.95
0.85
0.30
0.19
0.20
0.13
3.1
2.9
4.5
4.3
0.65
6.5
6.3
0.70
0.35
8
0
0.1
0.1
0.1
0.94
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.7
0.5
SOT530-1
MO-153
00-02-24
03-02-18
w
M
bp
D
Z
e
0.25
1
4
8
5
A
A2
A1
Lp
(A3)
detail X
L
HE
E
c
v
M
A
X
A
y
2.5
5 mm
0
scale
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 4.4 mm
SOT530-1
1.1
pin 1 index
Philips Semiconductors
PMWD18UN
Dual N-channel
TrenchMOSTM ultra low level FET
Product data
Rev. 02 -- 23 February 2004
10 of 12
9397 750 12706
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.
Revision history
Table 6:
Revision history
Rev Date
CPCN
Description
02
20040223
-
Product data (9397 750 12706)
Modifications:
Correction to I
D
data in
Section 1.4 "Quick reference data"
Correction to P
tot
, I
D,
I
DM
, I
S
and I
SM
data in
Table 3 "Limiting values"
Correction to R
th(j-sp)
data in
Table 4 "Thermal characteristics"
Figure 3
and
Figure 4
updated.
Section 3 "Ordering information"
added
01
20030204
-
Product data (9397 750 10832)
9397 750 12706
Philips Semiconductors
PMWD18UN
Dual N-channel
TrenchMOSTM ultra low level FET
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 -- 23 February 2004
11 of 12
9397 750 12706
Philips Semiconductors
PMWD18UN
Dual N-channel
TrenchMOSTM ultra low level FET
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 -- 23 February 2004
11 of 12
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
Fax: +31 40 27 24825
9.
Data sheet status
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
10. Definitions
Short-form specification -- The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition -- Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information -- Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
11. Disclaimers
Life support -- These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes -- Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status `Production'),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
12. Trademarks
TrenchMOS --
is a trademark of Koninklijke Philips Electronics N.V.
Level
Data sheet status
[1]
Product status
[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
Koninklijke Philips Electronics N.V. 2004.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 23 February 2004
Document order number: 9397 750 12706
Contents
Philips Semiconductors
PMWD18UN
Dual N-channel
TrenchMOSTM ultra low level FET
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 1
3
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
5
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
5.1
Transient thermal impedance . . . . . . . . . . . . . . 4
6
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10
9
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11
10
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11