ChipFind - документация

Электронный компонент: PSMN025-100D

Скачать:  PDF   ZIP
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PSMN025-100D
FEATURES
SYMBOL
QUICK REFERENCE DATA
'Trench' technology
Very low on-state resistance
V
DSS
= 100 V
Fast switching
Low thermal resistance
I
D
= 47 A
R
DS(ON)
25 m
GENERAL DESCRIPTION
PINNING
SOT428 (DPAK)
SiliconMAX products use the latest
PIN
DESCRIPTION
Philips
Trench
technology
to
achieve
the
lowest
possible
1
gate
on-state
resistance
in
each
package at each voltage rating.
2
drain
1
Applications:-
3
source
d.c. to d.c. converters
switched mode power supplies
tab
drain
The PSMN025-100D is supplied in
the
SOT428
(Dpak)
surface
mounting package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DSS
Drain-source voltage
T
j
= 25 C to 175C
-
100
V
V
DGR
Drain-gate voltage
T
j
= 25 C to 175C; R
GS
= 20 k
-
100
V
V
GS
Gate-source voltage
-
20
V
I
D
Continuous drain current
T
mb
= 25 C; V
GS
= 10 V
-
47
A
T
mb
= 100 C; V
GS
= 10 V
-
33
A
I
DM
Pulsed drain current
T
mb
= 25 C
-
188
A
P
D
Total power dissipation
T
mb
= 25 C
-
150
W
T
j
, T
stg
Operating junction and
- 55
175
C
storage temperature
d
g
s
1
2
3
tab
1 It is not possible to make connection to pin 2 of the SOT428 package.
August 1999
1
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PSMN025-100D
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
E
AS
Non-repetitive avalanche
Unclamped inductive load, I
AS
= 40 A;
-
260
mJ
energy
t
p
= 100
s; T
j
prior to avalanche = 25C;
V
DD
25 V; R
GS
= 50
; V
GS
= 10 V; refer
to fig:15
I
AS
Non-repetitive avalanche
-
47
A
current
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction
-
-
1
K/W
to mounting base
R
th j-a
Thermal resistance junction
SOT428 package, pcb mounted, minimum
-
50
-
K/W
to ambient
footprint
ELECTRICAL CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 0.25 mA;
100
-
-
V
voltage
T
j
= -55C
89
-
-
V
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 1 mA
2
3
4
V
T
j
= 175C
1
-
-
V
T
j
= -55C
-
-
6
V
R
DS(ON)
Drain-source on-state
V
GS
= 10 V; I
D
= 25 A
-
22
25
m
resistance
T
j
= 175C
-
-
68
m
I
GSS
Gate source leakage current V
GS
=
10 V; V
DS
= 0 V
-
0.02
100
nA
I
DSS
Zero gate voltage drain
V
DS
= 100 V; V
GS
= 0 V;
-
0.05
10
A
current
T
j
= 175C
-
-
500
A
Q
g(tot)
Total gate charge
I
D
= 45 A; V
DD
= 80 V; V
GS
= 10 V
-
61
-
nC
Q
gs
Gate-source charge
-
13
-
nC
Q
gd
Gate-drain (Miller) charge
-
25
-
nC
t
d on
Turn-on delay time
V
DD
= 50 V; R
D
= 1.8
;
-
18
-
ns
t
r
Turn-on rise time
V
GS
= 10 V; R
G
= 5.6
-
72
-
ns
t
d off
Turn-off delay time
Resistive load
-
69
-
ns
t
f
Turn-off fall time
-
58
-
ns
L
d
Internal drain inductance
Measured tab to centre of die
-
3.5
-
nH
L
s
Internal source inductance
Measured from source lead to source
-
7.5
-
nH
bond pad
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
-
2600
-
pF
C
oss
Output capacitance
-
340
-
pF
C
rss
Feedback capacitance
-
195
-
pF
August 1999
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PSMN025-100D
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
I
S
Continuous source current
-
-
47
A
(body diode)
I
SM
Pulsed source current (body
-
-
188
A
diode)
V
SD
Diode forward voltage
I
F
= 25 A; V
GS
= 0 V
-
0.87
1.2
V
t
rr
Reverse recovery time
I
F
= 20 A; -dI
F
/dt = 100 A/
s;
-
82
-
ns
Q
rr
Reverse recovery charge
V
GS
= 0 V; V
R
= 25 V
-
0.26
-
C
August 1999
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PSMN025-100D
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
mb
); V
GS
10 V
Fig.3. Safe operating area
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Fig.5. Typical output characteristics, T
j
= 25 C.
I
D
= f(V
DS
)
Fig.6. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(I
D
)
Normalised Power Derating, PD (%)
0
10
20
30
40
50
60
70
80
90
100
0
25
50
75
100
125
150
175
Mounting Base temperature, Tmb (C)
0.001
0.01
0.1
1
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
Pulse width, tp (s)
Transient thermal impedance, Zth j-mb (K/W)
single pulse
D = 0.5
0.2
0.1
0.05
0.02
tp
D = tp/T
D
P
T
Normalised Current Derating, ID (%)
0
10
20
30
40
50
60
70
80
90
100
0
25
50
75
100
125
150
175
Mounting Base temperature, Tmb (C)
0
5
10
15
20
25
30
35
40
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Drain-Source Voltage, VDS (V)
4 V
Drain Current, ID (A)
4.6 V
Tj = 25 C
VGS = 10V
4.8 V
8 V
4.4 V
5 V
6 V
4.2 V
0.1
1
10
100
1000
1
10
100
1000
Drain-Source Voltage, VDS (V)
Peak Pulsed Drain Current, IDM (A)
D.C.
100 ms
10 ms
RDS(on) = VDS/ ID
1 ms
tp = 10 us
100 us
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0
2
4
6
8
10
12
14
16
18
20
Drain Current, ID (A)
Drain-Source On Resistance, RDS(on) (Ohms)
VGS = 10V
Tj = 25 C
6V
8 V
4.2 V
4.8 V
5 V
4.4 V
4 V
4.6 V
August 1999
4
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PSMN025-100D
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
)
Fig.8. Typical transconductance, T
j
= 25 C.
g
fs
= f(I
D
)
Fig.9. Normalised drain-source on-state resistance.
R
DS(ON)
/R
DS(ON)25 C
= f(T
j
)
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
0
5
10
15
20
25
30
35
40
45
50
0
1
2
3
4
5
6
Gate-source voltage, VGS (V)
Drain current, ID (A)
VDS > ID X RDS(ON)
Tj = 25 C
175 C
Threshold Voltage, VGS(TO) (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
-60
-40
-20
0
20
40
60
80
100 120 140 160 180
Junction Temperature, Tj (C)
typical
maximum
minimum
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
Drain current, ID (A)
Transconductance, gfs (S)
Tj = 25 C
175 C
VDS > ID X RDS(ON)
Drain current, ID (A)
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Gate-source voltage, VGS (V)
minimum
typical
maximum
Normalised On-state Resistance
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
-60
-40
-20
0
20
40
60
80
100 120 140 160 180
Junction temperature, Tj (C)
10
100
1000
10000
0.1
1
10
100
Drain-Source Voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
Ciss
Coss
Crss
August 1999
5
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PSMN025-100D
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
)
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.15. Maximum permissible non-repetitive
avalanche current (I
AS
) versus avalanche time (t
AV
);
unclamped inductive load
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
Gate charge, QG (nC)
Gate-source voltage, VGS (V)
ID = 45A
Tj = 25 C
VDD = 20 V
VDD = 80 V
1
10
100
0.001
0.01
0.1
1
10
Avalanche time, t
AV
(ms)
Maximum Avalanche Current, I
AS
(A)
Tj prior to avalanche = 150 C
25 C
0
5
10
15
20
25
30
35
40
45
50
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1.1 1.2 1.3 1.4 1.5
Source-Drain Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
Tj = 25 C
175 C
VGS = 0 V
August 1999
6
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PSMN025-100D
MECHANICAL DATA
Fig.16. SOT428 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
SOT428
98-04-07
0
10
20 mm
scale
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
SOT428
E
b2
D1
w
A
M
b
c
b1
L1
L
1
3
2
D
E1
HE
L2
Note
1. Measured from heatsink back to lead.
e1
e
A
A2
A
A1
y
seating plane
mounting
base
A1
(1)
D
max.
b
D1
max.
E
max.
HE
max.
w
y
max.
A2
b2
b1
max.
c
E1
min.
e
e1
L1
min.
L2
L
A
max.
UNIT
DIMENSIONS (mm are the original dimensions)
0.2
0.2
mm
2.38
2.22
0.65
0.45
0.89
0.71
0.89
0.71
1.1
0.9
5.36
5.26
0.4
0.2
6.22
5.98
4.81
4.45
2.285
4.57
10.4
9.6
0.5
0.7
0.5
6.73
6.47
4.0
2.95
2.55
August 1999
7
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PSMN025-100D
MOUNTING INSTRUCTIONS
Dimensions in mm
Fig.17. SOT428 : soldering pattern for surface mounting.
7.0
7.0
2.15
2.5
4.57
1.5
August 1999
8
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PSMN025-100D
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
August 1999
9
Rev 1.000