Philips Semiconductors

Product specification

SA1638

Low voltage IF I/Q transceiver

1997 Sept 03

853-1818 18351

DESCRIPTION

The SA1638 is a combined Rx and Tx IF I/Q circuit. The receive
path contains an IF amplifier, a pair of quadrature down-mixers, and
a pair of baseband filters and amplifiers. A second pair of mixers in
the transmit path transposes a quadrature baseband input up to the
IF frequency. An external VCO signal is divided down internally and
buffered to provide quadrature local oscillator signals for the mixers.
A further divider chain, reference divider and phase detector are
provided to avoid the need for an external IF synthesizer. Rx or Tx
path or the entire circuit may be powered down by logic inputs.
On-board voltage regulators are provided to allow direct connection
to a battery supply.

FEATURES

Direct supply: 3.3V to 7.5V

Two DC regulators giving 3.0V output

Low current consumption: 18mA for Rx or 22mA for Tx

Input/output IF frequency from 70-400 MHz

Internal IF PLL for synthesizing the local oscillator signal

High performance on-board integrated receive filters with
bandwidth tunable between 50-850 kHz

Switchable alternative bandwidth setting available to allow
channel bandwidth flexibility in operation

Designed for a widely used I and Q baseband GSM interface

Control registers power up in a default state

Optional DC offset trim capability to <200mV

Only a standard reference input frequency required, choice of 13,
26, 39 or 52MHz

Fully compatible with SA1620 GSM RF front-end (see Figure 9)

APPLICATIONS

IF circuitry for GSM 900MHz hand-held units

IF circuitry for PCN (DCS1800) hand-held units

Quadrature up and down mixer stage

PIN CONFIGURATION

LQFP Package

CLK IN

CLK INX

VEEDIG

DATA

VEECP

IREF

LO INX

LO IN

ADJ IN

CLOCK

VREG1

VREGF2

VREG2

GNDREG2

PON

VBATT

AOUT

BOUT

DCRES

RESD

48pin LQFP

13 14

15 16 17 18 19

21 22 23 24

RESA

RESB

STROBE

LOCK

GNDREG1

VccTxRx

GND1

RxIF IN

RxIF INX

GND2

TxIFOUT

TxIFOUTX

GND3

PONPLL

VccCP

PONRx

IRxOUT

IRxOUTX

QRxOUTX

ITx IN

ITx INX

QTx IN

QTx INX

PDTx

VccDIG

QRxOUT

SR00524

REF

Figure 1. SA1638 Pin Configuration

ORDERING INFORMATION

DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

DWG #

48-Pin Thin Quad Flat Pack (LQFP)

-40 to +85

SA1638BE

SOT313-2

Philips Semiconductors

Product specification

SA1638

Low voltage IF I/Q transceiver

1997 Sept 03

PIN DESCRIPTIONS

Pin No.

Pin Name

Description

VREG1

Output voltage of regulator 1

VREGF2

Feedback of regulator 2

VREG2

Output voltage of regulator 2

GNDREG2

Ground of regulator 2

PON

Power-on input for voltage regulators 1 and 2 (active high)

BATT

Input voltage for regulators 1 and 2

AOUT

Programmable logic output (see Figure 9)

BOUT

Programmable logic output (see Figure 9)

DCRES

Reference current setting resistor for DC offset circuit

RESD

Additional external current defining resistor for filters

RESA

Principal external current defining resistor for filters

RESB

Principal external current defining resistor for filters

PONRx

Power-on input for Rx (active high)

REF

Reference voltage

QRxOUT

Differential receive baseband output

QRxOUTX

Differential receive baseband output

IRxOUT

Differential receive baseband output

IRxOUTX

Differential receive baseband output

QTx IN

Differential transmit baseband input

QTx INX

Differential transmit baseband input

ITx IN

Differential transmit baseband input

ITx INX

Differential transmit baseband input

PDTx

Power-on for transmitter (active low)

DIG

Digital circuit supply

DIG

Digital ground

DATA

Serial bus data input

CLOCK

Serial bus clock input

STROBE

Serial bus strobe input

LOCK

Test control/synthesizer lock indicator

CLK INX

Differential reference divider input

CLK IN

Differential reference divider input

ADJ IN

Used for test only. Do not connect

LO IN

Differential LO input

LO INX

Differential LO input

REF

Reference current setting for charge pump

Charge pump ground

Charge pump output

Charge pump circuit supply

POnPLL

Power-on input for synthesizer circuits (active high)

GND3

Ground (internal connection to GND1 and GND2)

TxIFOUTX

Differential transmit IFoutput (open collector)

TxIFOUT

Differential transmit IFoutput (open collector)

GND2

Ground (internal connection to GND1 and GND3)

RxIF INX

Differential receive IF input

RxIF IN

Differential receive IF input

GND1

Ground (internal connection to GND2 and GND3)

TxRx

Transmit and receive circuits supply voltage (also feedback of Regulator 1)

GNDREG1

Ground of regulator 1

NOTE: There are no ESD protection diodes at Pins 41 and 42. Thus, open collector outputs may have increased DC voltage or higher AC
peak voltage.

Philips Semiconductors

Product specification

SA1638

Low voltage IF I/Q transceiver

1997 Sept 03

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

RATING

UNITS

XXX

Supply voltages: V

TxRx, V

DIG, V

-0.3 to +6.0

BATT

Battery voltage

-0.3 to +8.0

Voltage applied to any other pin

-0.3 to (V

CCXXX

+0.3)

Any GND pin to any other GND pin

Power dissipation, T

= 25

C (still air)

300

JMAX

Maximum operating junction temperature

150

MAX

Maximum power input/output

+20

dBm

STG

Storage temperature range

65 to +150

NOTE:
1. Maximum dissipation is determined by the operating ambient temperature and the thermal resistance,

. 48-pin LQFP:

= 67

C/W.

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

RATING

UNITS

XXX

Supply voltages: V

TxRx, V

DIG

2.7 to 5.5

Charge pump supply voltage

2.9 to 5.5

BATT

Battery voltage

3.3 to 7.5

Operating ambient temperature range

-40 to +85

Voltage Regulators

= 25

C, P

= 3V, P

RX = 0V, PDTX = 3V, P

PLL = 0V, V

BATT

= 3.3V, I

OUT

1 = I

OUT

2 = 15mA, V

REG

1 connected to V

TxRx, V

REG

connected to V

REG

F2; V

DIG = V

CP = 3V; unless otherwise stated.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

SYMBOL

PARAMETER

TEST CONDITIONS

Min

Typ

Max

UNITS

REG

Nominal V

OUT

2.85

2.93

3.00

3.07

3.15

BATT

3.3

7.5

OUT

1, I

OUT

Maximum output current for each
regulator

BATT

Supply current for both regulators

LOAD

= 0mA

4.3

5.7

BATT PD

Power-down supply current

= 0V, I

LOAD

= 0mA

7.7

10.3

REG

1 cap load

0.1

1000

REG

2 cap load

0.1

500

LINEREG

Line regulation

DC, V

BATT

= 3.3V to 7.5V

0.4

0.2

0.001

0.2

0.4

LOADREG

Load regulation

LOAD

= 15mA to 30mA

0.37

-0.17

0.03

Bandwidth

100

kHz

PON

Feedthrough attenuation from P

each regulator

-40

REG

Feedthrough attenuation from V

BATT

each regulator

100kHz

f = 10MHz

f = 100MHz
f = 400MHz

-61

-32

-37

-48

Turn ON time

NOTES:
1. At T

150

C a thermal switch reduces the output current to avoid damage.

2. Recommended load capacitors: In every case C

REG

1 = C

REG

2 = 100nF to ground with series resistance

0.1

. Additional capacitor

optional

1000

F with series resistance

. The low series resistance is very important to ensure regulator stability.

3. Standard deviations are based on the characterization results of 90 ICs.

Philips Semiconductors

Product specification

SA1638

Low voltage IF I/Q transceiver

1997 Sept 03

DC ELECTRICAL CHARACTERISTICS

TxRx=V

DIG=V

CP=PONRx=PONPLL= +3V; V

DIG = V

CP=GND1=GND2=GND3=PDTx = 0V; T

= 25

C, unless otherwise stated.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Supply current

Rx and IF synthesizer active

PONRx = PONPLL = PDTx = Hi

14.4

17.6

Tx and IF synthesizer active

PONRx = PDTx = Low;

PONPLL = Hi

17.4

19.5

21.6

Power-down mode

PONRx = PONPLL = Low;

PDTx = Hi

0.068

REF

Reference voltage

Generated internally

1.39

1.57

1.75

REF

SINK

SOURCE

5
5

OUT

DC output current

At pins TxIFOUT and

TxIFOUTX

1.5

1.86

2.0

2.14

2.7

Digital inputs (P

)

High level input voltage range

2.0

BATT

Low level input voltage range

0.8

Digital inputs (PDTx, P

Rx, P

PLL, P

)

High level input voltage range

2.0

TxRx

Low level input voltage range

0.8

Digital inputs (Clock, Data, Strobe)

High level input voltage range

2.0

Dig

Low level input voltage range

0.8

Digital outputs (LOCK, AOUT, BOUT)

Output voltage HIGH

= -2mA

DIG0.4

Output voltage LOW

= 2mA

0.4

AC ELECTRICAL CHARACTERISTICS

TxRx=V

DIG=V

CP=PONRx=PONPLL= +3V; V

DIG = V

CP=GND1=GND2=GND3=PDTx = 0V; LO

= 100mV

PEAK

800MHz;

CLK

= 100mV

PEAK

, 52MHz; serial registers programmed with default values; T

= 25

C unless otherwise stated. Test Circuit Figure 8.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

IF Transmit Modulator

Input modulation bandwidth

200

source impedance

0.82

0.94

1.06

MHz

COM

Common mode range for
baseband inputs

DC at pins ITxIN, ITxINx,

QTxIN, QTxINx

1.5

Peak input signal amplitude

Centered on V

COM

0.75

Third harmonic distortion

| ITxIn | = | ITxInX | =

| QTxIn | = | QTxInX |

= 0.75V

PEAK;

fin = 20kHz

-61

-57

-53

-40

INTx

Input resistance

Between pins: ITxIn and

ITxInX or QTxIn and

QTxInX

112

INTx

Input capacitance

At ITxIn, ITxInX,

QTxIn, QTxInX

Output saturation limit

TxRx-0.3

OUT

RMS output current

| ITxIn | = | ITxInX | =

| QTxIn | = | QTxInX |

= 0.75V

PEAK

0.6

0.73

0.82

0.91

1.08

LO suppression

| ITxIn | = | ITxInX | =

| QTxIn | = | QTxInX |

= 0.75V

PEAK

; fin = 20k

+30

+43

SSB

Sideband suppression

| ITxIn | = | ITxInX | =

| QTxIn | = | QTxInX |

= 0.75V

PEAK

; fin = 20k

+35

+50

Philips Semiconductors

Product specification

SA1638

Low voltage IF I/Q transceiver

1997 Sept 03

AC ELECTRICAL CHARACTERISTICS

(Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

IF Transmit Modulator (continued)

Noise density at 600kHz

|ITxIn| = |ITxInX| = |QTxIn| =

-130

-129

-128

dBc/Hz

Noise density at 10MHz

|QTxInX| = 0.75V

PEAK

-133

-131

-129

dBc/Hz

Turn ON time

PdTx = LO, transmit signal to 90%

OFF

Turn OFF time

PdTx = HI, transmit signal to 10%

IF Receiver (R = 36k

between pins RESA and RESB)

RInRx

Differential input impedance

= 400MHz

5 || 0.6

|| pF

ROutRx

Output impedance

Output common mode voltage

REF

f3dB

Low pass filter -3dB bandwidth

kHz

Low pass filter attenuation:

200kHz
400kHz
600kHz
6.5MHz
13.0MHz

6.5

8.9

38.1

10.7

45
70

>80
>80

12.5
51.9

Voltage gain

Differential output PD into GSM

baseband relative to 1200

source EMF

49.4

52.7

Noise figure

1200

source and external

matching resistor and inductor

5.7

7.0

8.3

Channel matching:

Gain
Phase

= 400.005MHz

-1.5

-0.26

0.0

1.5

degrees

Output DC offset

Differential, DCRES=562k

-60

-25

OUT

Output drive current at each pin

Source (Sink)

10 (700)

OUT

Minimum differential output swing

2.0

-1dB

Input 1dB compression point:

In band
200kHz
400kHz
600kHz

1200

source EMF

-59
-54

-55.3
-49.3

-53
-47
-47
-47

-50.7
-44.8

-47
-40

dBV

Turn ON time

POnRx = HI, to baseband signal

out

OFF

Turn OFF time

POnRx = LO, to no baseband

signal out

IF Synthesizer

Local oscillator input frequency
range

140

800

MHz

LOIN

Differential input impedance

Between pins LO

and LO

X, f

= 800MHz

276 || 0.6

|| pF

LOIN

LO peak input voltage range

Single-ended

Referred to 50

100

Programmable divider:

Division range
Step size

511

CLKIN

Reference clock input frequency

CLKIN

= 100mV

PEAK

MHz

CLKIN

Differential input impedance

Between pins ClkIn and ClkInX

10 || 1.0

|| pF

CLKIN

CLK

peak input voltage range

Single-ended, referred to 50

400

REF

Charge pump input reference
current

31.2

| I

Charge pump output current:

c0...c2 = 000
c0...c2 = 111
Step size

REF

=31.2

= V

CP/2

0.425

0.85

0.045

0.487
0.979
0.062

0.5
1.0

0.071

0.513
1.021

0.08

0.575

1.15

0.105

Philips Semiconductors

Product specification

SA1638

Low voltage IF I/Q transceiver

1997 Sept 03

AC ELECTRICAL CHARACTERISTICS

(Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

IF Synthesizer (cont.)

Relative output current variation

REF

=31.2

0.1

1.3

2.5

CP_M

Output current matching

REF

=31.2

= V

CP/2

CP_L

Output leakage current

= 0.3V to V

CP-0.3V

-0.02

0.1

0.22

Turn ON time

POnPLL = HI, to full charge

pump current

OFF

Turn OFF time

POnPLL = LO, to I

CP,

DIG <5% of operational

supply current

Serial Interface

CLOCK

Clock frequency

MHz

Set-up time: DATA to CLOCK,
CLOCK to STROBE

Hold time: CLOCK to DATA

Pulse width: CLOCK

Pulse width: STROBE

NOTES:
1. Parameter measured relative to modulation sideband amplitude.
2. After programming the DC offset register for minimum offset. DCRES = 562k

3. The turn on time relates only to the power up time of the circuit. The settling time of the integrated baseband filters has to be added (for

GSMmode = 8

s with filter bandwidth setting resistor = 36k

4. The relative output current variation is defined thus:

OUT

)

|(I

)

; with V

= 0.3V, V

= V

CP 0.3V (see Figure 3).

5. The output current matching is measured when both (positive current and negative current) sections of the output charge pumps are on.
6. As soon as P

PLL is set to LO, the phase detector is reset and no charge pumps pulses are generated.

7. Guaranteed by design.

8. NF =

20 log

4kTR

VG where, E

is the output noise voltage measured in a 1Hz bandwidth, R = 1200

, VG = gain in dB.

9. Minimium frequency is guaranteed by design.

CURRENT

VOLTAGE

SR00526

Figure 3. Relative Output Current Variation

FUNCTIONAL DESCRIPTION
Serial Programming Input

The serial input is a 3-wire input (CLOCK, STROBE, DATA) to
program the counter ratios, charge pump current, status- and
DC-offset register, mode select and test register. The programming
data is structured into two 21-bit words; each word includes 4 chip

address bits and 1 subaddress bit. Figure 2 shows the timing
diagram of the serial input. When the STROBE = L, the clock driver
is enabled and on the positive edges of the CLOCK the signal on
DATA input is clocked into a shift register. When the STROBE = H,
the clock is disabled and the data in the shift register remains stable.
Depending on the value of the subaddress bit the data is latched
into different working registers. Table 3 shows the contents of each
word.

Default States

Upon power up (V

DIG is applied) a reset signal is generated,

which sets all registers to a default state. The logic level at the
STROBE pin should be low during power up to guarantee a proper
reset. These default states are shown in Table 3.

Reference Divider

The reference divider can be programmed to four different division
ratios (:13, :26, :39, :52), see registers r0, r1; default setting: divide
by 13.

Main Divider

The external VCO signal, applied to the LO

and LO

X inputs, is

divided by two and then fed to the main divider (:N). The main
divider is a programmable 9 bit divider, the minimum division ratio is

Philips Semiconductors

Product specification

SA1638

Low voltage IF I/Q transceiver

1997 Sept 03

divide by 64. The division ratio is binary coded and set in the
registers n0 to n8. The default setting is a divide by 400.

At the completion of a main divider cycle, a main divider output is
generated which will drive the phase detector.

Phase Detector

The phase detector is a D-type flip-flop phase and frequency
detector shown in Figure 5. The flip-flops are set by the negative
edges of the output signals of the dividers. The rising edge of the
signal L will reset the flip-flops after both flip-flops have been set.
Around zero phase error this has the effect of delaying the reset for
1 reference input cycle. This avoids non-linearity or deadband
around zero phase error. The flip-flops drive on-chip charge pumps.
A source current from the charge pump acts to increase the VCO
frequency; a sink current acts to decrease the VCO frequency.

Current Setting

The charge pump current is defined by the current set between the
pin I

REF

and V

CP. The current value to be set there is 31.2

This current can be set by an external resistor to be connected
between the pin I

REF

and V

CP. The typical value R

EXT

(current

setting resistor) can be calculated with the formula

EXT

1.4V

31.2

The current can be set to zero by connecting the pin I

REF

to V

CP.

Charge Pumps

The charge pumps at pin CP are driven by the phase dectector and
the current value is determined by the binary value of the charge
pumps register CN = c2, c1, c0, default 1mA. The active charge
pump current is typically:

(c0

)

2c1

)

4c2)

)

500

Lock Detect

The output LOCK is H when the phase detector indicates a lock
condition. This condition is defined as a phase difference of less
than

1 cycle on the reference input CLK

, CLK

Test Modes (Synthesizer, Transmit Mixer)

The LOCK output is selectable as a test output. Bits x0, x1 control
the selection, the default setting is normal lock output as described
in the Lock detect section. The selection of a Bit x0, x1 combination
has a twofold effect: First it routes a divider output signal to the
LOCK pin, second it disables mixer stages in the transmit path.
Setting x0,1 = 11 disables both transmit path mixers. This mode can
be used to prevent the transmitter from producing an IF output
signal even if the transmit part is powered on (PDTx = 0V). This can
be used to simplify the control timing while commanding the transmit
and receive simultaneously without the transmit part causing
interference.

Table 1.

Test Modes

Synthesizer Signal

Transmit Mixer

at LOCK Pin

Q-mixer

I-mixer

normal lock detect

CLK

divided by reference

divider ratio

off

2 * (main divider ratio)

off

main divider output, that goes to

the phase detector

off

Status Register

The s0 and s1 status bits determine the values of the logic output
pins A

OUT

and B

OUT

. These outputs can be connected to the AGC

control inputs A and B of the SA1620. (See Figure 9)

DC Offset Register

Registers i0 to i3 and q0 to q3 control a correction to the output DC
offset of the I and Q channels of the receiver. The polarity of the DC
offset correction in the I and Q channels are determined by i0 and
q0, respectively. The other bits set the magnitude of the offset
correction. The step size of the two offset correction DACs is fixed
by an external resistor between the DCRES pin and ground. A
value of 120k

will give a step size of 200mV.

Mode Select Register

t0:

switches the RX IF gain.

t0 = 0

no attenuation

t0 = 1

10dB attenuation

The attenuation switch is included between the IF amplifier and the I
and Q mixers, thereby influencing the noise figure negligibly. The
purpose of this switch is to provide another AGC step which does
not influence the receiver noise figure. Please note that this gain
change will influence the DC offset of the I and Q mixers.
t1 = 0 test mode only, always to be set to 0.
t2, t3 sets the mode of the level locked loop (LLL)

The LLL is a circuit which processes the LO input signal in order to
provide an LO signal with a perfect 50% duty cycle, which
determines the precision of the 90

shift of the I and Q mixing

signals generated by the

2 divider. For an external tuning of the

phase shift of the I and Q mixing signals, a trimming resistor

may be connected (but is not required) between the ADJ

pin and

ground, and the LLL has to be put in one of the following modes:

Table 2.

Mode Select Register

LLL Status

LLL on (no external tune, monitor performance, default)

LLL on (with medium external tune)

LLL off (tune externally)

LLL on (with fine external tune)

selects the bandwidth of the RC low pass filters at the I, Q
Rx mixer outputs

t4 = 0

cutt-off frequency (-3dB) 110kHz

t4 = 1

cutt-off frequency (-3dB) 792kHz

selects the bandwidth of the integrated 5th-order gyrator
filters. The filters are tuneable over a range of 50kHz to
1MHz with external resistors. The -3dB bandwidth is
inversely proportional to the value of the external resistor.

With

t5, two external resistor values are selectable.

t5 = 0

the resistance between the pins RESA and
RESB determines the cutoff frequency. For
GSM a nominal bandwidth of 80kHz is chosen
when the external resistor is 36k

t5 = 1

a second resistor between the pins RESB and
RESD is connected in parallel to the first
external resistor, thus increasing the filter
bandwidth. The relative amplification is
decreased in this mode.

Philips Semiconductors

Product specification

SA1638

Low voltage IF I/Q transceiver

1997 Sept 03

The overall filter response in the receive section is the sum of the
filter responses of the passive RC low-pass filter and the active
gyrator filter.

Power Down Modes

There are 4 power-on pins in the SA1638: P

, P

Rx, PDTx,

PLL.

= H powers up both voltage regulators V

REG

1 and V

REG

2. P

should be set to L, if these internal voltage regulators are not to be
used.

Rx = H powers up the receiver part.

PDTx = L powers up the transmitter part.

PLL = H powers up the synthesizer part. As it also powers up

the first divide by 2 stage for generating the 0/90 degree phase
shifted signals for the transmit and receive mixers, it also has to be
set H if either the transmit part or the receive part is used. P

PLL

= L powers down the dividers, resets the phase detector and
disconnects the current setting pin I

REF

. In P

PLL = L mode, the

values in the serial input registers are still kept and the part still can
be reprogrammed as long as V

DIG is present.

Table 3.

Definition of SA1638 Serial Registers

First data word: (shown with default values)

Address SA1638

Sub

Adr

N-Divider

Ref

Reg

Charge-Pump

Reg Test

MSB

LSB

Address:

4 bits, a0...a3, fixed to 1110

Sub:Address:

1 bit, sa, fixed to 0 for first data word

N-Divider:

9 bits, n0...n8, values 64 (00100 0000) to 511 (111111111) allowed for IF-choice, default 400

Reference Divider Register:

2 bits, r0...r1, 00 =

13, 01 =

26, 10 =

39, 11 =

52. Default: 00

Charge-Pump Register:

3 bits, c0...c2, Binary current setting factor for charge pumps, values 000 = minimum current to 111 =
maximum current, default maximum charge pump current

Test Register:

2 bits, x0...x1, default 00, see Functional Description

Second data word: (shown with default values)

Address SA1638

Sub

Status

DC Offset Register

Mode Select Register

Address SA1638

Adr

Reg

Q-Channel

I-Channel

Mode Select Register

MSB

LSB

Address:

4 bits, a0...a3, fixed to 1110

Sub:Address:

1 bit, sa, fixed to 1 for second data word

Status Register:

2 bits, s0 sets pin A

OUT

; s1 sets pin B

OUT

, see Functional Description

DC Offset Register:

4 bits per channel, i0...i3 and q0...q3, no correction as default
i0 and q0 switches offset polarity, 0 to lower voltage, 1 to higher voltage
il...i3 and q1...q3, 000 no correction to 111 max. correction enabled

Mode Select Register:

6 bits,

t0...t5,

000000 = normal GSM-Operation as default, see Functional Description

Philips Semiconductors

Product specification

SA1638

Low voltage IF I/Q transceiver

1997 Sept 03

Overview of Dual GSM/PCN Architecture

The SA1620 RF front-end and SA1638 IF transceivers form a dual
conversion architecture which uses a common IF and standard I/Q
baseband interface for both transmit and receive paths. The time
division multiplex nature of the GSM system permits integration of
the transmit and receive functions together on the one RF and one
IF chips. This simplifies the distribution of local oscillator signals,
maximizes circuitry commonality, and reduces power consumption.

The SA1620 and SA1638 allow considerable flexibility to optimize
the transceiver design for particular price/size/performance
requirements, through choice of appropriate RF and IF filters. The
IF may be chosen freely in the range 70400 MHz. The same IF
can be used in the transmit and receive directions. Alternately,
different IFs can be used if the SA1638 synthesizer frequency is
switched between transmit and receive timeslots. The comparison
frequency of the SA1638 PLL is high in order to provide fast
switching time.

With suitable choice of the IF, an identical SA1638 IF receiver
design can be used for both 900MHz GSM and 1800MHz PCN
(DCS1800) equipment.

General Benefits/Advantages

2.7V operation. Compatible with 3V digital technology and
portable applications. (Higher voltage operation also possible, if
desired.)

Excellent dynamic range. The availability of two LNAs in the
SA1620 allows flexibility in receiver dynamic design for portable
and mobile GSM spec. applications with appropriate filters. If for
a particular application a GaAs or discrete front-end is desired,
one of the LNAs can be left unpowered. Placing the AGC gain
switches at the front results in some attenuation most of the time,
further increasing typical dynamic performance beyond that
specified by GSM.

High power transmit output driver, delivering +7.5dBm output.
This is sufficient to drive a filter and power amplifier input, without
a driver amplifier. To avoid unnecessary current consumption, the

output power can be reduced to an appropriate level by choice of
an external resistor.

DC offsets generated in the receive channel are independent of
the LNA AGC setting, and correctable by software to prevent
erosion of signal handling dynamic range by DC offsets.

Minimal high-quality filter requirements. As a result of the
integration in the SA1638 of high quality channel selectivity filters,
only sufficient filtering is needed in the receive path to provide
blocking protection for the second mixers. This reduces receiver
cost and size.

Operation at a high IF allows RF image reject filter requirements
to be relaxed. For example, at a 400MHz IF, the natural gain
roll-off in the SA1620 LNAs and mixer suppresses the image
signal in the 1800MHz band by typically 28dB below the desired
900MHz band signal.

DC Offset Correction

DC offset correction is provided by two DACs each feeding into one
of the two Rx channels. The step size of both DACs is set by the
value of the external resistor between DCRES and ground. Thus
any original offset less than 1.5V magnitude in either channel can be
reduced to the specified level by selecting the appropriate DAC
setting via the serial interface.

Integrated Receive Filters

The low-pass characteristics of the Rx channel are determined by
two low-pass responses. The first of these is a passive filter at the
output of the quadrature mixers and the second is the low-pass
filters which follow the post-mixer amplifiers. These specifications
refer only to the response of the default state, but this may be
switched by the control register to an alternative setting with a
nominal 3dB point of 792kHz.

The corner frequency of the low pass filters can be adjusted over a
wide range by varying the value of the external resistor between
RESA and RESB. The range of feasible corner frequencies extends
at least between 50kHz and 500kHz.

Philips Semiconductors

Product specification

SA1638

Low voltage IF I/Q transceiver

1997 Sept 03

030mA

100nF

1nF

10nF

112k

22k

56k

10k

I/Q

GEN

DC - 1MHz

BATT

OUT

REF

Rx OUT

PD Tx

CC DIG

DATA

CLOCK

STROBE

LOCK

3-WIRE

SERIAL

BUS

VREG1

VREGF2

VREG2

GNDREG2

BATT

OUT

DCRES

RESD

RESA

RESB

REF

QRxOUT

QRxOUTX

IRxOUT

IRxOUTX

QTxIN

QTxINX

ITxIN

ITxINX

PDTx

CC DIG

GNDREG1

TxRx

GND1

RxIFIN

RxIFINX

GND2

TxIFOUT

TxIFOUTX

GND3

PLL

CCP

REF

LOINX

LOIN

ADJ

CLKIN

CLKINX

LOCK

STROBE

CLOCK

DATA

EE DIG

1nF

100nF

10nF

470pF

4.7nF

4740

LOIN

ADJ

CLKIN

VCP

PLL

CCP

23V

TxOUT

RxIN

33nH

2:1

1nF

TC414

1.8pF

1800

51.4

2.5k

294

17.4

294

10nF

17.4

49.9

294

17.4

2.7pF

10pF

1nF

SR00531

800MHz

VCO

10nF

Figure 8. SA1638 Test Circuit

Philips Semiconductors

Product specification

SA1638

Low voltage IF I/Q transceiver

1997 Sept 03

TYPICAL PERFORMANCE CHARACTERISTICS

Regulator Dropout Voltage vs. Temperature and V

BATT

Temperature (

5.5V

7.5V

3.3V

LOAD

=30mA

-50 -40

-30

-20 -10

4.5

3.5

2.5

1.5

0.5

VOL

AGE (V)

Regulator Supply Current vs. Temperature and V

BATT

No Load

7.5V

3.3V

5.5V

Temperature (

-50 -40

-30

-20 -10

CURRENT

(mA)

6.5

5.5

4.5

3.5

Regulator Powerdown Supply Current vs.

Temperature and V

BATT

7.5V

Temperature (

-50 -40

-30

-20 -10

CURRENT

(

3.3V

5.5V

Regulator Load Regulation vs.

Temperature and V

BATT

7.5V

ILoad = 15mA to 30mA

Temperature (

-50 -40

-30

-20 -10

REGULA

TION (%)

0.8

0.6

0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1

3.3V

5.5V

Regulator Line Regulation vs.

Temperature and V

BATT

LOAD

=15mA

Temperature (

-50 -40

-30

-20 -10

0.4

REGULA

TION (%)

0.3

0.2

0.1

-0.1

-0.2

-0.3

-0.4

7.5V

5.5V

3.3V

Regulator Output Voltage vs.

Temperature and V

BATT

7.5V

LOAD

=15ma

Temperature (

-50 -40

-30

-20 -10

3.15

VOL

AGE (V)

5.5V

3.3V

3.1

3.05

2.95

2.9

2.85

Figure 10. Typical Performance Characteristics

Philips Semiconductors

Product specification

SA1638

Low voltage IF I/Q transceiver

1997 Sept 03

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Transmitter Input Modulation Bandwidth vs.

Temperature and V

TxRx

ITXIN=ITXINX=QTXIN=QTXINX=1.5Vpp

Temperature (

-50

-30

-10

1100.0

FREQUENCY

(kHz)

1050.0

1000.0

950.0

900.0

850.0

800.0

2.7V

5.5V

4.0V
3.0V

Transmitter Output Second Harmonic Distortion

5.5V

2.7V

Temperature (

-50

SECOND HARMONIC LEVEL

(dBc)

-50

100

-55

-60

-65

-70

Tx In = 1.5V

P-P

Transmitter Output Third Harmonic vs.

Temperature and V

TxRx

=1.5V

P-P

Temperature (

-50

-30

-10

-50

DIST

TION LEVEL

(dBc)

-55

-60

-65

-70

5.5V

2.7V

5.5V

2.7V

Temperature (

-60

FOUR

TH HARMONIC LEVEL

(dBc)

-50

100

Tx In = 1.5V

P-P

-65

-70

-75

-80

Transmitter Output Fifth Harmonic Distortion

5.5V

Temperature (

-60

FIFTH HARMONIC LEVEL

(dBc)

-50

100

Tx In = 1.5V

P-P

-65

-70

-75

-80

Transmitter Output Fourth Harmonic Distortion

Figure 11. Typical Performance Characteristics (continued)

Philips Semiconductors

Product specification

SA1638

Low voltage IF I/Q transceiver

1997 Sept 03

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Transmitter Output Saturation vs.

Temperature and VccTxRx

3.0V

2.7V

4.0V

5.5V

Temperature (

-50 -40

-30

-20 -10

-50

5th HARMONIC DIST

TION LEVEL

(dBc) -52

-54

-56

-58

-60

-62

-64

-66

-68

-70

TXIFOUT=TXIFOUTX=VccTxRx0.3V

Transmitter RMS Output Current

vs. Temperature and V

TxRx

5.5V

4.0V

3.0V

2.7V

IF=400MHz

Temperature (

-50 -40

-30

-20 -10

1.1

RMS CURRENT

(mA)

1.05

0.95

0.9

0.85

0.8

0.75

0.7

0.65

0.6

Transmitter DC Output Current vs.

Temperature and V

TxRx

2.7V

3.0V

5.5V

4.0V

Temperature (

-50 -40

-30

-20 -10

2.5

CURRENT

(mA)

2.4

2.3

2.2

2.1

1.9

1.8

1.7

1.6

1.5

Transmitter LO Suppression vs.

Temperature and VccTxRx

5.5V

4.0V

3.0V

2.7V

Temperature (

-50 -40

-30

-20 -10

-36.0

SUPPRESSION (dBc)

-38.0

-40.0

-42.0

-44.0

-46.0

-48.0

-50.0

Transmitter Side Band Suppresion vs.

TxRx and Temperature

2.7V

5.5V

4.0V

3.0V

Temperature (

-50 -40

-30

-20 -10

-35

SUPPRESSION (dBc)

-40

-45

-50

-55

-60

-65

-70

Transmit Noise Floor vs Temperature and Supply Voltage

10MHz from Carrier

600kHz from Carrier

2.7V

5.5V

2.7V

5.5V

Temperature (

-50 -40

-30

-20 -10

-136

OUTPUT NOISE (dBc/Hz)

-135

-134

-133

-132

-131

-130

-129

-128

-127

-126

Baseband Input = 1.5V

P-P

differential, 30kHz

Figure 12. Typical Performance Characteristics (continued)

Philips Semiconductors

Product specification

SA1638

Low voltage IF I/Q transceiver

1997 Sept 03

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Transmitter Input Common Mode Range

Vs. Supply Voltage

T = +25

4.0V

2.7V

5.5V

3.0V

-20

-40

-60

-80

COMMON MODE VOLTAGE

5th HARMONIC dBc

Receiver 3dB Bandwidth vs. Temperature and V

TxRx

2.7V

3.0V

5.5V

4.0V

Temperature (

-50 -40

-30

-20 -10

100.0

FREQUENCY

(kHz)

90.0

80.0

70.0

60.0

50.0

40.0

Receiver NF vs Temperature and Supply Voltage

Relative to 1200

source resistance

2.7V

5.5V

Temperature (

-50 -40

-30

-20 -10

NF (dB)

2.7V

4.0V

3.0V

5.5V

Temperature (

-50 -40

-30

-20 -10

TCH (dB)

0.8

0.6

0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1

Receiver Gain match vs V

TxRx and Temperature

Receiver Channel Matching Phase Error

vs. Temperature and V

TxRx

5.5V

2.7V

3.0V

4.0V

Temperature (

-50 -40

-30

-20 -10

ERROR ( )

-1

-2

-3

-4

-5

Receiver Gain vs. Temperature and V

TxRx

5.5V

4.0V

3.0V

2.7V

IF=400.005MHz, LO=400MHz

Temperature (

-50 -40

-30

-20 -10

60.0

GAIN (dB)

58.0

56.0

54.0

52.0

50.0

48.0

46.0

44.0

42.0

40.0

Figure 13. Typical Performance Characteristics (continued)

Philips Semiconductors

Product specification

SA1638

Low voltage IF I/Q transceiver

1997 Sept 03

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Receiver Corrected Output Offset Voltage

vs. Temperature and V

TxRx

5.5V

4.0V

3.0V

2.7V

DCRes Resistor=100k

Temperature (

-50 -40

-30

-20 -10

200

OFFSET (mV)

150

100

-50

-100

-150

-200

Receiver Inband 1dB Compression Point

vs. Temperature and V

TxRx

2.7V

5.5V

3.0V
4.0V

Temperature (

-50 -40

-30

-20 -10

-47.0

LEVEL

(dBm)

-49.0

-51.0

-53.0

-55.0

-57.0

-59.0

SA1638 Receiver QRXOUT Voltage

5.5V

2.7V

-50

100

TEMPERATURE (

PIN 15 DC VOL

AGE (V)

1.8

1.7

1.6

1.5

1.4

Reference Voltage

5.5V

2.7V

-50

100

TEMPERATURE (

VREF (V)

1.8

1.7

1.6

1.5

1.45

1.75

1.65

1.55

Maximum Frequency Div800

5.5V

2.7V

-50

100

TEMPERATURE (

FREQUENCY

(MHz)

1100

1050

1000

950

900

2.7V

5.5V

Temperature (

-50 -40

-30

-20 -10

IP2 (dBm)

Receiver IP2 vs Temperature and Supply Voltage

5.00

4.00

3.00

2.00

1.00

-1.00

-2.00

-3.00

-4.00

-5.00

LOIN

= 100mV

PEAK

Figure 14. Typical Performance Characteristics (continued)

Philips Semiconductors

Product specification

SA1638

Low voltage IF I/Q transceiver

1997 Sept 03

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

CLK

Maximum Frequency Div52

5.5V

2.7V

-50

100

TEMPERATURE (

FREQUENCY

(MHz)

250

225

200

175

150

N Charge Pump

Output Current 000

5.5V

2.7V

-50

100

TEMPERATURE (

CURRENT

(

-495

-500

-505

-510

-515

-520

-525

P Charge Pump

Output Current 111

5.5V

2.7V

-50

100

TEMPERATURE (

-1000

-1010

-1020

-1030

-1040

-1050

-1060

N Charge Pump Relative

Output Variation

5.5V

2.7V

-50

100

TEMPERATURE (

ARIA

TION (%)

1.25

0.75

0.5

0.25

Charge Pump Match

Current 111

5.5V

2.7V

-50

100

TEMPERATURE (

-20

-30

-40

-50

-60

Charge Pump Output Leakage Current

5.5V

2.7V

-50

100

TEMPERATURE (

0.25

CURRENT

(nA)

-0.25

-0.5

-0.75

CURRENT

(

CURRENT

(

CLKIN

= 100mV

PEAK

Figure 15. Typical Performance Characteristics (continued)

Philips Semiconductors

Product specification

SA1638

Low voltage IF I/Q transceiver

1997 Sept 03

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Receiver Supply Current vs.

Temperature and V

TxRx

Temperature (

-50 -40

-30

-20 -10

CURRENT

(mA)

Power Down Supply Current vs.

Temperature and V

TxRx

5.5V

Temperature (

-50 -40

-30

-20 -10

160

140

120

100

Transmitter Supply Current vs.

Temperature and V

TxRx

Temperature (

-50 -40

-30

-20 -10

CURRENT

(mA)

4.0V

3.0V

2.7V

5.5V

4.0V

3.0V

2.7V

5.5V

4.0V

3.0V

2.7V

CURRENT

(

270

265

260

255

250

245

240

-50

-30

-10

VOL

AGE (mV)

TEMPERATURE (

Receiver Uncorrected Output Offset

Voltage vs Temperature and V

TxRx

DCRES = 100k

2.7V

3.0V

4.0V

5.5V

330

-50

-30

-10

VOL

AGE (mV)

TEMPERATURE (

Receiver Output Offset Control Step

Size vs Temperature and V

TxRx

DCRES = 100k

2.7V

3.0V

4.0V

5.5V

320

310

300

290

280

-50

-30

-10

VOL

AGE (mV)

TEMPERATURE (

Receiver Output Offset Control Step Size vs

Temperature and V

TxRx

DCRES = 1M

2.7V

3.0V

4.0V

5.5V

Figure 16. Typical Performance Characteristics (continued)

Philips Semiconductors

Product specification

SA1638

Low voltage IF I/Q transceiver

1997 Sept 03

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381

Date of release: 08-98

Document order number:

9397 750 06847

Philips

Semiconductors

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

[1]

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

Data sheet status

[1]

Please consult the most recently issued datasheet before initiating or completing a design.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SA1638

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