Philips Semiconductors RF Communications Products
Product specification
NE/SA572
Programmable analog compandor
2
October 7, 1987
853-0813 90829
DESCRIPTION
The NE572 is a dual-channel,
high-performance gain control circuit in which
either channel may be used for dynamic
range compression or expansion. Each
channel has a full-wave rectifier to detect the
average value of input signal, a linearized,
temperature-compensated variable gain cell
(
G) and a dynamic time constant buffer. The
buffer permits independent control of
dynamic attack and recovery time with
minimum external components and improved
low frequency gain control ripple distortion
over previous compandors.
The NE572 is intended for noise reduction in
high-performance audio systems. It can also
be used in a wide range of communication
systems and video recording applications.
FEATURES
Independent control of attack and recovery
time
Improved low frequency gain control ripple
Complementary gain compression and
expansion with external op amp
Wide dynamic range--greater than 110dB
Temperature-compensated gain control
Low distortion gain cell
Low noise--6
V typical
Wide supply voltage range--6V-22V
System level adjustable with external
components
APPLICATIONS
Dynamic noise reduction system
Voltage control amplifier
Stereo expandor
Automatic level control
High-level limiter
Low-level noise gate
State variable filter
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
D
1
, N, F Packages
TRACK TRIM A
RECOV. CAP A
RECT. IN A
ATTACK CAP A
THD TRIM A
GND
G OUT A
G IN A
TRACK TRIM B
RECOV. CAP B
RECT. IN B
ATTACK CAP B
THD TRIM B
G OUT B
G IN B
VCC
NOTE:
1. D package released in large SO (SOL) package
only.
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
DWG #
16-Pin Plastic Small Outline (SO)
0 to +70
C
NE572D
0005
16-Pin Plastic Dual In-Line Package (DIP)
0 to +70
C
NE572N
0406
16-Pin Plastic Small Outline (SO)
40 to +85
C
SA572D
0005
16-Pin Ceramic Dual In-Line Package (Cerdip)
40 to +85
C
SA572F
0582
16-Pin Plastic Dual In-Line Package (DIP)
40 to +85
C
SA572N
0406
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
V
CC
Supply voltage
22
V
DC
T
A
Operating temperature range
NE572
0 to +70
C
SA572
40 to +85
P
D
Power dissipation
500
mW
Philips Semiconductors RF Communications Products
Product specification
NE/SA572
Programmable analog compandor
October 7, 1987
3
BLOCK DIAGRAM
(7,9)
(6,10)
(3,13)
(16)
(8)
(4,12)
(2,14)
(1,15)
(5,11)
GAIN CELL
RECTIFIER
P.S.
6.8k
10k
BUFFER
10k
270
500
R1
G
+
+
DC ELECTRICAL CHARACTERISTICS
Standard test conditions (unless otherwise noted) V
CC
=15V, T
A
=25
C;
Expandor mode (see Test Circuit). Input signals at unity gain level (0dB)
= 100mV
RMS
at 1kHz; V
1
= V
2
; R
2
= 3.3k
; R
3
= 17.3k
.
SYMBOL
PARAMETER
TEST CONDITIONS
NE572
SA572
UNIT
Min
Typ
Max
Min
Typ
Max
V
CC
Supply voltage
6
22
6
22
V
DC
I
CC
Supply current
No signal
6
6.3
mA
V
R
Internal voltage reference
2.3
2.5
2.7
2.3
2.5
2.7
V
DC
THD
Total harmonic distortion
(untrimmed)
1kHz C
A
=1.0
F
0.2
1.0
0.2
1.0
%
THD
Total harmonic distortion
(trimmed)
1kHz C
R
=10
F
0.05
0.05
%
THD
Total harmonic distortion
(trimmed)
100Hz
0.25
0.25
%
No signal output noise
Input to V
1
and V
2
grounded
(2020kHz)
6
25
6
25
V
DC level shift (untrimmed)
Input change from no signal to
100mV
RMS
20
50
20
50
mV
Unity gain level
1
0
+1
1.5
0
+1.5
dB
Largesignal distortion
V
1
=V
2
=400mV
0.7
3.0
0.7
3
%
Tracking error (measured
relative to value at unity
Rectifier input
gain)=
V
2
=+6dB V
1
=0dB
0.2
0.2
[V
O
V
O
(unity gain)]dB
V
2
=30dB V
1
=0dB
0.5
1.5
0.5
2.5
dB
V
2
dB
+0.8
+1.6
Channel crosstalk
200mV
RMS
into channel A, measured
output on channel B
60
60
dB
PSRR
Power supply rejection ra-
tio
120Hz
70
70
dB
Philips Semiconductors RF Communications Products
Product specification
NE/SA572
Programmable analog compandor
October 7, 1987
4
TEST CIRCUIT
BUFFER
RECTIFIER
NE5234
+15V
15V
(7,9)
(2,14)
(4,12)
6.8k
(5,11)
(6,10)
(8)
(1,15)
(16)
3.3k
(3,13)
G
V1
V2
V0
270pF
82k
2.2k
17.3k
1%
2.2
F
22
F
2.2
F
22
F
.1
F
1
F
2.2
F
5
= 10
F
R3
1%
R2
100
1k
+
+
+
+
AUDIO SIGNAL PROCESSING IC
COMBINES VCA AND FAST AT-
TACK/SLOW RECOVERY LEVEL
SENSOR
In high-performance audio gain control
applications, it is desirable to independently
control the attack and recovery time of the
gain control signal. This is true, for example,
in compandor applications for noise
reduction. In high end systems the input
signal is usually split into two or more
frequency bands to optimize the dynamic
behavior for each band. This reduces low
frequency distortion due to control signal
ripple, phase distortion, high frequency
channel overload and noise modulation.
Because of the expense in hardware, multiple
band signal processing up to now was limited
to professional audio applications.
With the introduction of the Signetics NE572
this high-performance noise reduction
concept becomes feasible for consumer hi fi
applications. The NE572 is a dual channel
gain control IC. Each channel has a
linearized, temperature-compensated gain
cell and an improved level sensor. In
conjunction with an external low noise op
amp for current-to-voltage conversion, the
VCA features low distortion, low noise and
wide dynamic range.
The novel level sensor which provides gain
control current for the VCA gives lower gain
control ripple and independent control of fast
attack, slow recovery dynamic response. An
attack capacitor C
A
with an internal 10k
resistor R
A
defines the attack time t
A
. The
recovery time t
R
of a tone burst is defined by
a recovery capacitor C
R
and an internal 10k
resistor R
R
. Typical attack time of 4ms for
the high-frequency spectrum and 40ms for
the low frequency band can be obtained with
0.1
F and 1.0
F attack capacitors,
respectively. Recovery time of 200ms can be
obtained with a 4.7
F recovery capacitor for
a 100Hz signal, the third harmonic distortion
is improved by more than 10dB over the
simple RC ripple filter with a single 1.0
F
attack and recovery capacitor, while the
attack time remains the same.
The NE572 is assembled in a standard
16-pin dual in-line plastic package and in
oversized SOL package. It operates over a
wide supply range from 6V to 22V. Supply
current is less than 6mA. The NE572 is
designed for consumer application over a
temperature range 0-70
The SA572 is
intended for applications from 40
C to
+85
C.
NE572 BASIC APPLICATIONS
Description
The NE572 consists of two linearized,
temperature-compensated gain cells (
G),
each with a full-wave rectifier and a buffer
amplifier as shown in the block diagram. The
two channels share a 2.5V common bias
reference derived from the power supply but
otherwise operate independently. Because of
inherent low distortion, low noise and the
capability to linearize large signals, a wide
dynamic range can be obtained. The buffer
amplifiers are provided to permit control of
attack time and recovery time independent of
each other. Partitioned as shown in the block
diagram, the IC allows flexibility in the design
of system levels that optimize DC shift, ripple
distortion, tracking accuracy and noise floor
for a wide range of application requirements.
Gain Cell
Figure 1 shows the circuit configuration of the
gain cell. Bases of the differential pairs Q
1
-Q
2
and Q
3
-Q
4
are both tied to the output and
inputs of OPA A
1
. The negative feedback
through Q
1
holds the V
BE
of Q
1
-Q
2
and the
V
BE
of Q
3
-Q
4
equal. The following
relationship can be derived from the
transistor model equation in the forward
active region.
D
V
BE
Q3Q4
+ D
BE
Q1Q2
(V
BE
= V
T
I
IN
IC/IS)
VREF
THD
TRIM
V+
R1
6.8k
1
2
I
G
)
1
2
I
O
I1
140
A
280
A
I2
IG
IO
Q4
Q3
Q1
Q2
VIN
+
A1
Figure 1. Basic Gain Cell Schematic
Philips Semiconductors RF Communications Products
Product specification
NE/SA572
Programmable analog compandor
October 7, 1987
5
V
T
I
n
1
2
I
G
)
1
2
I
O
I
S
*
V
T
I
n
1
2
I
G
*
1
2
I
O
I
S
where I
IN
+
V
IN
R
1
R
1
= 6.8k
I
1
= 140
A
I
2
= 280
A
V
T
I
n
I
1
)
I
IN
I
S
*
V
T
I
n
I
2
*
I
1
*
I
IN
I
S
(2)
where I
IN
+
V
IN
R
1
R
1
= 6.8k
I
1
= 140
A
I
2
= 280
A
I
O
is the differential output current of the gain
cell and I
G
is the gain control current of the
gain cell.
If all transistors Q
1
through Q
4
are of the
same size, equation (2) can be simplified to:
I
O
+
2
I
2
@ I
IN
@ I
G
*
1
I
2
I
2
* 2I
1
@ I
G
(3)
The first term of Equation 3 shows the
multiplier relationship of a linearized two
quadrant transconductance amplifier. The
second term is the gain control feedthrough
due to the mismatch of devices. In the
design, this has been minimized by large
matched devices and careful layout. Offset
voltage is caused by the device mismatch
and it leads to even harmonic distortion. The
offset voltage can be trimmed out by feeding
a current source within
25
A into the THD
trim pin.
The residual distortion is third harmonic
distortion and is caused by gain control
ripple. In a compandor system, available
control of fast attack and slow recovery
improve ripple distortion significantly. At the
unity gain level of 100mV, the gain cell gives
THD (total harmonic distortion) of 0.17% typ.
Output noise with no input signals is only 6
V
in the audio spectrum (10Hz-20kHz). The
output current I
O
must feed the virtual ground
input of an operational amplifier with a
resistor from output to inverting input. The
non-inverting input of the operational
amplifier has to be biased at V
REF
if the
output current I
O
is DC coupled.
Rectifier
The rectifier is a full-wave design as shown in
Figure 2. The input voltage is converted to
current through the input resistor R
2
and
turns on either Q
5
or Q
6
depending on the
signal polarity. Deadband of the voltage to
current converter is reduced by the loop gain
of the gain block A
2
. If AC coupling is used,
the rectifier error comes only from input bias
current of gain block A
2
. The input bias
current is typically about 70nA. Frequency
response of the gain block A
2
also causes
second-order error at high frequency. The
collector current of Q
6
is mirrored and
summed at the collector of Q
5
to form the full
wave rectified output current I
R
. The rectifier
transfer function is
I
R
+
V
IN
*
V
REF
R
2
(4)
If V
IN
is AC-coupled, then the equation will be
reduced to:
I
RAC
+
V
IN
(
AVG)
R
2
The internal bias scheme limits the maximum
output current I
R
to be around 300
A. Within a
1dB error band the input range of the rectifier
is about 52dB.
VIN
VREF
V+
A2
+
R2
Q6
Q5
D7
I
R
+
V
IN
*
V
REF
R
2
Figure 2. Simplified Rectifier Schematic
Q8
Q9
Q10
Q17
X2
Q16
X2
Q18
10k
D13
Q14
CR
D15
A3
10k
D11
D12
CA
TRACKING
TRIM
IR1
IR2
IQ
=
2IR2
V+
I
R
+
V
IN
R
+
Figure 3. Buffer Amplifier Schematic
Philips Semiconductors RF Communications Products
Product specification
NE/SA572
Programmable analog compandor
October 7, 1987
6
Buffer Amplifier
In audio systems, it is desirable to have fast
attack time and slow recovery time for a tone
burst input. The fast attack time reduces
transient channel overload but also causes
low-frequency ripple distortion. The
low-frequency ripple distortion can be
improved with the slow recovery time. If
different attack times are implemented in
corresponding frequency spectrums in a split
band audio system, high quality performance
can be achieved. The buffer amplifier is
designed to make this feature available with
minimum external components. Referring to
Figure 3, the rectifier output current is
mirrored into the input and output of the
unipolar buffer amplifier A
3
through Q
8
, Q
9
and Q
10
. Diodes D
11
and D
12
improve
tracking accuracy and provide
common-mode bias for A
3
. For a
positive-going input signal, the buffer
amplifier acts like a voltage-follower.
Therefore, the output impedance of A
3
makes
the contribution of capacitor CR to attack time
insignificant. Neglecting diode impedance,
the gain Ga(t) for
G can be expressed as
follows:
Ga(t)
+ (Ga
INT
*
Ga
FNL
e
* t
t
A
)
Ga
FNL
Ga
INT
=Initial Gain
Ga
FNL
=Final Gain
A
=R
A
CA=10k
CA
where
A
is the attack time constant and R
A
is a 10k internal resistor. Diode D
15
opens
the feedback loop of A
3
for a negative-going
signal if the value of capacitor CR is larger
than capacitor CA. The recovery time
depends only on CR
R
R
. If the diode
impedance is assumed negligible, the
dynamic gain G
R
(t) for
G is expressed as
follows.
G
R
(
t)
+
(
G
RINT
*
G
RFNL
e
*
t
t
R
)
G
RFNL
G
R
(t)=(G
R INT
G
R FNL
) e +G
R FNL
R=R
R
CR=10k
CR
where
R is the recovery time constant and
R
R
is a 10k internal resistor. The gain control
current is mirrored to the gain cell through
Q
14
. The low level gain errors due to input
bias current of A
2
and A
3
can be trimmed
through the tracking trim pin into A
3
with a
current source of
3
A.
Basic Expandor
Figure 4 shows an application of the circuit as
a simple expandor. The gain expression of
the system is given by
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