SC16C550

Universal Asynchronous Receiver/Transmitter (UART)
with 16-byte FIFO and infrared (IrDA) encoder/decoder

Rev. 05 -- 19 June 2003

Product data

General description

The SC16C550 is a Universal Asynchronous Receiver and Transmitter (UART) used
for serial data communications. Its principal function is to convert parallel data into
serial data, and vice versa. The UART can handle serial data rates up to 3 Mbits/s.

The SC16C550 is pin compatible with the ST16C550, TL16C550 and PC16C550,
and it will power-up to be functionally equivalent to the 16C450. Programming of
control registers enables the added features of the SC16C550. Some of these added
features are the 16-byte receive and transmit FIFOs, automatic hardware or software
flow control and Infrared encoding/decoding. The selectable auto-flow control feature
significantly reduces software overload and increases system efficiency while in FIFO
mode by automatically controlling serial data flow using RTS output and CTS input
signals. The SC16C550 also provides DMA mode data transfers through FIFO trigger
levels and the TXRDY and RXRDY signals. On-board status registers provide the
user with error indications, operational status, and modem interface control. System
interrupts may be tailored to meet user requirements. An internal loop-back capability
allows on-board diagnostics.

The SC16C550 operates at 5 V, 3.3 V and 2.5 V, and the Industrial temperature
range, and is available in plastic DIP40, PLCC44 and LQFP48 packages.

Features

5 V, 3.3 V and 2.5 V operation

Industrial temperature range

After reset, all registers are identical to the typical 16C450 register set

Capable of running with all existing generic 16C450 software

Pin compatibility with the industry-standard ST16C450/550, TL16C450/550,
PC16C450/550

Up to 3 Mbits/s transmit/receive operation at 5 V, 2 Mbits/s at 3.3 V, and
1 Mbit/s at 2.5 V

16 byte transmit FIFO

16 byte receive FIFO with error flags

Programmable auto-RTS and auto-CTS

In auto-CTS mode, CTS controls transmitter

In auto-RTS mode, RxFIFO contents and threshold control RTS

Automatic software/hardware flow control

Programmable Xon/Xoff characters

Software selectable Baud Rate Generator

Four selectable Receive FIFO interrupt trigger levels

Philips Semiconductors

SC16C550

UART with 16-byte FIFO and IrDA encoder/decoder

Product data

Rev. 05 -- 19 June 2003

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9397 750 11619

Standard modem interface or infrared IrDA encoder/decoder interface

Sleep mode

Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun
Break)

Independent receiver clock input

Transmit, Receive, Line Status, and Data Set interrupts independently controlled

Fully programmable character formatting:

5-, 6-, 7-, or 8-bit characters

Even-, Odd-, or No-Parity formats

1-, 1

-, or 2-stop bit

Baud generation (DC to 3 Mbit/s)

False start-bit detection

Complete status reporting capabilities

3-State output TTL drive capabilities for bi-directional data bus and control bus

Line Break generation and detection

Internal diagnostic capabilities:

Loop-back controls for communications link fault isolation

Prioritized interrupt system controls

Modem control functions (CTS, RTS, DSR, DTR, RI, DCD).

Ordering information

Table 1:

Ordering information

Industrial: V

= 2.5 V, 3.3 V or 5 V

10%; T

amb

C to +85

Type number

Package

Name

Description

Version

SC16C550IA44

PLCC44

plastic leaded chip carrier; 44 leads

SOT187-2

SC16C550IB48

LQFP48

plastic low profile quad flat package; 48 leads; body 7

1.4 mm

SOT313-2

SC16C550IN40

DIP40

plastic dual in-line package; 40 leads (600 mil)

SOT129-1

Philips Semiconductors

SC16C550

UART with 16-byte FIFO and IrDA encoder/decoder

Product data

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5.2 Pin description

Fig 4.

DIP40.

SC16C550IN40

002aaa091

RCLK

CS0

CS1

BAUDOUT

XTAL1

XTAL2

IOW

VSS

VCC

DCD

DSR

CTS

OUT1

DTR

RTS

OUT2

INT

RXRDY

TXRDY

DDIS

IOR

CS2

Table 2:

Pin description

Symbol

Pin

Type

Description

PLCC44 LQFP48 DIP40

A2-A0

28, 27,
26

Register select. A0-A2 are used during read and write operations to
select the UART register to read from or write to. Refer to

Table 3

for

Address strobe. When AS is active (LOW), A0, A1, and A2 and CS0,
CS1, and CS2 drive the internal select logic directly; when AS is
HIGH, the register select and chip select signals are held at the logic
levels they were in when the LOW-to-HIGH transition of AS occurred.

BAUDOUT

Baud out. BAUDOUT is a 16

clock signal for the transmitter section

of the UART. The clock rate is established by the reference oscillator
frequency divided by a divisor specified in the baud generator divisor
latches. BAUDOUT may also be used for the receiver section by tying
this output to RCLK.

Philips Semiconductors

SC16C550

UART with 16-byte FIFO and IrDA encoder/decoder

Product data

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CS0, CS1,
CS2

14, 15,
16

9, 10,
11

12, 13,
14

Chip select. When CS0 and CS1 are HIGH and CS2 is LOW, these
three inputs select the UART. When any of these inputs are inactive,
the UART remains inactive (refer to AS description).

CTS

Clear to send. CTS is a modem status signal. Its condition can be
checked by reading bit 4 (CTS) of the modem status register. Bit 0
(CTS) of the modem status register indicates that CTS has changed
states since the last read from the modem status register. If the
modem status interrupt is enabled when CTS changes levels and the
auto-CTS mode is not enabled, an interrupt is generated. CTS is also
used in the auto-CTS mode to control the transmitter.

D7-D0

2-9

43-47,
2-4

8-1

I/O

Data bus. Eight data lines with 3-State outputs provide a bi-directional
path for data, control and status information between the UART and
the CPU.

DCD

Data carrier detect. DCD is a modem status signal. Its condition can
be checked by reading bit 7 (DCD) of the modem status register. Bit 3
(DCD) of the modem status register indicates that DCD has changed
states since the last read from the modem status register. If the
modem status interrupt is enabled when DCD changes levels, an
interrupt is generated.

DDIS

Driver disable. DDIS is active (LOW) when the CPU is not reading
data. When active, DDIS can disable an external transceiver.

DSR

Data set ready. DSR is a modem status signal. Its condition can be
checked by reading bit 5 (DSR) of the modem status register. Bit 1
(DSR) of the modem status register indicates DSR has changed levels
since the last read from the modem status register. If the modem
status interrupt is enabled when DSR changes levels, an interrupt is
generated.

DTR

Data terminal ready. When active (LOW), DTR informs a modem or
data set that the UART is ready to establish communication. DTR is
placed in the active level by setting the DTR bit of the modem control
register. DTR is placed in the inactive level either as a result of a
Master Reset, during loop mode operation, or clearing the DTR bit.

INT

Interrupt. When active (HIGH), INT informs the CPU that the UART
has an interrupt to be serviced. Four conditions that cause an interrupt
to be issued are: a receiver error, received data that is available or
timed out (FIFO mode only), an empty transmitter holding register or
an enabled modem status interrupt. INT is reset (deactivated) either
when the interrupt is serviced or as a result of a Master Reset.

Master Reset. When active (HIGH), MR clears most UART registers
and sets the levels of various output signals.

1, 12,
23, 34

1, 5, 13,
21, 25,
36, 37,
48

Not connected.

OUT1, OUT2 38, 35

34, 31

Outputs 1 and 2. These are user-designated output terminals that are
set to the active (low) level by setting respective modem control
register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2 are set to
inactive the (HIGH) level as a result of Master Reset, during loop mode
operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR.

Table 2:

Pin description

...continued

Symbol

Pin

Type

Description

PLCC44 LQFP48 DIP40

Philips Semiconductors

SC16C550

UART with 16-byte FIFO and IrDA encoder/decoder

Product data

Rev. 05 -- 19 June 2003

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RCLK

Receiver clock. RCLK is the 16

baud rate clock for the receiver

section of the UART.

IOR, IOR

24, 25

19, 20

21, 22

Read inputs. When either IOR or IOR is active (LOW or HIGH,
respectively) while the UART is selected, the CPU is allowed to read
status information or data from a selected UART register. Only one of
these inputs is required for the transfer of data during a read operation;
the other input should be tied to its inactive level (i.e., IOR tied LOW or
IOR tied HIGH).

Ring indicator. RI is a modem status signal. Its condition can be
checked by reading bit 6 (RI) of the modem status register. Bit 2
(TERI) of the modem status register indicates that RI has transitioned
from a LOW to a HIGH level since the last read from the modem status
register. If the modem status interrupt is enabled when this transition
occurs, an interrupt is generated.

RTS

Request to send. When active, RTS informs the modem or data set
that the UART is ready to receive data. RTS is set to the active level by
setting the RTS modem control register bit and is set to the inactive
(HIGH) level either as a result of a Master Reset or during loop mode
operations or by clearing bit 1 (RTS) of the MCR. In the auto-RTS
mode, RTS is set to the inactive level by the receiver threshold control
logic.

RXRDY

Receiver ready. Receiver direct memory access (DMA) signaling is
available with RXRDY. When operating in the FIFO mode, one of two
types of DMA signaling can be selected using the FIFO control register
bit 3 (FCR[3]). When operating in the 16C450 mode, only DMA
mode 0 is allowed. Mode 0 supports single-transfer DMA in which a
transfer is made between CPU bus cycles. Mode 1 supports
multi-transfer DMA in which multiple transfers are made continuously
until the receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0
or FCR0 = 1, FCR3 = 0), when there is at least one character in the
receiver FIFO or receiver holding register, RXRDY is active (LOW).
When RXRDY has been active but there are no characters in the FIFO
or holding register, RXRDY goes inactive (HIGH). In DMA mode 1
(FCR0 = 1, FCR3 = 1), when the trigger level or the time-out has been
reached, RXRDY goes active (LOW); when it has been active but there
are no more characters in the FIFO or holding register, it goes inactive
(HIGH).

Serial data input. RX is serial data input from a connected
communications device.

Serial data output. TX is composite serial data output to a connected
communication device. TX is set to the marking (HIGH) level as a
result of Master Reset.

TXRDY

Transmitter ready. Transmitter DMA signaling is available with
TXRDY. When operating in the FIFO mode, one of two types of DMA
signaling can be selected using FCR[3]. When operating in the
16C450 mode, only DMA mode 0 is allowed. Mode 0 supports
single-transfer DMA in which a transfer is made between CPU bus
cycles. Mode 1 supports multi-transfer DMA in which multiple transfers
are made continuously until the transmit FIFO has been filled.

Table 2:

Pin description

...continued

Symbol

Pin

Type

Description

PLCC44 LQFP48 DIP40

Philips Semiconductors

SC16C550

UART with 16-byte FIFO and IrDA encoder/decoder

Product data

Rev. 05 -- 19 June 2003

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9397 750 11619

[1]

In sleep mode, XTAL2 is left floating.

Functional description

The SC16C550 provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data
stream into parallel data that is required with digital data systems. Synchronization for
the serial data stream is accomplished by adding start and stop bits to the transmit
data to form a data character (character orientated protocol). Data integrity is insured
by attaching a parity bit to the data character. The parity bit is checked by the receiver
for any transmission bit errors. The SC16C550 is fabricated with an advanced CMOS
process to achieve low drain power and high speed requirements.

The SC16C550 is an upward solution that provides 16 bytes of transmit and receive
FIFO memory, instead of none in the 16C450. The SC16C550 is designed to work
with high speed modems and shared network environments that require fast data
processing time. Increased performance is realized in the SC16C550 by the larger
transmit and receive FIFOs. This allows the external processor to handle more
networking tasks within a given time. In addition, the four selectable levels of FIFO
trigger interrupt and automatic hardware/software flow control is uniquely provided for
maximum data throughput performance, especially when operating in a multi-channel
environment. The combination of the above greatly reduces the bandwidth
requirement of the external controlling CPU, increases performance, and reduces
power consumption.

The SC16C550 is capable of operation up to 3 Mbits/s with a 48 MHz external clock
input (at 5 V).

The rich feature set of the SC16C550 is available through internal registers.
Automatic hardware/software flow control, selectable receive FIFO trigger level,
selectable TX and RX baud rates, infrared encoder/decoder interface, modem
interface controls, and a sleep mode are some of these features. MCR[5] provides an
efficient hardware auto-flow control.

Power 2.5 V, 3.3 V or 5 V supply voltage.

Power Ground voltage.

IOW, IOW

20, 21

16, 17

18, 19

Write inputs. When either IOW or IOW is active (LOW or HIGH,
respectively) and while the UART is selected, the CPU is allowed to
write control words or data into a selected UART register. Only one of
these inputs is required to transfer data during a write operation; the
other input should be tied to its inactive level (i.e., IOW tied LOW or
IOW tied HIGH).

XTAL1

Crystal connection or External clock input.

XTAL2

[1]

Crystal connection or the inversion of XTAL1 if XTAL1 is driven.

Table 2:

Pin description

...continued

Symbol

Pin

Type

Description

PLCC44 LQFP48 DIP40

Philips Semiconductors

SC16C550

UART with 16-byte FIFO and IrDA encoder/decoder

Product data

Rev. 05 -- 19 June 2003

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6.1 Internal registers

The SC16C550 provides 15 internal registers for monitoring and control. These
registers are shown in

Table 3

. Twelve registers are similar to those already available

in the standard 16C550. These registers function as data holding registers
(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register
(FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM),
and a user accessible scratchpad register (SPR). Beyond the general 16C550
features and capabilities, the SC16C550 offers an enhanced feature register set
(EFR, Xon/Xoff1-2) that provides on-board hardware/software flow control. Register
functions are more fully described in the following paragraphs.

[1]

These registers are accessible only when LCR[7] is a logic 0.

[2]

These registers are accessible only when LCR[7] is a logic 1.

[3]

Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to
"BF(HEX).

6.2 FIFO operation

The 16-byte transmit and receive data FIFOs are enabled by the FIFO Control
Register bit-0 (FCR[0]). With 16C550 devices, the user can set the receive trigger
level, but not the transmit trigger level. The receiver FIFO section includes a time-out
function to ensure data is delivered to the external CPU. An interrupt is generated
whenever the Receive Holding Register (RHR) has not been read following the
loading of a character or the receive trigger level has not been reached.

Table 3:

Internal registers decoding

READ mode

WRITE mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR/LSR, SPR)

[1]

Receive Holding Register

Transmit Holding Register

Interrupt Enable Register

Interrupt Status Register

FIFO Control Register

Line Control Register

Modem Control Register

Line Status Register

n/a

Modem Status Register

n/a

Scratchpad Register

Baud rate register set (DLL/DLM)

[2]

LSB of Divisor Latch

MSB of Divisor Latch

Enhanced register set (EFR, Xon/off 1-2)

[3]

Enhanced Feature Register

Xon1 word

Xon2 word

Xoff1 word

Xoff2 word

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UART with 16-byte FIFO and IrDA encoder/decoder

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6.3 Autoflow control (see

Figure 5

)

Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS
input must be active before the transmitter FIFO can emit data. With auto-RTS, RTS
becomes active when the receiver needs more data and notifies the sending serial
device. When RTS is connected to CTS, data transmission does not occur unless the
receiver FIFO has space for the data; thus, overrun errors are eliminated using
UART 1 and UART 2 from a SC16C550 with the autoflow control enabled. If not,
overrun errors occur when the transmit data rate exceeds the receiver FIFO read
latency.

6.3.1

Auto-RTS (see

Figure 5

)

Auto-RTS data flow control originates in the receiver timing and control block (see

Figure 1 "Block diagram."

) and is linked to the programmed receiver FIFO trigger

level. When the receiver FIFO level reaches a trigger level of 1, 4, or 8 (see

Figure 7

RTS is de-asserted. With trigger levels of 1, 4, and 8, the sending UART may send an
additional byte after the trigger level is reached (assuming the sending UART has
another byte to send) because it may not recognize the de-assertion of RTS until
after it has begun sending the additional byte. RTS is automatically reasserted once
the RX FIFO is emptied by reading the receiver buffer register. When the trigger level
is 14 (see

Figure 8

), RTS is de-asserted after the first data bit of the 16th character is

present on the RX line. RTS is reasserted when the RX FIFO has at least one
available byte space.

Table 4:

Flow control mechanism

Selected trigger level
(characters)

INT pin activation

Negate RTS or
send Xoff

Assert RTS or
send Xon

Fig 5.

Autoflow control (auto-RTS and auto-CTS) example.

RCV

FIFO

SERIAL TO

PARALLEL

FLOW

CONTROL

XMT

FIFO

PARALLEL

TO SERIAL

FLOW

CONTROL

PARALLEL

TO SERIAL

FLOW

CONTROL

SERIAL TO

PARALLEL

FLOW

XMT

FIFO

RCV

FIFO

ACE1

ACE2

D7 D0

RTS

CTS

D7 D0

CONTROL

002aaa048

CTS

RTS

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UART with 16-byte FIFO and IrDA encoder/decoder

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6.3.2

Auto-CTS (see

Figure 5

)

The transmitter circuitry checks CTS before sending the next data byte. When CTS is
active, it sends the next byte. To stop the transmitter from sending the following byte,
CTS must be released before the middle of the last stop bit that is currently being
sent (see

Figure 6

). The auto-CTS function reduces interrupts to the host system.

When flow control is enabled, CTS level changes do not trigger host interrupts
because the device automatically controls its own transmitter. Without auto-CTS, the
transmitter sends any data present in the transmit FIFO and a receiver overrun error
may result.

6.3.3

Enabling autoflow control and auto-CTS

Autoflow control is enabled by setting Enhanced Feature register bits 6 and 7
(autoflow enable or AFE) to a `1'.

6.3.4

Auto-CTS and auto-RTS functional timing

The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described
in

Figure 7

and

Figure 8

(1) When CTS is LOW, the transmitter keeps sending serial data out.

(2) If CTS goes HIGH before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte,

but is does not send the next byte.

(3) When CTS goes from HIGH to LOW, the transmitter begins sending data again.

Fig 6.

CTS functional timing waveforms.

START

BITS 0-7

START

BITS 0-7

START

BITS 0-7

STOP

CTS

002aaa049

(1) N = RCV FIFO trigger level (1, 4, or 8 bytes).

(2) The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding auto-RTS

section.

Fig 7.

RTS functional timing waveforms, RCV FIFO trigger level = 1, 4, or 8 bytes.

START

BYTE N

START

BYTE N + 1

START

BYTE

STOP

RTS

IOR

(RD RBR)

N+1

002aaa050

Philips Semiconductors

SC16C550

UART with 16-byte FIFO and IrDA encoder/decoder

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6.4 Software flow control

When software flow control is enabled, the SC16C550 compares one or two
sequential receive data characters with the programmed Xon or Xoff character
value(s). If receive character(s) (RX) match the programmed values, the SC16C550
will halt transmission (TX) as soon as the current character(s) has completed
transmission. When a match occurs, the receive ready (if enabled via Xoff IER[5])
flags will be set and the interrupt output pin (if receive interrupt is enabled) will be
activated. Following a suspension due to a match of the Xoff characters' values, the
SC16C550 will monitor the receive data stream for a match to the Xon1,2 character
value(s). If a match is found, the SC16C550 will resume operation and clear the flags
(ISR[4]).

Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow
control. Different conditions can be set to detect Xon/Xoff characters and
suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected,
the SC16C550 compares two consecutive receive characters with two software flow
control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions
accordingly. Under the above described flow control mechanisms, flow control
characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
When using a software flow control the Xon/Xoff characters cannot be used for data
transfer.

In the event that the receive buffer is overfilling and flow control needs to be executed,
the SC16C550 automatically sends an Xoff message (when enabled) via the serial
TX output to the remote modem. The SC16C550 sends the Xoff1,2 characters as
soon as received data passes the programmed trigger level. To clear this condition,
the SC16C550 will transmit the programmed Xon1,2 characters as soon as receive
data drops below the programmed trigger level.

(1) RTS is de-asserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing

the sixteenth byte.

(2) RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing, or there is

more than one byte of space available.

(3) When the receive FIFO is full, the first receive buffer register read re-asserts RTS.

Fig 8.

RTS functional timing waveforms, RCV FIFO trigger level = 14 bytes.

BYTE 14

BYTE 15

RTS

IOR

(RD RBR)

START

BYTE 18

STOP

START

BYTE 16

STOP

RTS RELEASED AFTER THE

FIRST DATA BIT OF BYTE 16

002aaa051

Philips Semiconductors

SC16C550

UART with 16-byte FIFO and IrDA encoder/decoder

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6.5 Special feature software flow control

A special feature is provided to detect an 8-bit character when EFR[5] is set. When
8-bit character is detected, it will be placed on the user-accessible data stack along
with normal incoming RX data. This condition is selected in conjunction with
EFR[0-3]. Note that software flow control should be turned off when using this special
mode by setting EFR[0-3] to a logic 0.

The SC16C550 compares each incoming receive character with Xoff2 data. If a
match exists, the received data will be transferred to the FIFO, and ISR[4] will be set
to indicate detection of a special character. Although

Table 8 "SC16C550 internal

registers"

shows each X-Register with eight bits of character information, the actual

number of bits is dependent on the programmed word length. Line Control Register
bits LCR[0-1] define the number of character bits, i.e., either 5 bits, 6 bits, 7 bits or
8 bits. The word length selected by LCR[0-1] also determine the number of bits that
will be used for the special character comparison. Bit 0 in the X-registers corresponds
with the LSB bit for the receive character.

6.6 Hardware/software and time-out interrupts

Three special interrupts have been added to monitor the hardware and software flow
control. The interrupts are enabled by IER[5-7]. Care must be taken when handling
these interrupts. Following a reset, the transmitter interrupt is enabled, the SC16C550
will issue an interrupt to indicate that the Transmit Holding Register is empty. This
interrupt must be serviced prior to continuing operations. The LSR register provides
the current singular highest priority interrupt only. It could be noted that CTS and RTS
interrupts have lowest interrupt priority. A condition can exist where a higher priority
interrupt may mask the lower priority CTS/RTS interrupt(s). Only after servicing the
higher pending interrupt will the lower priority CTS/TRS interrupt(s) be reflected in the
status register. Servicing the interrupt without investigating further interrupt conditions
can result in data errors.

When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[3]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C550 FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
receive holding register (RHR) is read. The actual time-out value is 4 character time,
including data information length, start bit, parity bit, and the size of stop bit, i.e., 1

1.5

, or 2

bit times.

Philips Semiconductors

SC16C550

UART with 16-byte FIFO and IrDA encoder/decoder

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6.7 Programmable baud rate generator

The SC16C550 supports high speed modem technologies that have increased input
data rates by employing data compression schemes. For example, a 33.6 kbit/s
modem that employs data compression may require a 115.2 kbit/s input data rate.
A 128.0 kbit/s ISDN modem that supports data compression may need an input
data rate of 460.8 kbit/s. The SC16C550 can support a standard data rate of
921.6 kbit/s.

A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generator is
capable of accepting an input clock up to 48 MHz, as required for supporting a
3 Mbits/s data rate. The SC16C550 can be configured for internal or external clock
operation. For internal clock oscillator operation, an industry standard microprocessor
crystal is connected externally between the XTAL1 and XTAL2 pins (see

Figure 9

Alternatively, an external clock can be connected to the XTAL1 pin to clock the
internal baud rate generator for standard or custom rates (see

Table 5

The generator divides the input 16

clock by any divisor from 1 to 2

1. The

SC16C550 divides the basic crystal or external clock by 16. The frequency of the
BAUDOUT output pin is exactly 16

(16 times) of the selected baud rate

(BAUDOUT = 16 Baud Rate). Customized baud rates can be achieved by selecting
the proper divisor values for the MSB and LSB sections of baud rate generator.

Programming the Baud Rate Generator registers DLM (MSB) and DLL (LSB)
provides a user capability for selecting the desired final baud rate. The example in

Table 5

shows selectable baud rates when using a 1.8432 MHz crystal.

For custom baud rates, the divisor value can be calculated using the following
equation:

(1)

Fig 9.

Crystal oscillator connection.

002aaa169

1.8432 MHz

C1
22 pF

C2
47 pF

AL1

AL2

1.8432 MHz

C1
47 pF

C2
100 pF

AL1

AL2

1.5 k

Divisor (in decimal)

XTAL1 clock frequency

serial data rate

-----------------------------------------------------------

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6.8 DMA operation

The SC16C550 FIFO trigger level provides additional flexibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in
the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY
output pins. Tables

and

show this.

Table 5:

Baud rates using 1.8432 MHz or 3.072 MHz crystal

Using 1.8432 MHz crystal

Using 3.072 MHz crystal

Desired
baud rate

Divisor for
16

clock

Baud rate
error

Desired
baud rate

Divisor for
16

clock

Baud rate
error

2304

3840

1536

2560

110

1047

0.026

110

1745

0.026

134.5

857

0.058

134.5

1428

0.034

150

768

150

1280

300

384

300

640

600

192

600

320

1200

160

1800

107

0.312

2000

0.69

2000

2400

3600

0.628

4800

7200

1.23

9600

19200

38400

56000

2.86

Table 6:

Effect of DMA mode on state of RXRDY pin

Non-DMA mode

DMA mode

1 = FIFO empty

0-to-1 transition when FIFO empties

0 = at least 1 byte in FIFO

1-to-0 transition when FIFO reaches trigger level,
or time-out occurs

Table 7:

Effect of DMA mode on state of TXRDY pin

Non-DMA mode

DMA mode

1 = at least 1 byte in FIFO

1 = FIFO is full

0 = FIFO empty

0 = FIFO has at least 1 empty location

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6.9 Sleep mode

The SC16C550 is designed to operate with low power consumption. A special sleep
mode is included to further reduce power consumption when the chip is not being
used. With EFR[4] and IER[4] enabled (set to a logic 1), the SC16C550 enters the
sleep mode, but resumes normal operation when a start bit is detected, a change of
state on any of the modem input pins RX, RI, CTS, DSR, DCD, or a transmit data is
provided by the user. If the sleep mode is enabled and the SC16C550 is awakened by
one of the conditions described above, it will return to the sleep mode automatically
after the last character is transmitted or read by the user. In any case, the sleep mode
will not be entered while an interrupt(s) is pending. The SC16C550 will stay in the
sleep mode of operation until it is disabled by setting IER[4] to a logic 0.

6.10 Loop-back mode

The internal loop-back capability allows on-board diagnostics. In the loop-back mode,
the normal modem interface pins are disconnected and reconfigured for loop-back
internally. MCR[0-3] register bits are used for controlling loop-back diagnostic testing.
In the loop-back mode, OUT1 and OUT2 in the MCR register (bits 3-2) control the
modem RI and DCD inputs, respectively. MCR signals DTR and RTS (bits 0-1) are
used to control the modem CTS and DSR inputs, respectively. The transmitter output
(TX) and the receiver input (RX) are disconnected from their associated interface
pins, and instead are connected together internally (see

Figure 10

). The CTS, DSR,

DCD, and RI are disconnected from their normal modem control input pins, and
instead are connected internally to DTR, RTS, OUT1 and OUT2. Loop-back test data
is entered into the transmit holding register via the user data bus interface, D0-D7.
The transmit UART serializes the data and passes the serial data to the receive
UART via the internal loop-back connection. The receive UART converts the serial
data back into parallel data that is then made available at the user data interface
D0-D7. The user optionally compares the received data to the initial transmitted data
for verifying error-free operation of the UART TX/RX circuits.

In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational. However, the interrupts can only be read
using lower four bits of the Modem Status Register (MSR[0-3]) instead of the four
Modem Status Register bits 4-7. The interrupts are still controlled by the IER.

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Register descriptions

Table 8

details the assigned bit functions for the fifteen SC16C550 internal registers.

The assigned bit functions are more fully defined in

Section 7.1

through

Section 7.11

[1]

The value shown represents the register's initialized HEX value; X = n/a.

[2]

These registers are accessible only when LCR[7] = 0.

[3]

The Special Register set is accessible only when LCR[7] is set to a logic 1.

[4]

Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to `BF

Hex

Table 8:

SC16C550 internal registers

Shaded bits are only accessible when EFR[4] is set.

Register Default

[1]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

General Register Set

[2]

RHR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

THR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

IER

CTS
interrupt

RTS
interrupt

Xoff
interrupt

Sleep
mode

modem
status
interrupt

receive
line status
interrupt

transmit
holding
register

receive
holding
register

FCR

RCVR
trigger
(MSB)

RCVR
trigger
(LSB)

reserved reserved

DMA
mode
select

XMIT
FIFO
reset

RCVR
FIFO
reset

FIFO
enable

ISR

FIFOs
enabled

INT
priority
bit 4

INT
priority
bit 3

INT
priority
bit 2

INT
priority
bit 1

INT
priority
bit 0

INT
status

LCR

divisor
latch
enable

set break set parity even

parity

parity
enable

stop bits

word
length
bit 1

word
length
bit 0

MCR

reserved IR enable reserved loop back OUT2,

INT
enable

OUT1

RTS

DTR

LSR

FIFO
data
error

trans.
empty

trans.
holding
empty

break
interrupt

framing
error

parity
error

overrun
error

receive
data
ready

MSR

DCD

DSR

CTS

DCD

DSR

CTS

SPR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Special Register Set

[3]

DLL

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

DLM

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

Enhanced Register Set

[4]

EFR

Auto
CTS

Auto RTS Special

char.
select

Enable
IER[4-7],
ISR[4,5],
FCR[4,5],
MCR[5-7]

Cont-3
Tx, Rx
Control

Cont-2
Tx, Rx
Control

Cont-1
Tx, Rx
Control

Cont-0
Tx, Rx
Control

Xon-1

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Xon-2

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

Xoff-1

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Xoff-2

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

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7.1 Transmit (THR) and Receive (RHR) Holding Registers

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to
the THR, providing that the THR or TSR is empty. The THR empty flag in the LSR
register will be set to a logic 1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can be performed when the THR
empty flag is set (logic 0 = FIFO full; logic 1 = at least one FIFO location available).

The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive data is removed from the SC16C550 and receive FIFO by reading the RHR
register. The receive section provides a mechanism to prevent false starts. On the
falling edge of a start or false start bit, an internal receiver counter starts counting
clocks at the 16

clock rate. After 7-

clocks, the start bit time should be shifted to

the center of the start bit. At this time the start bit is sampled, and if it is still a logic 0
it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready,
transmitter empty, line status and modem status registers. These interrupts would
normally be seen on the INT output pin.

Table 9:

Interrupt Enable Register bits description

Bit

Symbol

Description

IER[7]

CTS interrupt.

Logic 0 = Disable the CTS interrupt (normal default condition).

Logic 1 = Enable the CTS interrupt. The SC16C550 issues an interrupt
when the CTS pin transitions from a logic 0 to a logic 1.

IER[6]

RTS interrupt.

Logic 0 = Disable the RTS interrupt (normal default condition).

Logic 1 = Enable the RTS interrupt. The SC16C550 issues an interrupt
when the RTS pin transitions from a logic 0 to a logic 1.

IER[5]

Xoff interrupt.

Logic 0 = Disable the software flow control, receive Xoff interrupt
(normal default condition).

Logic 1 = Enable the software flow control, receive Xoff interrupt. See

Section 6.4 "Software flow control"

for details.

IER[4]

Sleep mode.

Logic 0 = Disable sleep mode (normal default condition).

Logic 1 = Enable sleep mode. See

Section 6.9 "Sleep mode"

for details.

IER[3]

Modem Status Interrupt.

Logic 0 = Disable the modem status register interrupt (normal default
condition).

Logic 1 = Enable the modem status register interrupt.

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7.2.1

IER versus Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1)
are enabled, the receive interrupts and register status will reflect the following:

The receive data available interrupts are issued to the external CPU when the
FIFO has reached the programmed trigger level. It will be cleared when the FIFO
drops below the programmed trigger level.

FIFO status will also be reflected in the user accessible ISR register when the
FIFO trigger level is reached. Both the ISR register status bit and the interrupt will
be cleared when the FIFO drops below the trigger level.

The data ready bit (LSR[0]) is set as soon as a character is transferred from the
shift register to the receive FIFO. It is reset when the FIFO is empty.

7.2.2

IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C550 in the FIFO polled
mode of operation. Since the receiver and transmitter have separate bits in the LSR,
either or both can be used in the polled mode by selecting respective transmit or
receive control bit(s).

LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

LSR[1-4] will provide the type of errors encountered, if any.

LSR[5] will indicate when the transmit FIFO is empty.

LSR[6] will indicate when both the transmit FIFO and transmit shift register are
empty.

LSR[7] will indicate any FIFO data errors.

IER[2]

Receive Line Status interrupt. This interrupt will be issued whenever a fully
assembled receive character is transferred from RSR to the RHR/FIFO,
i.e., data ready, LSR[0].

Logic 0 = Disable the receiver line status interrupt (normal default
condition).

Logic 1 = Enable the receiver line status interrupt.

IER[1]

Transmit Holding Register interrupt. This interrupt will be issued whenever
the THR is empty, and is associated with LSR[1].

Logic 0 = Disable the transmitter empty interrupt (normal default
condition).

Logic 1 = Enable the transmitter empty interrupt.

IER[0]

Receive Holding Register interrupt. This interrupt will be issued when the
FIFO has reached the programmed trigger level, or is cleared when the
FIFO drops below the trigger level in the FIFO mode of operation.

Logic 0 = Disable the receiver ready interrupt (normal default condition).

Logic 1 = Enable the receiver ready interrupt.

Table 9:

Interrupt Enable Register bits description

...continued

Bit

Symbol

Description

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7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO
trigger levels, and select the DMA mode.

7.3.1

DMA mode

Mode 0 (FCR bit 3 = `0'):

Set and enable the interrupt for each single transmit or

receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) will
go to a logic 0 whenever an empty transmit space is available in the Transmit Holding
Register (THR). Receive Ready (RXRDY) will go to a logic 0 whenever the Receive
Holding Register (RHR) is loaded with a character.

Mode 1 (FCR bit 3 = `1'):

Set and enable the interrupt in a block mode operation.

The transmit interrupt is set when the transmit FIFO has at least one empty location.
The receive interrupt is set when the receive FIFO fills to the programmed trigger
level. However, the FIFO continues to fill regardless of the programmed level until the
FIFO is full. RXRDY remains a logic 0 as long as the FIFO fill level is above the
programmed trigger level.

7.3.2

FIFO mode

Table 10:

FIFO Control Register bits description

Bit

Symbol

Description

7-6

FCR[7]
(MSB),
FCR[6]
(LSB)

RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.

An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continue to
be loaded until it is full. Refer to

Table 11

5-4

FCR[5]
(MSB),
FCR[4]
(LSB)

Not used; set to 00.

FCR[3]

DMA mode select.

Logic 0 = Set DMA mode `0' (normal default condition).

Logic 1 = Set DMA mode `1'

Transmit operation in mode `0': When the SC16C550 is in the 16C450
mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs
enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no
characters in the transmit FIFO or transmit holding register, the TXRDY
pin will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after
the first character is loaded into the transmit holding register.

Receive operation in mode `0': When the SC16C550 is in 16C450
mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and
there is at least one character in the receive FIFO, the RXRDY pin will
be a logic 0. Once active, the RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.

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Transmit operation in mode `1': When the SC16C550 is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1
when the transmit FIFO is completely full. It will be a logic 0 if one or
more FIFO locations are empty.

Receive operation in mode `1': When the SC16C550 is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been
reached, or a Receive Time-Out has occurred, the RXRDY pin will go to
a logic 0. Once activated, it will go to a logic 1 after there are no more
characters in the FIFO.

FCR[2]

XMIT FIFO reset.

Logic 0 = No FIFO transmit reset (normal default condition).

Logic 1 = Clears the contents of the transmit FIFO and resets the
FIFO counter logic (the transmit shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO.

FCR[1]

RCVR FIFO reset.

Logic 0 = No FIFO receive reset (normal default condition).

Logic 1 = Clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.

FCR[0]

FIFO enable.

Logic 0 = Disable the transmit and receive FIFO (normal default
condition).

Logic 1 = Enable the transmit and receive FIFO. This bit must be a
`1' when other FCR bits are written to, or they will not be
programmed.

Table 11:

RCVR trigger levels

FCR[7]

FCR[6]

RX FIFO trigger level (bytes)

Table 10:

FIFO Control Register bits description

...continued

Bit

Symbol

Description

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7.4 Interrupt Status Register (ISR)

The SC16C550 provides six levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. Whenever the interrupt status register is read,
the interrupt status is cleared. However, it should be noted that only the current
pending interrupt is cleared by the read. A lower level interrupt may be seen after
re-reading the interrupt status bits.

Table 12 "Interrupt source"

shows the data values

(bits 0-5) for the six prioritized interrupt levels and the interrupt sources associated
with each of these interrupt levels.

Table 12:

Interrupt source

Priority
level

ISR[5]

ISR[4]

ISR[3]

ISR[2]

ISR[1]

ISR[0]

Source of the interrupt

LSR (Receiver Line Status
Register)

RXRDY (Received Data
Ready)

RXRDY (Receive Data
time-out)

TXRDY (Transmitter
Holding Register Empty)

MSR (Modem Status
Register)

RXRDY (Received Xoff
signal) / Special character

CTS, RTS change of state

Table 13:

Interrupt Status Register bits description

Bit

Symbol

Description

7-6

ISR[7-6]

FIFOs enabled. These bits are set to a logic 0 when the FIFO is
not being used. They are set to a logic 1 when the FIFOs are
enabled.

Logic 0 or cleared = default condition.

5-4

ISR[5-4]

INT priority bits 4-3. These bits are enabled when EFR[4] is set to
a logic 1. ISR[4] indicates that matching Xoff character(s) have
been detected. ISR[5] indicates that CTS, RTS have been
generated. Note that once set to a logic 1, the ISR[4] bit will stay a
logic 1 until Xon character(s) are received.

Logic 0 or cleared = default condition.

3-1

ISR[3-1]

INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see

Table 12

Logic 0 or cleared = default condition.

ISR[0]

INT status.

Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.

Logic 1 = No interrupt pending (normal default condition).

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7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.

[1]

When LCR[7] = 1, the general register set cannot be accessed until LCR[7] = 0.

Table 14:

Line Control Register bits description

Bit

Symbol

Description

LCR[7]

[1]

Divisor latch enable. The internal baud rate counter latch and Enhance
Feature mode enable.

Logic 0 = Divisor latch disabled (normal default condition).

Logic 1 = Divisor latch and enhanced feature register enabled.

LCR[6]

Set break. When enabled, the Break control bit causes a break condition
to be transmitted (the TX output is forced to a logic 0 state). This
condition exists until disabled by setting LCR[6] to a logic 0.

Logic 0 = no TX break condition (normal default condition).

Logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition.

LCR[5]

Set parity. If the parity bit is enabled, LCR[5] selects the forced parity
format. Programs the parity conditions (see

Table 15

Logic 0 = parity is not forced (normal default condition).

LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1
for the transmit and receive data.

LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0
for the transmit and receive data.

LCR[4]

Even parity. If the parity bit is enabled with LCR[3] set to a logic 1,
LCR[4] selects the even or odd parity format.

Logic 0 = ODD Parity is generated by forcing an odd number of
logic 1s in the transmitted data. The receiver must be programmed to
check the same format (normal default condition).

Logic 1 = EVEN Parity is generated by forcing an even number of
logic 1s in the transmitted data. The receiver must be programmed to
check the same format.

LCR[3]

Parity enable. Parity or no parity can be selected via this bit.

Logic 0 = no parity (normal default condition).

Logic 1 = a parity bit is generated during the transmission, receiver
checks the data and parity for transmission errors.

LCR[2]

Stop bits. The length of stop bit is specified by this bit in conjunction with
the programmed word length (see

Table 16

Logic 0 or cleared = default condition.

1-0

LCR[1-0]

Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see

Table 17

Logic 0 or cleared = default condition.

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7.6 Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 18:

Modem Control Register bits description

Bit

Symbol

Description

MCR[7]

Reserved; set to `0'.

MCR[6]

IR enable.

Logic 0 = Enable the standard modem receive and transmit
input/output interface (normal default condition).

Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs.
While in this mode, the TX/RX output/inputs are routed to the
infrared encoder/decoder. The data input and output levels will
conform to the IrDA infrared interface requirement. As such, while
in this mode, the infrared TX output will be a logic 0 during idle data
conditions.

MCR[5]

Reserved; set to `0'.

Use EFR[6,7] to enable Auto RTS, CTS flow control.

MCR[4]

Loop-back. Enable the local loop-back mode (diagnostics). In this
mode the transmitter output (TX) and the receiver input (RX), CTS,
DSR, DCD, and RI are disconnected from the SC16C550 I/O pins.
Internally the modem data and control pins are connected into a
loop-back data configuration (see

Figure 10

). In this mode, the

receiver and transmitter interrupts remain fully operational. The
Modem Control Interrupts are also operational, but the interrupts'
sources are switched to the lower four bits of the Modem Control.
Interrupts continue to be controlled by the IER register.

Logic 0 = Disable loop-back mode (normal default condition).

Logic 1 = Enable local loop-back mode (diagnostics).

MCR[3]

OUT2, INTx enable. Used to control the modem DCD signal in the
loop-back mode.

Logic 0 = Forces INT output to the 3-State mode. In the loop-back
mode, sets OUT2 (DCD) internally to a logic 1.

Logic 1 = Forces the INT output to the active mode. In the
loop-back mode, sets OUT2 (DCD) internally to a logic 0.

MCR[2]

OUT1. This bit is used in the Loop-back mode only. In the loop-back
mode, this bit is used to write the state of the modem RI interface
signal via OUT1.

MCR[1]

RTS

Logic 0 = Force RTS output to a logic 1 (normal default condition).

Logic 1 = Force RTS output to a logic 0.

MCR[0]

DTR

Logic 0 = Force DTR output to a logic 1 (normal default condition).

Logic 1 = Force DTR output to a logic 0.

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7.7 Line Status Register (LSR)

This register provides the status of data transfers between the SC16C550 and
the CPU.

Table 19:

Line Status Register bits description

Bit

Symbol

Description

LSR[7]

FIFO data error.

Logic 0 = No error (normal default condition).

Logic 1 = At least one parity error, framing error or break indication is in
the current FIFO data. This bit is cleared when LSR register is read.

LSR[6]

THR and TSR empty. This bit is the Transmit Empty indicator. This bit is
set to a logic 1 whenever the transmit holding register and the transmit
shift register are both empty. It is reset to logic 0 whenever either the THR
or TSR contains a data character. In the FIFO mode, this bit is set to `1'
whenever the transmit FIFO and transmit shift register are both empty.

LSR[5]

THR empty. This bit is the Transmit Holding Register Empty indicator.
This bit indicates that the UART is ready to accept a new character for
transmission. In addition, this bit causes the UART to issue an interrupt to
CPU when the THR interrupt enable is set. The THR bit is set to a logic 1
when a character is transferred from the transmit holding register into the
transmitter shift register. The bit is reset to a logic 0 concurrently with the
loading of the transmitter holding register by the CPU. In the FIFO mode,
this bit is set when the transmit FIFO is empty; it is cleared when at least
1 byte is written to the transmit FIFO.

LSR[4]

Break interrupt.

Logic 0 = No break condition (normal default condition).

Logic 1 = The receiver received a break signal (RX was a logic 0 for
one character frame time). In the FIFO mode, only one break character
is loaded into the FIFO.

LSR[3]

Framing error.

Logic 0 = No framing error (normal default condition).

Logic 1 = Framing error. The receive character did not have a valid stop
bit(s). In the FIFO mode, this error is associated with the character at
the top of the FIFO.

LSR[2]

Parity error.

Logic 0 = No parity error (normal default condition).

Logic 1 = Parity error. The receive character does not have correct
parity information and is suspect. In the FIFO mode, this error is
associated with the character at the top of the FIFO.

LSR[1]

Overrun error.

Logic 0 = No overrun error (normal default condition).

Logic 1 = Overrun error. A data overrun error occurred in the receive
shift register. This happens when additional data arrives while the FIFO
is full. In this case, the previous data in the shift register is overwritten.
Note that under this condition, the data byte in the receive shift register
is not transferred into the FIFO, therefore the data in the FIFO is not
corrupted by the error.

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7.8 Modem Status Register (MSR)

This register provides the current state of the control interface signals from the
modem, or other peripheral device to which the SC16C550 is connected. Four bits of
this register are used to indicate the changed information. These bits are set to a
logic 1 whenever a control input from the modem changes state. These bits are set to
a logic 0 whenever the CPU reads this register.

LSR[0]

Receive data ready.

Logic 0 = No data in receive holding register or FIFO (normal default
condition).

Logic 1 = Data has been received and is saved in the receive holding
register or FIFO.

Table 19:

Line Status Register bits description

...continued

Bit

Symbol

Description

Table 20:

Modem Status Register bits description

Bit

Symbol

Description

MSR[7]

Data Carrier Detect. DCD (Active-HIGH, logical 1). Normally this bit is
the complement of the DCD input. In the loop-back mode this bit is
equivalent to the OUT2 bit in the MCR register.

MSR[6]

Ring Indicator. RI (Active-HIGH, logical 1). Normally this bit is the
complement of the RI input. In the loop-back mode this bit is equivalent
to the OUT1 bit in the MCR register.

MSR[5]

Data Set Ready. DSR (Active-HIGH, logical 1). Normally this bit is the
complement of the DSR input. In loop-back mode this bit is equivalent to
the DTR bit in the MCR register.

MSR[4]

Clear To Send. CTS. CTS functions as hardware flow control signal
input if it is enabled via EFR[7]. The transmit holding register flow control
is enabled/disabled by MSR[4]. Flow control (when enabled) allows
starting and stopping the transmissions based on the external modem
CTS signal. A logic 1 at the CTS pin will stop SC16C550 transmissions
as soon as current character has finished transmission. Normally
MSR[4] is the complement of the CTS input. However, in the loop-back
mode, this bit is equivalent to the RTS bit in the MCR register.

MSR[3]

DCD

[1]

Logic 0 = No DCD change (normal default condition).

Logic 1 = The DCD input to the SC16C550 has changed state since
the last time it was read. A modem Status Interrupt will be generated.

MSR[2]

[1]

Logic 0 = No RI change (normal default condition).

Logic 1 = The RI input to the SC16C550 has changed from a logic 0 to
a logic 1. A modem Status Interrupt will be generated.

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[1]

Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.

7.9 Scratchpad Register (SPR)

The SC16C550 provides a temporary data register to store 8 bits of user information.

7.10 Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register.

Bits 0 through 4 provide single or dual character software flow control selection.
When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double
8-bit words are concatenated into two sequential numbers.

MSR[1]

DSR

[1]

Logic 0 = No DSR change (normal default condition).

Logic 1 = The DSR input to the SC16C550 has changed state since
the last time it was read. A modem Status Interrupt will be generated.

MSR[0]

CTS

[1]

Logic 0 = No CTS change (normal default condition).

Logic 1 = The CTS input to the SC16C550 has changed state since
the last time it was read. A modem Status Interrupt will be generated.

Table 20:

Modem Status Register bits description

...continued

Bit

Symbol

Description

Table 21:

Enhanced Feature Register bits description

Bit

Symbol

Description

EFR[7]

Automatic CTS flow control.

Logic 0 = Automatic CTS flow control is disabled (normal default
condition).

Logic 1 = Enable Automatic CTS flow control. Transmission will stop
when CTS goes to a logical 1. Transmission will resume when the CTS
pin returns to a logical 0.

EFR[6]

Automatic RTS flow control. Automatic RTS may be used for hardware flow
control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will
be generated when the receive FIFO is filled to the programmed trigger
level and RTS will go to a logic 1 at the next trigger level. RTS will return to
a logic 0 when data is unloaded below the next lower trigger level
(programmed trigger level 1). The state of this register bit changes with the
status of the hardware flow control. RTS functions normally when
hardware flow control is disabled.

0 = Automatic RTS flow control is disabled (normal default condition).

1 = Enable Automatic RTS flow control.

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[1]

When using a software flow control the Xon/Xoff characters cannot be used for data transfer.

EFR[5]

Special Character Detect.

Logic 0 = Special character detect disabled (normal default condition).

Logic 1 = Special character detect enabled. The SC16C550 compares
each incoming receive character with Xoff2 data. If a match exists, the
received data will be transferred to FIFO and ISR[4] will be set to
indicate detection of special character. Bit-0 in the X-registers
corresponds with the LSB bit for the receive character. When this feature
is enabled, the normal software flow control must be disabled (EFR[3-0]
must be set to a logic 0).

EFR[4]

Enhanced function control bit. The content of IER[7-4], ISR[5-4], FCR[5-4],
and MCR[7-5] can be modified and latched. After modifying any bits in the
enhanced registers, EFR[4] can be set to a logic 0 to latch the new values.
This feature prevents existing software from altering or overwriting the
SC16C550 enhanced functions.

Logic 0 = Disable (normal default condition).

Logic 1 = Enable.

3-0

EFR[3-0] Cont-3-0 Tx, Rx control. Logic 0 or cleared is the default condition.

Combinations of software flow control can be selected by programming
these bits. See

Table 22

Table 22:

Software flow control functions

[1]

Cont-3

Cont-2

Cont-1

Cont-0

TX, RX software flow controls

No transmit flow control

Transmit Xon1/Xoff1

Transmit Xon2/Xoff2

Transmit Xon1 and Xon2/Xoff1 and Xoff2

No receive flow control

Receiver compares Xon1/Xoff1

Receiver compares Xon2/Xoff2

Transmit Xon1/Xoff1

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

Transmit Xon2/Xoff2

Receiver compares Xon1 and Xon2/Xoff1 and Xoff2

Transmit Xon1 and Xon2/Xoff1 and Xoff2

Receiver compares Xon1 and Xon2/Xoff1 and Xoff2

Table 21:

Enhanced Feature Register bits description

...continued

Bit

Symbol

Description

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7.11 SC16C550 external reset conditions

Limiting values

Table 23:

Reset state for registers

Register

Reset state

IER

IER[7-0] = 0

ISR

ISR[7-1] = 0; ISR[0] = 1

LCR

LCR[7-0] = 0

MCR

MCR[7-0] = 0

LSR

LSR[7] = 0; LSR[6-5] = 1; LSR[4-0] = 0

MSR

MSR[7-4] = input signals; MSR[3-0] = 0

FCR

FCR[7-0] = 0

EFR

EFR[7-0] = 0

Table 24:

Reset state for outputs

Output

Reset state

HIGH

RTS

HIGH

DTR

HIGH

RXRDY

HIGH

TXRDY

LOW

Table 25:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

supply voltage

voltage at any pin

GND

0.3

+ 0.3

amb

operating temperature

+85

stg

storage temperature

+150

tot(pack)

total power dissipation per
package

500

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Static characteristics

[1]

Refer to

Table 2 "Pin description" on page 6

for a listing of pins having internal pull-up resistors.

[2]

Except for x

, V

= 1 V typically.

Table 26:

DC electrical characteristics

amb

C to +85

C; V

= 2.5 V, 3.3 V or 5.0 V

10%, unless otherwise specified.

Symbol

Parameter

Conditions

2.5 V

3.3 V

5.0 V

Unit

Min

Max

Min

Max

Min

Max

IL(CK)

LOW-level clock input voltage

0.3

0.45

0.3

0.6

0.5

0.6

IH(CK)

HIGH-level clock input voltage

1.8

2.4

3.0

LOW-level input voltage

0.3

0.65

0.3

0.8

0.5

0.8

HIGH-level input voltage

1.6

2.0

2.2

LOW-level output voltage on all
outputs

[2]

= 5 mA

(databus)

0.4

= 4 mA

(other outputs)

0.4

= 2 mA

(databus)

0.4

= 1.6 mA

(other outputs)

0.4

HIGH-level output voltage

5 mA

(databus)

2.4

1 mA

(other outputs)

2.0

800

(databus)

1.85

400

(other outputs)

1.85

LIL

LOW-level input leakage current

clock leakage

average power supply current

f = 5 MHz

3.5

4.5

input capacitance

pu(int)

internal pull-up resistance

500

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10. Dynamic characteristics

Table 27:

AC electrical characteristics

amb

C to +85

C; V

= 2.5 V, 3.3 V or 5.0 V

10%, unless otherwise specified.

Symbol

Parameter

Conditions

2.5 V

3.3 V

5.0 V

Unit

Min

Max

Min

Max

Min

Max

, t

clock pulse duration

clock frequency

[1]

MHz

address strobe width

address set-up time

address hold time

chip select set-up time to AS

address hold time

6s'

address set-up time

[2]

chip select hold time

IOR delay from chip select

IOR strobe width

25 pF load

chip select hold time from IOR

7h'

address hold time

[2]

IOR delay from address

read cycle delay

25 pF load

11d

IOR to DDIS delay

25 pF load

100

12d

delay from IOR to data

25 pF load

12h

data disable time

25 pF load

13d

IOW delay from chip select

13w

IOW strobe width

[3]

13h

chip select hold time from IOW

14d

IOW delay from address

15d

write cycle delay

[4]

16s

data set-up time

16h

data hold time

17d

delay from IOW to output

25 pF load

100

18d

delay to set interrupt from Modem
input

25 pF load

100

19d

delay to reset interrupt from IOR

25 pF load

100

20d

delay from stop to set interrupt

clk

21d

delay from IOR to reset interrupt

25 pF load

100

22d

delay from start to set interrupt

100

23d

delay from IOW to transmit start

clk

24d

delay from IOW to reset interrupt

100

25d

delay from stop to set RXRDY

clk

26d

delay from IOR to reset RXRDY

100

27d

delay from IOW to set TXRDY

100

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[1]

Applies to external clock, crystal oscillator max 24 MHz.

[2]

Applicable only when AS is tied LOW.

[3]

= 333 ns (for Baudrate

max

= 1.5 Mbits/s)

= 1

s (for Baudrate

max

= 460.8 kbits/s)

= 4

s (for Baudrate

max

= 115.2 kbits/s)

[4]

When in both DMA mode 0 and FIFO enable mode, the write cycle delay should be larger than one x

clock cycle.

10.1 Timing diagrams

28d

delay from start to reset TXRDY

clk

RESET

Reset pulse width

100

baud rate divisor

1 1

1 R

clk

Table 27:

AC electrical characteristics

...continued

amb

C to +85

C; V

= 2.5 V, 3.3 V or 5.0 V

10%, unless otherwise specified.

Symbol

Parameter

Conditions

2.5 V

3.3 V

5.0 V

Unit

Min

Max

Min

Max

Min

Max

IOWstrobe

max

2 Baudrate

max

(

)

--------------------------------------

Fig 11. General read timing when using AS signal.

DATA

ACTIVE

VALID

ADDRESS

002aaa331

A0A2

CS2

CS1CS0

IOR, IOR

D0D7

DDIS

11d

ACTIVE

12d

12h

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11. Package outline

Fig 25. PLCC44 (SOT187-2).

UNIT

min.

max.

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

4.57
4.19

0.51

3.05

0.53
0.33

0.021
0.013

16.66
16.51

1.27

17.65
17.40

2.16

0.18

0.1

0.18

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

SOT187-2

(1)

16.66
16.51

17.65
17.40

(1)

max.

(1)

max.

2.16

0.81
0.66

1.22
1.07

0.180
0.165

0.02

0.12

0.25

0.01

0.656
0.650

0.05

0.695
0.685

0.085

0.007 0.004

0.007

1.44
1.02

0.057
0.040

0.656
0.650

0.695
0.685

16.00
14.99

0.63
0.59

16.00
14.99

0.63
0.59

0.085

0.032
0.026

0.048
0.042

detail X

(A )

Z D

Z E

pin 1 index

112E10

MS-018

EDR-7319

10 mm

scale

99-12-27
01-11-14

inches

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

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Fig 26. LQFP48 (SOT313-2).

UNIT

max.

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

1.6

0.20
0.05

1.45
1.35

0.25

0.27
0.17

0.18
0.12

7.1
6.9

0.5

9.15
8.85

0.95
0.55

7
0

0.12

0.1

0.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75
0.45

SOT313-2

MS-026

136E05

00-01-19
03-02-25

(1)

7.1
6.9

9.15
8.85

0.95
0.55

Z E

detail X

(A )

2.5

5 mm

scale

pin 1 index

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

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Fig 27. DIP40 (SOT129-1).

UNIT

max.

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT129-1

99-12-27
03-02-13

min.

max.

1.70
1.14

0.53
0.38

0.36
0.23

52.5
51.5

14.1
13.7

3.60
3.05

0.254

2.54

15.24

15.80
15.24

17.42
15.90

2.25

4.7

0.51

0.067
0.045

0.021
0.015

0.014
0.009

2.067
2.028

0.56
0.54

0.14
0.12

0.01

0.1

0.6

0.62
0.60

0.69
0.63

0.089

0.19

0.02

0.16

051G08

MO-015

SC-511-40

(e )

seating plane

pin 1 index

10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

(1)

DIP40: plastic dual in-line package; 40 leads (600 mil)

SOT129-1

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12. Soldering

12.1 Introduction

This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our

Data Handbook IC26; Integrated Circuit

Packages (document order number 9398 652 90011).

There is no soldering method that is ideal for all IC packages. Wave soldering is often
preferred when through-hole and surface mount components are mixed on one
printed-circuit board. Wave soldering can still be used for certain surface mount ICs,
but it is not suitable for fine pitch SMDs. In these situations reflow soldering is
recommended. Driven by legislation and environmental forces the worldwide use of
lead-free solder pastes is increasing.

12.2 Through-hole mount packages

12.2.1

Soldering by dipping or by solder wave

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250

C or

265

C, depending on solder material applied, SnPb or Pb-free respectively.

The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the
plastic body must not exceed the specified maximum storage temperature (T

stg(max)

If the printed-circuit board has been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within the permissible limit.

12.2.2

Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron
bit is less than 300

C it may remain in contact for up to 10 seconds. If the bit

temperature is between 300 and 400

C, contact may be up to 5 seconds.

12.3 Surface mount packages

12.3.1

Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215 to 270

C depending on solder

paste material. The top-surface temperature of the packages should preferably be
kept:

below 220

C (SnPb process) or below 245

C (Pb-free process)

for all the BGA and SSOP-T packages

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for packages with a thickness

2.5 mm

for packages with a thickness < 2.5 mm and a volume

350 mm

so called

thick/large packages.

below 235

C (SnPb process) or below 260

C (Pb-free process) for packages with

a thickness < 2.5 mm and a volume < 350 mm

so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all
times.

12.3.2

Wave soldering

Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically
developed.

If wave soldering is used the following conditions must be observed for optimal
results:

Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

For packages with leads on four sides, the footprint must be placed at a 45

angle

to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250

C or

265

C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal of corrosive residues in
most applications.

12.3.3

Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300

When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320

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12.4 Package related soldering information

[1]

For more detailed information on the BGA packages refer to the

(LF)BGA Application Note

(AN01026); order a copy from your Philips Semiconductors sales office.

[2]

All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the

Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods.

[3]

For SDIP packages, the longitudinal axis must be parallel to the transport direction of the
printed-circuit board.

[4]

These transparent plastic packages are extremely sensitive to reflow soldering conditions and must
on no account be processed through more than one soldering cycle or subjected to infrared reflow
soldering with peak temperature exceeding 217

C measured in the atmosphere of the reflow

oven. The package body peak temperature must be kept as low as possible.

[5]

These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with
the heatsink on the top side, the solder might be deposited on the heatsink surface.

[6]

If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[7]

Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[8]

Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

Table 28:

Suitability of IC packages for wave, reflow and dipping soldering methods

Mounting

Package

[1]

Soldering method

Wave

Reflow

[2]

Dipping

Through-hole
mount

DBS, DIP, HDIP, SDIP, SIL suitable

[3]

suitable

Surface mount

BGA, LBGA, LFBGA,
SQFP, SSOP-T

[4]

TFBGA, VFBGA

not suitable

suitable

DHVQFN, HBCC, HBGA,
HLQFP, HSQFP, HSOP,
HTQFP, HTSSOP,
HVQFN, HVSON, SMS

not suitable

[5]

suitable

PLCC

[6]

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

[6][7]

suitable

SSOP, TSSOP, VSO,
VSSOP

not recommended

[8]

suitable

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Contact information

For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

14. Data sheet status

[1]

Please consult the most recently issued data sheet before initiating or completing a design.

[2]

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

15. Definitions

Short-form specification -- The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.

Application information -- Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.

16. Disclaimers

Life support -- These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status `Production'),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.

Level

Data sheet status

[1]

Product status

[2][3]

Definition

Objective data

Development

This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Qualification

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.

The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.

Date of release: 19 June 2003

Document order number: 9397 750 11619

Contents

Philips Semiconductors

SC16C550

UART with 16-byte FIFO and IrDA encoder/decoder

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pinning information . . . . . . . . . . . . . . . . . . . . . . 4

5.1

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

Functional description . . . . . . . . . . . . . . . . . . . 9

6.1

Internal registers . . . . . . . . . . . . . . . . . . . . . . . 10

6.2

FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 10

6.3

Autoflow control (see

Figure 5

) . . . . . . . . . . . . 11

6.3.1

Auto-RTS (see

Figure 5

). . . . . . . . . . . . . . . . . 11

6.3.2

Auto-CTS (see

Figure 5

). . . . . . . . . . . . . . . . . 12

6.3.3

Enabling autoflow control and auto-CTS . . . . 12

6.3.4

Auto-CTS and auto-RTS functional timing . . . 12

6.4

Software flow control . . . . . . . . . . . . . . . . . . . 13

6.5

Special feature software flow control . . . . . . . 14

6.6

Hardware/software and time-out interrupts. . . 14

6.7

Programmable baud rate generator . . . . . . . . 15

6.8

DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 16

6.9

Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.10

Loop-back mode . . . . . . . . . . . . . . . . . . . . . . . 17

Register descriptions . . . . . . . . . . . . . . . . . . . 19

7.1

Transmit (THR) and Receive (RHR)
Holding Registers . . . . . . . . . . . . . . . . . . . . . 20

7.2

Interrupt Enable Register (IER) . . . . . . . . . . . 20

7.2.1

IER versus Receive FIFO interrupt
mode operation . . . . . . . . . . . . . . . . . . . . . . . 21

7.2.2

IER versus Receive/Transmit FIFO polled
mode operation . . . . . . . . . . . . . . . . . . . . . . . 21

7.3

FIFO Control Register (FCR) . . . . . . . . . . . . . 22

7.3.1

DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.3.2

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.4

Interrupt Status Register (ISR) . . . . . . . . . . . . 24

7.5

Line Control Register (LCR) . . . . . . . . . . . . . . 25

7.6

Modem Control Register (MCR) . . . . . . . . . . . 27

7.7

Line Status Register (LSR) . . . . . . . . . . . . . . . 28

7.8

Modem Status Register (MSR). . . . . . . . . . . . 29

7.9

Scratchpad Register (SPR) . . . . . . . . . . . . . . 30

7.10

Enhanced Feature Register (EFR) . . . . . . . . . 30

7.11

SC16C550 external reset conditions . . . . . . . 32

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 32

Static characteristics . . . . . . . . . . . . . . . . . . . 33

Dynamic characteristics . . . . . . . . . . . . . . . . . 34

10.1

Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 35

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 44

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

12.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 47

12.2

Through-hole mount packages . . . . . . . . . . . 47

12.2.1

Soldering by dipping or by solder wave . . . . . 47

12.2.2

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 47

12.3

Surface mount packages . . . . . . . . . . . . . . . . 47

12.3.1

Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 47

12.3.2

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 48

12.3.3

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 48

12.4

Package related soldering information . . . . . . 49

Revision history . . . . . . . . . . . . . . . . . . . . . . . 50

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 51

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SC16C550IN40

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SC16C550IN40