SC16C652
Dual UART with 32 bytes of transmit and receive FIFOs
Rev. 04 -- 20 June 2003
Product data
1.
Description
The SC16C652 is a 2 channel Universal Asynchronous Receiver and Transmitter
(UART) used for serial data communications. Its principal function is to convert
parallel data into serial data and vice versa. The UART can handle serial data rates
up to 5 Mbits/s. The SC16C652 is pin compatible with the SC16C2550. It will
power-up to be functionally equivalent to the 16C2450. The SC16C652 provides
enhanced UART functions with 32-byte FIFOs, modem control interface, DMA mode
data transfer. The DMA mode data transfer is controlled by the FIFO trigger levels
and the TXRDY and RXRDY signals. On-board status registers provide the user with
error indications and operational status. System interrupts and modem control
features may be tailored by software to meet specific user requirements. An internal
loop-back capability allows on-board diagnostics. Independent programmable baud
rate generators are provided to select transmit and receive baud rates.
The SC16C652 operates at 5 V, 3.3 V and 2.5 V and the Industrial temperature
range, and is available in a plastic LQFP48 package.
2.
Features
s
2 channel UART
s
5 V, 3.3 V and 2.5 V operation
s
Industrial temperature range
s
Pin and functionally compatible to 16C2450 and software compatible with
SC16C650
s
Up to 5 Mbits/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V
s
32-byte transmit FIFO to reduce the bandwidth requirement of the external CPU
s
32-byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU
s
Independent transmit and receive UART control
s
Four selectable Receive and Transmit FIFO interrupt trigger levels
s
Automatic software/hardware flow control
s
Programmable Xon/Xoff characters
s
Software selectable Baud Rate Generator
s
Sleep mode
s
Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun
Break)
s
Transmit, Receive, Line Status, and Data Set interrupts independently controlled
Philips Semiconductors
SC16C652
Dual UART with 32 bytes of transmit and receive FIFOs
Product data
Rev. 04 -- 20 June 2003
2 of 41
9397 750 11634
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
s
Fully programmable character formatting:
x
5-, 6-, 7-, or 8-bit characters
x
Even-, Odd-, or No-Parity formats
x
1-, 1
1
/
2
-, or 2-stop bit
x
Baud generation (DC to 5 Mbit/s)
s
False start-bit detection
s
Complete status reporting capabilities
s
3-State output TTL drive capabilities for bi-directional data bus and control bus
s
Line Break generation and detection
s
Internal diagnostic capabilities:
x
Loop-back controls for communications link fault isolation
s
Prioritized interrupt system controls
s
Modem control functions (CTS, RTS, DSR, DTR, RI, CD).
3.
Ordering information
Table 1:
Ordering information
Type number
Package
Name
Description
Version
SC16C652IB48
LQFP48
plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
SOT313-2
Philips Semiconductors
SC16C652
Dual UART with 32 bytes of transmit and receive FIFOs
Product data
Rev. 04 -- 20 June 2003
3 of 41
9397 750 11634
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
4.
Block diagram
Fig 1.
SC16C652 block diagram.
TRANSMIT
FIFO
REGISTER
TXA, TXB
RECEIVE
SHIFT
REGISTER
RECEIVE
FIFO
REGISTER
RXA, RXB
INTERCONNECT B
US LINES
AND
CONTR
OL SIGNALS
SC16C652
TRANSMIT
SHIFT
REGISTER
MODEM
CONTROL
LOGIC
DTRA, DTRB
RTSA, RTSB
OP2A, OP2B
CLOCK AND
BAUD RATE
GENERATOR
CTSA, CTSB
RIA, RIB
CDA, CDB
DSRA, DSRB
XTAL2
XTAL1
DATA BUS
AND
CONTROL LOGIC
D0D7
IOR
IOW
RESET
A0A2
CSA
CSB
REGISTER
SELECT
LOGIC
INTA, INTB
TXRDYA, TXRDYB
RXRDYA, RXRDYB
INTERRUPT
CONTROL
LOGIC
002aaa348
Philips Semiconductors
SC16C652
Dual UART with 32 bytes of transmit and receive FIFOs
Product data
Rev. 04 -- 20 June 2003
4 of 41
9397 750 11634
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
5.
Pinning information
5.1 Pinning
5.2 Pin description
Fig 2.
LQFP48 pin configuration.
SC16C652IB48
002aaa349
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
D4
D3
D2
D1
D0
TXRDYA
V
CC
RIA
CDA
DSRA
CTSA
N.C.
XTAL1
XTAL2
IOW
CDB
GND
RXRDYB
IOR
DSRB
RIB
RTSB
CTSB
N.C.
D5
D6
D7
RXB
RXA
TXRDYB
TXA
TXB
OP2B
CSA
CSB
N.C.
RESET
DTRB
DTRA
RTSA
OP2A
RXRDYA
INTA
INTB
A0
A1
A2
N.C.
Table 2:
Pin description
Symbol
Pin
Type
Description
LQFP48
A0
28
I
Address 0 select bit. Internal register address selection.
A1
27
I
Address 1 select bit. Internal register address selection.
A2
26
I
Address 2 select bit. Internal register address selection.
CSA, CSB
10, 11
I
Chip Select A, B (Active-LOW). This function is associated with individual channels, A
through B. These pins enable data transfers between the user CPU and the SC16C652
for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing
a logic 0 on the respective CSA, CSB pin.
D0-D7
44-48, 1-3 I/O
Data bus (bi-directional). These pins are the 8-bit, 3-State data bus for transferring
information to or from the controlling CPU. D0 is the least significant bit and the first data
bit in a transmit or receive serial data stream.
GND
17
I
Signal and power ground.
Philips Semiconductors
SC16C652
Dual UART with 32 bytes of transmit and receive FIFOs
Product data
Rev. 04 -- 20 June 2003
5 of 41
9397 750 11634
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
INTA, INTB
30, 29
O
Interrupt A, B (3-State). This function is associated with individual channel interrupts,
INTA, INTB. INTA, INTB are enabled when MCR bit 3 is set to a logic 1, interrupts are
enabled in the interrupt enable register (IER), and is active when an interrupt condition
exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit
buffer empty, or when a modem status flag is detected.
IOR
19
I
Read strobe (Active-LOW strobe). A logic 0 transition on this pin will load the contents
of an internal register defined by address bits A0-A2 onto the SC16C652 data bus
(D0-D7) for access by external CPU.
IOW
15
I
Write strobe (Active-LOW strobe). A logic 0 transition on this pin will transfer the
contents of the data bus (D0-D7) from the external CPU to an internal register that is
defined by address bits A0-A2.
OP2A,
OP2B
32, 9
O
Output 2 (user-defined). This function is associated with individual channels, A through
B. The state at these pin(s) are defined by the user and through MCR register bit 3. INTA,
INTB are set to the active mode and OP2 to logic 0 when MCR[3] is set to a logic 1. INTA,
INTB are set to the 3-State mode and OP2 to a logic 1 when MCR[3] is set to a logic 0.
See bit 3, Modem Control Register (MCR[3]). Since these bits control both the INTA,
INTB operation and OP2 outputs, only one function should be used at one time, INT or
OP2.
RESET
36
I
Reset (Active-HIGH). A logic 1 on this pin will reset the internal registers and all the
outputs. The UART transmitter output and the receiver input will be disabled during reset
time. (See
Section 7.11 "SC16C652 external reset condition"
for initialization details.)
RXRDYA,
RXRDYB
31, 18
O
Receive Ready A, B (Active-LOW). This function provides the RX FIFO/RHR status for
individual receive channels (A-B). RXRDYn is primarily intended for monitoring DMA
mode 1 transfers for the receive data FIFOs. A logic 0 indicates there is a receive data to
read/upload, i.e., receive ready status with one or more RX characters available in the
FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the programmed
trigger level has not been reached. This signal can also be used for single mode transfers
(DMA mode 0).
TXRDYA,
TXRDYB
43, 6
O
Transmit Ready A, B (Active-LOW). These outputs provide the TX FIFO/THR status for
individual transmit channels (A-B). TXRDYn is primarily intended for monitoring DMA
mode 1 transfers for the transmit data FIFOs. An individual channel's TXRDYA, TXRDYB
buffer ready status is indicated by logic 0, i.e., at lease one location is empty and
available in the FIFO or THR. This pin goes to a logic 1 (DMA mode 1) when there are no
more empty locations in the FIFO or THR. This signal can also be used for single mode
transfers (DMA mode 0).
V
CC
42
I
Power supply input.
XTAL1
13
I
Crystal or external clock input. Functions as a crystal input or as an external clock
input. A crystal can be connected between this pin and XTAL2 to form an internal
oscillator circuit. This configuration requires an external 1 M
resistor between the
XTAL1 and XTAL2 pins. Alternatively, an external clock can be connected to this pin to
provide custom data rates. (See
Section 6.8 "Programmable baud rate generator"
.)
See
Figure 3
.
XTAL2
14
O
Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal oscillator
output or buffered clock output. Should be left open if an external clock is connected to
XTAL1. For extended frequency operation, this pin should be tied to V
CC
via a 2 k
resistor.
CDA, CDB
40, 16
I
Carrier Detect (Active-LOW). These inputs are associated with individual UART
channels A through B. A logic 0 on this pin indicates that a carrier has been detected by
the modem for that channel.
Table 2:
Pin description
...continued
Symbol
Pin
Type
Description
LQFP48
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