General description

The SC16C754B is a quad Universal Asynchronous Receiver/Transmitter (UART) with
64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s
(3.3 V and 5 V). The SC16C754B offers enhanced features. It has a transmission control
register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during
hardware and software flow control. With the FIFO RDY register, the software gets the
status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide
the user with error indications, operational status, and modem interface control. System
interrupts may be tailored to meet user requirements. An internal loop-back capability
allows on-board diagnostics.

The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and
receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or
8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed
to interrupt at different trigger levels. The UART generates its own desired baud rate
based upon a programmable divisor and its input clock. It can transmit even, odd, or no
parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors,
FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART
also contains a software interface for modem control operations, and has software flow
control and hardware flow control capabilities.

The SC16C754B is available in plastic LQFP64, LQFP80 and PLCC68 packages.

Features

4 channel UART

5 V, 3.3 V and 2.5 V operation

Pin compatible with SC16C654IA68, TL16C754, and SC16C554IA68 with additional
enhancements, and software compatible with TL16C754

Up to 5 Mbit/s data rate (at 3.3 V and 5 V; at 2.5 V maximum data rate is 3 Mbit/s)

5 V tolerant inputs

64-byte transmit FIFO

64-byte receive FIFO with error flags

Industrial temperature range (

C to +85

Programmable and selectable transmit and receive FIFO trigger levels for DMA and
interrupt generation

Software (Xon/Xoff)/hardware (RTS/CTS) flow control

Programmable Xon/Xoff characters

Programmable auto-RTS and auto-CTS

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte
FIFOs

Rev. 02 -- 13 June 2005

Product data sheet

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

2 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Optional data flow resume by Xon any character

DMA signalling capability for both received and transmitted data

Supports 5 V, 3.3 V and 2.5 V operation

Software selectable baud rate generator

Prescaler provides additional divide-by-4 function

Fast data bus access time

Programmable Sleep mode

Programmable serial interface characteristics

5, 6, 7, or 8-bit characters

Even, odd, or no-parity bit generation and detection

1, 1.5, or 2 stop bit generation

False start bit detection

Complete status reporting capabilities in both normal and Sleep mode

Line break generation and detection

Internal test and loop-back capabilities

Fully prioritized interrupt system controls

Modem control functions (CTS, RTS, DSR, DTR, RI, and CD)

Sleep mode

Ordering information

Table 1:

Ordering information

Type number

Package

Name

Description

Version

SC16C754BIBM

LQFP64

plastic low profile quad flat package; 64 leads; body 7

1.4 mm

SOT414-1

SC16C754BIB80

LQFP80

plastic low profile quad flat package; 80 leads; body 12

1.4 mm

SOT315-1

SC16C754BIA68

PLCC68

plastic leaded chip carrier; 68 leads

SOT188-2

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

5 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Fig 3.

Pin configuration for LQFP80

SC16C754BIB80

n.c.

DSRD

DSRA

CTSD

CTSA

DTRD

DTRA

GND

RTSD

RTSA

INTD

INTA

CSD

CSA

TXD

TXA

IOR

IOW

TXC

TXB

CSC

CSB

INTC

INTB

RTSC

RTSB

GND

DTSC

DTRB

CTSC

CTSB

DSRC

DSRB

n.c.

CDA

CDB

RIA

RIB

RXA

RXB

GND

CLKSEL

n.c.

XTAL1

XTAL2

RESET

RXRDY

INTSEL

TXRDY

GND

RXD

RXC

RID

RIC

CDD

CDC

n.c.

002aaa867

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

6 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

5.2 Pin description

Fig 4.

Pin configuration for PLCC68

SC16C754BIA68

DSRA

DSRD

CTSA

CTSD

DTRA

DTRD

GND

RTSA

RTSD

INTA

INTD

CSA

CSD

TXA

TXD

IOW

IOR

TXB

TXC

CSB

INTB

RTSB

GND

DTRB

CTSB

DSRB

CSC

INTC

RTSC

DTRC

CTSC

DSRC

CDB

GND

RIB

RXB

CLKSEL

CDA

RIA

RXA

n.c.

XTAL1

XTAL2

INTSEL

RESET

RXRDY

TXRDY

GND

RXC

RIC

CDC

RXD

RID

CDD

002aaa868

Table 2:

Pin description

Symbol

Pin

Type

Description

LQFP64 LQFP80 PLCC68

Address 0 select bit. Internal registers address selection.

Address 1 select bit. Internal registers address selection.

Address 2 select bit. Internal registers address selection.

CDA

Carrier Detect (active LOW). These inputs are associated with
individual UART channels A through D. A logic LOW on these pins
indicates that a carrier has been detected by the modem for that
channel. The state of these inputs is reflected in the modem status
register (MSR).

CDB

CDC

CDD

CLKSEL

Clock Select. CLKSEL selects the divide-by-1 or divide-by-4
prescalable clock. During the reset, a logic 1 (V

) on CLKSEL

selects the divide-by-1 prescaler. A logic 0 (GND) on CLKSEL selects
the divide-by-4 prescaler. The value of CLKSEL is latched into
MCR[7] at the trailing edge of RESET. A logic 1 (V

) on CLKSEL will

latch a 0 into MCR[7]. A logic 0 (GND) on CLKSEL will latch a 1 into
MCR[7]. MCR[7] can be changed after RESET to alter the prescaler
value. This pin is associated with LQFP80 and PLCC68 packages
only. This pin is connected to V

internally on LQFP64 package.

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

7 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

CSA

Chip Select (active LOW). These pins enable data transfers
between the user CPU and the SC16C754B for the channel(s)
addressed. Individual UART sections (A, B, C, D) are addressed by
providing a logic LOW on the respective CSA through CSD pins.

CSB

CSC

CSD

CTSA

Clear to Send (active LOW). These inputs are associated with
individual UART channels A through D. A logic 0 (LOW) on the CTS
pins indicates the modem or data set is ready to accept transmit data
from the SC16C754B. Status can be tested by reading MSR[4].
These pins only affect the transmit and receive operations when
Auto-CTS function is enabled via the Enhanced Feature Register
EFR[7] for hardware flow control operation.

CTSB

CTSC

CTSD

D0 to D7

53, 54,
55, 56,
57, 58,
59, 60

68, 69,
70, 71,
72, 73,
74, 75

66, 67,
68, 1, 2,
3, 4, 5

I/O

Data bus (bi-directional). These pins are the 8-bit, 3-state data bus
for transferring information to or from the controlling CPU. D0 is the
least significant bit and the first data bit in a transmit or receive serial
data stream.

DSRA

Data Set Ready (active LOW). These inputs are associated with
individual UART channels A through D. A logic 0 (LOW) on these pins
indicates the modem or data set is powered-on and is ready for data
exchange with the UART. The state of these inputs is reflected in the
modem status register (MSR).

DSRB

DSRC

DSRD

DTRA

Data Terminal Ready (active LOW). These outputs are associated
with individual UART channels A through D. A logic 0 (LOW) on these
pins indicates that the SC16C754B is powered-on and ready. These
pins can be controlled via the modem control register. Writing a
logic 1 to MCR[0] will set the DTR output to logic 0 (LOW), enabling
the modem. The output of these pins will be a logic 1 after writing a
logic 0 to MCR[0], or after a reset.

DTRB

DTRC

DTRD

GND

14, 28,
45, 61

16, 36,
56, 76

6, 23,
40, 57

Signal and power ground.

INTA

Interrupt A, B, C, and D (active HIGH). These pins provide
individual channel interrupts INTA through INTD. INTA through INTD
are enabled when MCR[3] is set to a logic 1, interrupt sources are
enabled in the interrupt enable register (IER). Interrupt conditions
include: receiver errors, available receiver buffer data, available
transmit buffer space, or when a modem status flag is detected.
INTA to INTD are in the high-impedance state after reset.

INTB

INTC

INTD

INTSEL

Interrupt select (active HIGH with internal pull-down). INTSEL
can be used in conjunction with MCR[3] to enable or disable the
3-state interrupts INTA to INTD or override MCR[3] and force
continuous interrupts. Interrupt outputs are enabled continuously by
making this pin a logic 1. Driving this pin LOW allows MCR[3] to
control the 3-state interrupt output. In this mode, MCR[3] is set to a
logic 1 to enable the 3-state outputs. This pin is associated with
LQFP80 and PLCC68 packages only. This pin is connected to GND
internally on the LQFP64 package.

IOR

Input/Output Read strobe (active LOW). A HIGH-to-LOW transition
on IOR will load the contents of an internal register defined by
address bits A[2:0] onto the SC16C754B data bus (D[7:0]) for access
by external CPU.

Table 2:

Pin description

...continued

Symbol

Pin

Type

Description

LQFP64 LQFP80 PLCC68

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

8 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

IOW

Input/Output Write strobe (active LOW). A LOW-to-HIGH transition
on IOW will transfer the contents of the data bus (D[7:0]) from the
external CPU to an internal register that is defined by address bits
A[2:0] and CSA and CSD.

n.c.

1, 2, 20,
21, 22,
27, 40,
41, 42,
60, 61,
62, 80

not connected

RESET

Reset. This pin will reset the internal registers and all the outputs.
The UART transmitter output and the receiver input will be disabled
during reset time. RESET is an active HIGH input.

RIA

Ring Indicator (active LOW). These inputs are associated with
individual UART channels, A through D. A logic 0 on these pins
indicates the modem has received a ringing signal from the telephone
line. A LOW-to-HIGH transition on these input pins generates a
modem status interrupt, if enabled. The state of these inputs is
reflected in the modem status register (MSR).

RIB

RIC

RID

RTSA

Request to Send (active LOW). These outputs are associated with
individual UART channels, A through D. A logic 0 on the RTS pin
indicates the transmitter has data ready and waiting to send. Writing
a logic 1 in the modem control register MCR[1] will set this pin to a
logic 0, indicating data is available. After a reset these pins are set to
a logic 1. These pins only affect the transmit and receive operations
when Auto-RTS function is enabled via the Enhanced Feature
Register (EFR[6]) for hardware flow control operation.

RTSB

RTSC

RTSD

RXA

Receive data input. These inputs are associated with individual
serial channel data to the SC16C754B. During the local loop-back
mode, these RX input pins are disabled and TX data is connected to
the UART RX input internally.

RXB

RXC

RXD

RXRDY

Receive Ready (active LOW). RXRDY contains the wire-ORed
status of all four receive channel FIFOs, RXRDY A to RXRDY D. It
goes LOW when the trigger level has been reached or a time-out
interrupt occurs. It goes HIGH when all RX FIFOs are empty and
there is an error in RX FIFO. This pin is associated with LQFP80 and
PLCC68 packages only.

TXA

Transmit data. These outputs are associated with individual serial
transmit channel data from the SC16C754B. During the local
loop-back mode, the TX output pin is disabled and TX data is
internally connected to the UART RX input.

TXB

TXC

TXD

TXRDY

Transmit Ready (active LOW). TXRDY contains the wire-ORed
status of all four transmit channel FIFOs, TXRDY A to TXRDY D. It
goes LOW when there are a trigger level number of spaces available.
It goes HIGH when all four TX buffers are full. This pin is associated
with LQFP80 and PLCC68 packages only.

Table 2:

Pin description

...continued

Symbol

Pin

Type

Description

LQFP64 LQFP80 PLCC68

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

9 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Functional description

The SC16C754B UART is pin-compatible with the SC16C554 and SC16C654 UARTs. It
provides more enhanced features. All additional features are provided through a special
enhanced feature register.

The UART will perform serial-to-parallel conversion on data characters received from
peripheral devices or modems, and parallel-to-parallel conversion on data characters
transmitted by the processor. The complete status of each channel of the SC16C754B
UART can be read at any time during functional operation by the processor.

The SC16C754B can be placed in an alternate mode (FIFO mode) relieving the processor
of excessive software overhead by buffering received/transmitted characters. Both the
receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of
error status per byte for the receiver FIFO) and have selectable or programmable trigger
levels. Primary outputs RXRDY and TXRDY allow signalling of DMA transfers.

The SC16C754B has selectable hardware flow control and software flow control.
Hardware flow control significantly reduces software overhead and increases system
efficiency by automatically controlling serial data flow using the RTS output and CTS input
signals. Software flow control automatically controls data flow by using programmable
Xon/Xoff characters.

The UART includes a programmable baud rate generator that can divide the timing
reference clock input by a divisor between 1 and (2

1).

6.1 Trigger levels

The SC16C754B provides independent selectable and programmable trigger levels for
both receiver and transmitter DMA and interrupt generation. After reset, both transmitter
and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of
one byte. The selectable trigger levels are available via the FCR. The programmable
trigger levels are available via the TLR.

4, 21,
35, 52

6, 46, 66 13, 47,

Power supply input.

XTAL1

Crystal or external clock input. Functions as a crystal input or as an
external clock input. A crystal can be connected between XTAL1 and
XTAL2 to form an internal oscillator circuit (see

Figure 14

Alternatively, an external clock can be connected to this pin to provide
custom data rates.

XTAL2

Output of the crystal oscillator or buffered clock. (See also
XTAL1.) XTAL2 is used as a crystal oscillator output or a buffered
clock output.

Table 2:

Pin description

...continued

Symbol

Pin

Type

Description

LQFP64 LQFP80 PLCC68

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

10 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

6.2 Hardware flow control

Hardware flow control is comprised of Auto-CTS and Auto-RTS. Auto-CTS and Auto-RTS
can be enabled/disabled independently by programming EFR[7:6].

With Auto-CTS, CTS must be active before the UART can transmit data.

Auto-RTS only activates the RTS output when there is enough room in the FIFO to receive
data and de-activates the RTS output when the RX FIFO is sufficiently full. The halt and
resume trigger levels in the TCR determine the levels at which RTS is
activated/deactivated.

If both Auto-CTS and Auto-RTS are enabled, when RTS is connected to CTS, data
transmission does not occur unless the receiver FIFO has empty space. Thus, overrun
errors are eliminated during hardware flow control. If not enabled, overrun errors occur if
the transmit data rate exceeds the receive FIFO servicing latency.

Fig 5.

Autoflow control (Auto-RTS and Auto-CTS) example

FIFO

FLOW

CONTROL

FIFO

PARALLEL

TO SERIAL

FIFO

UART 1

UART 2

D7 to D0

RTS

CTS

RTS

D7 to D0

002aaa228

SERIAL TO

PARALLEL

SERIAL TO

PARALLEL

FLOW

CONTROL

FLOW

CONTROL

FLOW

CONTROL

PARALLEL

TO SERIAL

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

11 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

6.2.1 Auto-RTS

Auto-RTS data flow control originates in the receiver block (see

Figure 1 "Block diagram of

SC16C754B" on page 3

Figure 6

shows RTS functional timing. The receiver FIFO trigger

levels used in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO level is below
the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached,
RTS is deasserted. The sending device (for example, another UART) may send an
additional byte after the trigger level is reached (assuming the sending UART has another
byte to send) because it may not recognize the deassertion of RTS until it has begun
sending the additional byte. RTS is automatically reasserted once the receiver FIFO
reaches the resume trigger level programmed via TCR[7:4]. This reassertion allows the
sending device to resume transmission.

6.2.2 Auto-CTS

The transmitter circuitry checks CTS before sending the next data byte. When CTS is
active, the transmitter sends the next byte. To stop the transmitter from sending the
following byte, CTS must be deasserted before the middle of the last stop bit that is
currently being sent. The auto-CTS function reduces interrupts to the host system. When
flow control is enabled, CTS level changes do not trigger host interrupts because the
device automatically controls its own transmitter. Without auto-CTS, the transmitter sends
any data present in the transmit FIFO and a receiver overrun error may result.

(1) N = receiver FIFO trigger level.

(2) The two blocks in dashed lines cover the case where an additional byte is sent, as described in

Section 6.2.1

Fig 6.

RTS functional timing

Start

byte N

Start

byte N

Start

Stop

RTS

IOR

N+1

002aaa226

(1) When CTS is LOW, the transmitter keeps sending serial data out.

(2) When CTS goes HIGH before the middle of the last stop bit of the current byte, the transmitter finishes sending the current

byte, but it does not send the next byte.

(3) When CTS goes from HIGH to LOW, the transmitter begins sending data again.

Fig 7.

CTS functional timing

Start

byte 0 to 7

Stop

CTS

002aaa227

Start

byte 0 to 7

Stop

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

12 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

6.3 Software flow control

Software flow control is enabled through the enhanced feature register and the modem
control register. Different combinations of software flow control can be enabled by setting
different combinations of EFR[3:0].

Table 3

shows software flow control options.

Remark: When using software flow control, the Xon/Xoff characters cannot be used for
data characters.

There are two other enhanced features relating to software flow control:

Xon Any function (MCR[5]): Operation will resume after receiving any character
after recognizing the Xoff character. It is possible that an Xon1 character is
recognized as an Xon Any character, which could cause an Xon2 character to be
written to the RX FIFO.

Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the
special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The
Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the
RX FIFO.

6.3.1 RX

When software flow control operation is enabled, the SC16C754B will compare incoming
data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2 must be
received sequentially). When the correct Xoff character is received, transmission is halted
after completing transmission of the current character. Xoff detection also sets IIR[4] (if
enabled via IER[5]) and causes INT to go HIGH.

To resume transmission, an Xon1/Xon2 character must be received (in certain cases
Xon1 and Xon2 must be received sequentially). When the correct Xon characters are
received, IIR[4] is cleared, and the Xoff interrupt disappears.

Table 3:

Software flow control options (EFR[3:0])

EFR[3]

EFR[2]

EFR[1]

EFR[0]

TX, RX software flow controls

no transmit flow control

transmit Xon1, Xoff1

transmit Xon2, Xoff2

transmit Xon1, Xon2, Xoff1, Xoff2

no receive flow control

receiver compares Xon1, Xoff1

receiver compares Xon2, Xoff2

transmit Xon1, Xoff1

receiver compares Xon1 or Xon2, Xoff1 or Xoff2

transmit Xon2, Xoff2

receiver compares Xon1 or Xon2, Xoff1 or Xoff2

transmit Xon1, Xon2, Xoff1, Xoff2

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

no transmit flow control

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

13 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

6.3.2 TX

Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the HALT trigger level
programmed in TCR[3:0].

Xon1/Xon2 character is transmitted when the RX FIFO reaches the RESUME trigger level
programmed in TCR[7:4].

The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an
ordinary byte from the FIFO. This means that even if the word length is set to be 5, 6, or 7
characters, then the 5, 6, or 7 least significant bits of Xoff1/Xoff2 and Xon1/Xon2 will be
transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but
this functionality is included to maintain compatibility with earlier designs.)

It is assumed that software flow control and hardware flow control will never be enabled
simultaneously.

Figure 8

shows an example of software flow control.

6.3.3 Software flow control example

6.3.3.1

Assumptions

UART1 is transmitting a large text file to UART2. Both UARTs are using software flow
control with single character Xoff (0F) and Xon (0D) tokens. Both have Xoff threshold
(TCR[3:0] = F) set to 60, and Xon threshold (TCR[7:4] = 8) set to 32. Both have the
interrupt receive threshold (TLR[7:4] = D) set to 52.

Fig 8.

Software flow control example

TRANSMIT FIFO

PARALLEL-TO-SERIAL

SERIAL-TO-PARALLEL

Xon-1 WORD

Xon-2 WORD

Xoff-1 WORD

Xoff-2 WORD

RECEIVE FIFO

PARALLEL-TO-SERIAL

SERIAL-TO-PARALLEL

Xon-1 WORD

Xon-2 WORD

Xoff-1 WORD

Xoff-2 WORD

UART2

UART1

002aaa229

data

XoffXonXoff

compare

programmed

Xon-Xoff

characters

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

14 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

UART1 begins transmission and sends 52 characters, at which point UART2 will generate
an interrupt to its processor to service the RCV FIFO, but assumes the interrupt latency is
fairly long. UART1 will continue sending characters until a total of 60 characters have
been sent. At this time, UART2 will transmit a 0F to UART1, informing UART1 to halt
transmission. UART1 will likely send the 61

character while UART2 is sending the Xoff

character. Now UART2 is serviced and the processor reads enough data out of the RX
FIFO that the level drops to 32. UART2 will now send a 0D to UART1, informing UART1 to
resume transmission.

6.4 Reset

Table 4

summarizes the state of register after reset.

Remark: Registers DLL, DLH, SPR, Xon1, Xon2, Xoff1, Xoff2 are not reset by the
top-level reset signal RESET, that is, they hold their initialization values during reset.

Table 5

summarizes the state of registers after reset.

Table 4:

Register reset functions

Register

Reset control

Reset state

Interrupt enable register

RESET

all bits cleared

Interrupt identification register

RESET

bit 0 is set; all other bits cleared

FIFO control register

RESET

all bits cleared

Line control register

RESET

reset to 0001 1101 (1Dh)

Modem control register

RESET

all bits cleared

Line status register

RESET

bit 5 and bit 6 set; all other bits cleared

Modem status register

RESET

bits 3:0 cleared; bits 7:4 input signals

Enhanced feature register

RESET

all bits cleared

Receiver holding register

RESET

pointer logic cleared

Transmitter holding register

RESET

pointer logic cleared

Transmission control register

RESET

all bits cleared

Trigger level register

RESET

all bits cleared

Table 5:

Signal RESET functions

Signal

Reset control

Reset state

RESET

HIGH

RTS

RESET

HIGH

DTR

RESET

HIGH

RXRDY

RESET

HIGH

TXRDY

RESET

LOW

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

15 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

6.5 Interrupts

The SC16C754B has interrupt generation and prioritization (six prioritized levels of
interrupts) capability. The interrupt enable register (IER) enables each of the six types of
interrupts and the INT signal in response to an interrupt generation. The IER can also
disable the interrupt system by clearing bits 7:5 and 3:0. When an interrupt is generated,
the IIR indicates that an interrupt is pending and provides the type of interrupt through
IIR[5:0].

Table 6

summarizes the interrupt control functions.

It is important to note that for the framing error, parity error, and break conditions, LSR[7]
generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO,
and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always
represent the error status for the received character at the top of the RX FIFO. Reading
the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of
the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.

For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt
is cleared by an Xon flow character detection. If a special character detection caused the
interrupt, the interrupt is cleared by a read of the IIR.

Table 6:

Interrupt control functions

IIR[5:0]

Priority
level

Interrupt type

Interrupt source

Interrupt reset method

00 0001

None

none

00 0110

receiver line status

OE, FE, PE, or BI errors occur in
characters in the RX FIFO

FE, PE, BI: all erroneous
characters are read from the
RX FIFO.

OE: read LSR

00 1100

RX time-out

stale data in RX FIFO

read RHR

00 0100

RHR interrupt

DRDY (data ready)

(FIFO disable)

RX FIFO above trigger level

(FIFO enable)

read RHR

00 0010

THR interrupt

TFE (THR empty)

(FIFO disable)

TX FIFO passes above trigger level

(FIFO enable)

read IIR or a write to the THR

00 0000

modem status

MSR[3:0] = 0

read MSR

01 0000

Xoff interrupt

receive Xoff character(s)/special
character

receive Xon character(s)/Read of
IIR

10 0000

CTS, RTS

RTS pin or CTS pin change state from
active (LOW) to inactive (HIGH)

read IIR

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

16 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

6.5.1 Interrupt mode operation

In interrupt mode (if any bit of IER[3:0] is `1') the processor is informed of the status of the
receiver and transmitter by an interrupt signal, INT. Therefore, it is not necessary to
continuously poll the line status register (LSR) to see if any interrupt needs to be serviced.

Figure 9

shows interrupt mode operation.

6.5.2 Polled mode operation

In polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be
checked by polling the line status register (LSR). This mode is an alternative to the FIFO
interrupt mode of operation where the status of the receiver and transmitter is
automatically known by means of interrupts sent to the CPU.

Figure 10

shows FIFO polled

mode operation.

Fig 9.

Interrupt mode operation

IIR

IER

THR

RHR

PROCESSOR

IOW / IOR

INT

002aaa230

Fig 10. FIFO polled mode operation

LSR

IER

THR

RHR

PROCESSOR

IOW / IOR

002aaa231

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

17 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

6.6 DMA operation

There are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by
FCR[3].

In DMA mode 0 or FIFO disable (FCR[0] = 0) DMA occurs in single character transfers. In
DMA mode 1, multi-character (or block) DMA transfers are managed to relieve the
processor for longer periods of time.

6.6.1 Single DMA transfers (DMA mode 0/FIFO disable)

Figure 11

shows TXRDY and RXRDY in DMA mode 0/FIFO disable.

6.6.1.1

Transmitter

When empty, the TXRDY signal becomes active. TXRDY will go inactive after one
character has been loaded into it.

6.6.1.2

Receiver

RXRDY is active when there is at least one character in the FIFO. It becomes inactive
when the receiver is empty.

Fig 11. TXRDY and RXRDY in DMA mode 0/FIFO disable

wrptr

FIFO EMPTY

TXRDY

rdptr

FIFO EMPTY

RXRDY

002aaa232

at least one

location filled

at least one

location filled

TXRDY

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

18 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

6.6.2 Block DMA transfers (DMA mode 1)

Figure 12

shows TXRDY and RXRDY in DMA mode 1.

6.6.2.1

Transmitter

TXRDY is active when there is a trigger level number of spaces available. It becomes
inactive when the FIFO is full.

6.6.2.2

Receiver

RXRDY becomes active when the trigger level has been reached, or when a time-out
interrupt occurs. It will go inactive when the FIFO is empty or an error in the RX FIFO is
flagged by LSR[7].

6.7 Sleep mode

Sleep mode is an enhanced feature of the SC16C754B UART. It is enabled when EFR[4],
the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when:

The serial data input line, RX, is idle (see

Section 6.8 "Break and time-out

conditions"

The TX FIFO and TX shift register are empty.

There are no interrupts pending except THR and time-out interrupts.

Remark: Sleep mode will not be entered if there is data in the RX FIFO.

In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are
clocked using these clocks, the power consumption is greatly reduced. The UART will
wake up when any change is detected on the RX line, when there is any change in the
state of the modem input pins, or if data is written to the TX FIFO.

Remark: Writing to the divisor latches, DLL and DLH, to set the baud clock, must not be
done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4]
before writing to DLL or DLH.

Fig 12. TXRDY and RXRDY in DMA mode 1

wrptr

TXRDY

FIFO full

TXRDY

rdptr

FIFO EMPTY

RXRDY

002aaa869

trigger

level

trigger

level

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

19 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

6.8 Break and time-out conditions

An RX idle condition is detected when the receiver line, RX, has been HIGH for
4 character time. The receiver line is sampled midway through each bit.

When a break condition occurs, the TX line is pulled LOW. A break condition is activated
by setting LCR[6].

6.9 Programmable baud rate generator

The SC16C754B UART contains a programmable baud generator that takes any clock
input and divides it by a divisor in the range between 1 and (2

1). An additional

divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in

Figure 13

. The output frequency of the baud rate generator is 16

the baud rate. The

formula for the divisor is:

Where:

prescaler = 1, when MCR[7] is set to 0 after reset (divide-by-1 clock selected)

prescaler = 4, when MCR[7] is set to 1 after reset (divide-by-4 clock selected).

Remark: The default value of prescaler after reset is divide-by-1.

Figure 13

shows the internal prescaler and baud rate generator circuitry.

DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the
least significant and most significant byte of the baud rate divisor. If DLL and DLH are both
zero, the UART is effectively disabled, as no baud clock will be generated.

Remark: The programmable baud rate generator is provided to select both the transmit
and receive clock rates.

Table 7

and

Table 8

show the baud rate and divisor correlation for crystal with frequency

1.8432 MHz and 3.072 MHz, respectively.

Figure 14

shows the crystal clock circuit reference.

Fig 13. Prescaler and baud rate generator block diagram

divisor

XTAL1 crystal input frequency

prescaler

---------------------------------------------------------------------------

desired baud rate

(

)

---------------------------------------------------------------------------------

BAUD RATE

GENERATOR

LOGIC

MCR[7] = 1

MCR[7] = 0

PRESCALER

LOGIC

(DIVIDE-BY-1)

INTERNAL

OSCILLATOR

LOGIC

002aaa233

XTAL1

XTAL2

input clock

PRESCALER

LOGIC

(DIVIDE-BY-4)

reference
clock

internal
baud rate
clock for
transmitter
and receiver

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

21 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Register descriptions

Each register is selected using address lines A0, A1, A2, and in some cases, bits from
other registers. The programming combinations for register selection are shown in

Table 9

[1]

MCR[7] can only be modified when EFR[4] is set.

[2]

Accessed by a combination of address pins and register bits.

[3]

Accessible only when LCR[7] is logic 1.

[4]

Accessible only when LCR is set to 1011 1111 (xBF).

[5]

Accessible only when EFR[4] = 1 and MCR[6] = 1, that is, EFR[4] and MCR[6] are read/write enables.

[6]

Accessible only when CSA - CSD = 0, MCR[2] = 1, and loop-back is disabled (MCR[4] = 0).

Fig 14. Crystal oscillator connection

002aaa870

C2
47 pF

XTAL1

XTAL2

1.8432 MHz

C1
22 pF

C2
33 pF

XTAL1

XTAL2

1.5 k

1.8432 MHz

C1
22 pF

Table 9:

Register map - read/write properties

Read mode

Write mode

receive holding register (RHR)

transmit holding register (THR)

interrupt enable register (IER)

interrupt enable register

interrupt identification register (IIR)

FIFO control register (FCR)

line control register (LCR)

line control register

modem control register (MCR)

[1]

modem control register

[1]

line status register (LSR)

n/a

modem status register (MSR)

n/a

scratchpad register (SPR)

scratchpad register

divisor latch LSB (DLL)

[2] [3]

divisor latch LSB

[2] [3]

divisor latch MSB (DLH)

[2] [3]

divisor latch MSB

[2] [3]

enhanced feature register (EFR)

[2] [4]

enhanced feature register

[2] [4]

Xon1 word

[2] [4]

Xon1 word

[2] [4]

Xon2 word

[2] [4]

Xon2 word

[2] [4]

Xoff1 word

[2] [4]

Xoff1 word

[2] [4]

Xoff2 word

[2] [4]

Xoff2 word

[2] [4]

transmission control register (TCR)

[2] [5]

transmission control register

[2] [5]

trigger level register (TLR)

[2] [5]

trigger level register

[2] [5]

FIFO ready register

[2] [6]

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

22 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Table 10

lists and describes the SC16C754B internal registers.

[1]

These registers are accessible only when LCR[7] = 0.

[2]

This bit can only be modified if register bit EFR[4] is enabled, that is, if enhanced functions are enabled.

[3]

The Special Register set is accessible only when LCR[7] is set to a logic 1.

[4]

Enhanced Feature Register; Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to `BFh'.

Table 10:

SC16C754B internal registers

A2 A1 A0 Register Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Read/
Write

General Register set

[1]

RHR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

THR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

IER

0/CTS
interrupt
enable

[2]

0/RTS
interrupt
enable

[2]

0/Xoff

[2]

0/X Sleep
mode

[2]

modem
status
interrupt

receive
line status
interrupt

THR
empty
interrupt

Rx data
available
interrupt

R/W

FCR

RX
trigger
level
(MSB)

RX trigger
level (LSB)

0/TX
trigger
level
(MSB)

[2]

0/TX
trigger
level
(LSB)

[2]

DMA
mode
select

TX FIFO
reset

RX FIFO
reset

FIFO
enable

IIR

FCR[0]

0/CTS,
RTS

0/Xoff

interrupt
priority
bit 2

interrupt
priority
bit 1

interrupt
priority
bit 0

interrupt
status

LCR

DLAB

break
control bit

set parity

parity type
select

parity
enable

number of
stop bits

word
length
bit 1

word
length
bit 0

R/W

MCR

clock

[2]

TCR and
TLR
enable

[2]

0/Xon
Any

[2]

0/enable
loop-back

IRQ
enable
OP

FIFO
ready
enable

RTS

DTR

R/W

LSR

0/error in
RX FIFO

THR and
TSR empty

THR
empty

break
interrupt

framing
error

parity error overrun

error

data in
receiver

MSR

DSR

CTS

DSR

CTS

SPR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

TCR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

TLR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

FIFO
Rdy

RX FIFO
D status

RX FIFO
C status

RX FIFO
B status

RX FIFO
A status

TX FIFO
D status

TX FIFO
C status

TX FIFO
B status

TX FIFO
A status

Special Register set

[3]

DLL

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

DLH

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

R/W

Enhanced Register set

[4]

EFR

Auto CTS Auto RTS

Special
character
detect

Enable
enhanced
functions

[2]

software
flow
control
bit 3

software
flow
control
bit 2

software
flow
control
bit 1

software
flow
control
bit 0

R/W

Xon1

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

Xon2

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

Xoff1

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

Xoff2

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

23 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Remark: Refer to the notes under

Table 9

for more register access information.

7.1 Receiver Holding Register (RHR)

The receiver section consists of the Receiver Holding Register (RHR) and the Receiver
Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data
from the RX terminal. The data is converted to parallel data and moved to the RHR. The
receiver section is controlled by the Line Control Register (LCR). If the FIFO is disabled,
location zero of the FIFO is used to store the characters.

Remark: In this case, characters are overwritten if overflow occurs.

If overflow occurs, characters are lost. The RHR also stores the error status bits
associated with each character.

7.2 Transmit Holding Register (THR)

The transmitter section consists of the Transmit Holding Register (THR) and the Transmit
Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and
shifts it into the TSR, where it is converted to serial data and moved out on the TX
terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are
lost if overflow occurs.

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

24 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.3 FIFO Control Register (FCR)

This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting
transmitter and receiver trigger levels, and selecting the type of DMA signalling.

Table 11

shows FIFO control register bit settings.

Table 11:

FIFO Control Register bits description

Bit

Symbol

Description

7:6

FCR[7] (MSB),
FCR[6] (LSB)

RCVR trigger. Sets the trigger level for the RX FIFO.

00 - 8 characters

01 - 16 characters

10 - 56 characters

11 - 60 characters

5:4

FCR[5] (MSB),
FCR[4] (LSB)

TX trigger. Sets the trigger level for the TX FIFO.

00 - 8 spaces

01 - 16 spaces

10 - 32 spaces

11 - 56 spaces

FCR[5:4] can only be modified and enabled when EFR[4] is set. This is
because the transmit trigger level is regarded as an enhanced function.

FCR[3]

DMA mode select.

logic 0 = Set DMA mode `0'

logic 1 = Set DMA mode `1'

FCR[2]

Reset TX FIFO.

logic 0 = no FIFO transmit reset (normal default condition)

logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.

FCR[1]

Reset RX FIFO.

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.

FCR[0]

FIFO enable.

logic 0 = disable the transmit and receive FIFO (normal default
condition)

logic 1 = enable the transmit and receive FIFO

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

25 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.4 Line Control Register (LCR)

This register controls the data communication format. The word length, number of stop
bits, and parity type are selected by writing the appropriate bits to the LCR.

Table 12

shows the line control register bit settings.

Table 12:

Line Control Register bits description

Bit

Symbol

Description

LCR[7]

Divisor latch enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch enabled

LCR[6]

Break control bit. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0 state). This
condition exists until disabled by setting LCR[6] to a logic 0.

logic 0 = no TX break condition (normal default condition)

logic 1 = forces the transmitter output (TX) to a logic 0 to alert the
communication terminal to a line break condition

LCR[5]

Set parity. LCR[5] selects the forced parity format (if LCR[3] = 1).

logic 0 = parity is not forced (normal default condition)

LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1 for
the transmit and receive data

LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0 for
the transmit and receive data

LCR[4]

Parity type select.

logic 0 = odd parity is generated (if LCR[3] = 1)

logic 1 = even parity is generated (if LCR[3] = 1)

LCR[3]

Parity enable.

logic 0 = no parity (normal default condition)

logic 1 = a parity bit is generated during transmission and the receiver
checks for received parity

LCR[2]

Number of stop bits. Specifies the number of stop bits.

0 = 1 stop bit (word length = 5, 6, 7, 8)

1 = 1.5 stop bits (word length = 5)

1 = 2 stop bits (word length = 6, 7, 8)

1:0

LCR[1:0]

Word length bits 1, 0. These two bits specify the word length to be
transmitted or received.

00 - 5 bits

01 - 6 bits

10 - 7 bits

11 - 8 bits

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

26 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.5 Line Status Register (LSR)

Table 13

shows the line status register bit settings.

When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the
top of the RX FIFO (next character to be read). The LSR[4:2] registers do not physically
exist, as the data read from the RX FIFO is output directly onto the output data bus,
DI[4:2], when the LSR is read. Therefore, errors in a character are identified by reading
the LSR and then reading the RHR.

LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when
there are no more errors remaining in the FIFO.

Reading the LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO
read pointer is incremented by reading the RHR.

Table 13:

Line Status Register bits description

Bit

Symbol

Description

LSR[7]

FIFO data error.

logic 0 = no error (normal default condition)

logic 1 = at least one parity error, framing error, or break indication is in the
receiver FIFO. This bit is cleared when no more errors are present in the
FIFO.

LSR[6]

THR and TSR empty. This bit is the Transmit Empty indicator.

logic 0 = transmitter hold and shift registers are not empty

logic 1 = transmitter hold and shift registers are empty

LSR[5]

THR empty. This bit is the Transmit Holding Register Empty indicator.

logic 0 = Transmit Hold Register is not empty

logic 1 = Transmit Hold Register is empty. The processor can now load up
to 64 bytes of data into the THR if the TX FIFO is enabled.

LSR[4]

Break interrupt.

logic 0 = no break condition (normal default condition)

logic 1 = a break condition occurred and associated byte is 00, that is,
RX was LOW for one character time frame

LSR[3]

Framing error.

logic 0 = no framing error in data being read from RX FIFO (normal default
condition)

logic 1 = framing error occurred in data being read from RX FIFO, that is,
received data did not have a valid stop bit

LSR[2]

Parity error.

logic 0 = no parity error (normal default condition)

logic 1 = parity error in data being read from RX FIFO

LSR[1]

Overrun error.

logic 0 = no overrun error (normal default condition)

logic 1 = overrun error has occurred

LSR[0]

Data in receiver.

logic 0 = no data in receive FIFO (normal default condition)

logic 1 = at least one character in the RX FIFO

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

27 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.6 Modem Control Register (MCR)

The MCR controls the interface with the modem, data set, or peripheral device that is
emulating the modem.

Table 14

shows Modem Control Register bit settings.

[1]

MCR[7:5] can only be modified when EFR[4] is set, that is, EFR[4] is a write enable.

Table 14:

Modem Control Register bits description

Bit

Symbol

Description

MCR[7]

[1]

Clock select.

logic 0 = divide-by-1 clock input

logic 1 = divide-by-4 clock input

MCR[6]

[1]

TCR and TLR enable.

logic 0 = no action

logic 1 = enable access to the TCR and TLR registers

MCR[5]

[1]

Xon Any.

logic 0 = disable Xon Any function

logic 1 = enable Xon Any function

MCR[4]

Enable loop-back.

logic 0 = normal operating mode

Logic 1 = enable local loop-back mode (internal). In this mode the
MCR[3:0] signals are looped back into MSR[7:4] and the TX output is
looped back to the RX input internally.

MCR[3]

IRQ enable OP.

logic 0 = forces INTA-INTB outputs to the 3-state mode and OP output
to HIGH state

logic 1 = forces the INTA-INTB outputs to the active state and OP
output to LOW state. In loop-back mode, controls MSR[7].

MCR[2]

FIFO Ready enable.

logic 0 = disable the FIFO Rdy register

logic 1 = enable the FIFO Rdy register. In loop-back mode, controls
MSR[6].

MCR[1]

RTS

logic 0 = force RTS output to inactive (HIGH)

logic 1 = force RTS output to active (LOW).
In loop-back mode, controls MSR[4]. If Auto-RTS is enabled, the RTS
output is controlled by hardware flow control.

MCR[0]

DTR

logic 0 = force DTR output to inactive (HIGH)

logic 1 = force DTR output to active (LOW).
In loop-back mode, controls MSR[5].

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

28 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.7 Modem Status Register (MSR)

This 8-bit register provides information about the current state of the control lines from the
modem, data set, or peripheral device to the processor. It also indicates when a control
input from the modem changes state.

Table 15

shows Modem Status Register bit settings

per channel.

[1]

The primary inputs RI, CD, CTS, DSR are all active LOW, but their registered equivalents in the MSR and
MCR (in loop-back) registers are active HIGH.

Table 15:

Modem Status Register bits description

Bit

Symbol

Description

MSR[7]

[1]

CD (active HIGH, logical 1). This bit is the complement of the CD input
during normal mode. During internal loop-back mode, it is equivalent to
MCR[3].

MSR[6]

[1]

RI (active HIGH, logical 1). This bit is the complement of the RI input during
normal mode. During internal loop-back mode, it is equivalent to MCR[2].

MSR[5]

[1]

DSR (active HIGH, logical 1). This bit is the complement of the DSR input
during normal mode. During internal loop-back mode, it is equivalent
MCR[0].

MSR[4]

[1]

CTS (active HIGH, logical 1). This bit is the complement of the CTS input
during normal mode. During internal loop-back mode, it is equivalent to
MCR[1].

MSR[3]

CD. Indicates that CD input (or MCR[3] in loop-back mode) has changed

state. Cleared on a read.

MSR[2]

RI. Indicates that RI input (or MCR[2] in loop-back mode) has changed

state from LOW to HIGH. Cleared on a read.

MSR[1]

DSR. Indicates that DSR input (or MCR[0] in loop-back mode) has changed

state. Cleared on a read.

MSR[0]

CTS. Indicates that CTS input (or MCR[1] in loop-back mode) has changed

state. Cleared on a read.

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

29 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.8 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver
error, RHR interrupt, THR interrupt, Xoff received, or CTS/RTS change of state from LOW
to HIGH. The INT output signal is activated in response to interrupt generation.

Table 16

shows Interrupt Enable Register bit settings.

[1]

IER[7:4] can only be modified if EFR[4] is set, that is, EFR[4] is a write enable. Re-enabling IER[1] will
cause a new interrupt if the THR is below the threshold.

Table 16:

Interrupt Enable Register bits description

Bit

Symbol

Description

IER[7]

[1]

CTS interrupt enable.

logic 0 = disable the CTS interrupt (normal default condition)

logic 1 = enable the CTS interrupt

IER[6]

[1]

RTS interrupt enable.

logic 0 = disable the RTS interrupt (normal default condition)

logic 1 = enable the RTS interrupt

IER[5]

[1]

Xoff interrupt.

logic 0 = disable the Xoff interrupt (normal default condition)

logic 1 = enable the Xoff interrupt

IER[4]

[1]

Sleep mode.

logic 0 = disable Sleep mode (normal default condition)

logic 1 = enable Sleep mode. See

Section 6.7 "Sleep mode"

for details.

IER[3]

Modem Status Interrupt.

logic 0 = disable the modem status register interrupt (normal default
condition)

logic 1 = enable the modem status register interrupt

IER[2]

Receive Line Status interrupt.

logic 0 = disable the receiver line status interrupt (normal default condition)

logic 1 = enable the receiver line status interrupt

IER[1]

Transmit Holding Register interrupt.

logic 0 = disable the THR interrupt (normal default condition)

logic 1 = enable the THR interrupt

IER[0]

Receive Holding Register interrupt.

logic 0 = disable the RHR interrupt (normal default condition)

logic 1 = enable the RHR interrupt

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

30 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.9 Interrupt Identification Register (IIR)

The IIR is a read-only 8-bit register which provides the source of the interrupt in a
prioritized manner.

Table 17

shows Interrupt Identification Register bit settings.

The interrupt priority list is shown in

Table 18

Table 17:

Interrupt Identification Register bits description

Bit

Symbol

Description

7-6

IIR[7:6]

Mirror the contents of FCR[0].

IIR[5]

RTS/CTS LOW-to-HIGH change of state.

IIR[4]

1 = Xoff/Special character has been detected.

3-1

IIR[3:1]

3-bit encoded interrupt. See

Table 18

IIR[0]

Interrupt status.

logic 0 = an interrupt is pending

logic 1 = no interrupt is pending

Table 18:

Interrupt priority list

Priority
level

IIR[5]

IIR[4]

IIR[3]

IIR[2]

IIR[1]

IIR[0]

Source of the interrupt

Receiver Line Status error

Receiver time-out interrupt

RHR interrupt

THR interrupt

Modem interrupt

Received Xoff signal/
special character

CTS, RTS change of state from
active (LOW) to inactive (HIGH)

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

31 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.10 Enhanced Feature Register (EFR)

This 8-bit register enables or disables the enhanced features of the UART.

Table 19

shows

the Enhanced Feature Register bit settings.

7.11 Divisor latches (DLL, DLH)

These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLH stores the most significant part of the divisor. DLL stores
the least significant part of the divisor.

Note that DLL and DLH can only be written to before Sleep mode is enabled, that is,
before IER[4] is set.

Table 19:

Enhanced Feature Register bits description

Bit

Symbol

Description

EFR[7]

CTS flow control enable.

logic 0 = CTS flow control is disabled (normal default condition)

logic 1 = CTS flow control is enabled. Transmission will stop when a HIGH
signal is detected on the CTS pin.

EFR[6]

RTS flow control enable.

logic 0 = RTS flow control is disabled (normal default condition)

logic 1 = RTS flow control is enabled. The RTS pin goes HIGH when the
receiver FIFO HALT trigger level TCR[3:0] is reached, and goes LOW when
the receiver FIFO RESUME transmission trigger level TCR[7:4] is reached.

EFR[5]

Special character detect.

logic 0 = special character detect disabled (normal default condition)

logic 1 = special character detect enabled. Received data is compared with
Xoff2 data. If a match occurs, the received data is transferred to FIFO and
IIR[4] is set to a logical 1 to indicate a special character has been detected.

EFR[4]

Enhanced functions enable bit.

logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4],
MCR[7:5].

logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5]
can be modified, that is, this bit is therefore a write enable.

3:0

EFR[3:0]

Combinations of software flow control can be selected by programming these
bits. See

Table 3 "Software flow control options (EFR[3:0])"

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

32 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.12 Transmission Control Register (TCR)

This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission
during hardware/software flow control.

Table 20

shows Transmission Control Register bit

settings.

TCR trigger levels are available from 0 to 60 bytes with a granularity of four.

Remark: TCR can only be written to when EFR[4] = 1 and MCR[6] = 1. The programmer
must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware
check to make sure this condition is met. Also, the TCR must be programmed with this
condition before Auto-RTS or software flow control is enabled to avoid spurious operation
of the device.

7.13 Trigger Level Register (TLR)

This 8-bit register is used to store the transmit and received FIFO trigger levels used for
DMA and interrupt generation. Trigger levels from 4 to 60 can be programmed with a
granularity of 4.

Table 21

shows Trigger Level Register bit settings.

Remark: TLR can only be written to when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or
TLR[7:4] are logical 0, the selectable trigger levels via the FIFO Control Register (FCR)
are used for the transmit and receive FIFO trigger levels. Trigger levels from 4 to 60 bytes
are available with a granularity of four. The TLR should be programmed for

, where N is

the desired trigger level.

7.14 FIFO ready register

The FIFO ready register provides real-time status of the transmit and receive FIFOs of
both channels.

Table 20:

Transmission Control Register bits description

Bit

Symbol

Description

7:4

TCR[7:4]

RX FIFO trigger level to resume transmission (0-60).

3:0

TCR[3:0]

RX FIFO trigger level to halt transmission (0-60).

Table 21:

Trigger Level Register bits description

Bit

Symbol

Description

7:4

TLR[7:4]

RX FIFO trigger levels (4 to 60), number of characters available.

3:0

TLR[3:0]

TX FIFO trigger levels (4 to 60), number of spaces available.

Table 22:

FIFO ready register bits description

Bit

Symbol

Description

7:4

FIFO Rdy[7:4]

0 = there are less than a RX trigger level number of characters in the
RX FIFO

1 = the RX FIFO has more than a RX trigger level number of characters
available for reading or a time-out condition has occurred

3:0

FIFO Rdy[3:0]

0 = there are less than a TX trigger level number of spaces available in
the TX FIFO

1 = there are at least a TX trigger level number of spaces available in the
TX FIFO

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

33 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

The FIFO Rdy register is a read-only register that can be accessed when any of the two
UARTs is selected CSA - CSD = 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and loop-back
is disabled. The address is 111.

Programmer's guide

The base set of registers that is used during high-speed data transfer have a
straightforward access method. The extended function registers require special access
bits to be decoded along with the address lines. The following guide will help with
programming these registers. Note that the descriptions below are for individual register
access. Some streamlining through interleaving can be obtained when programming all
the registers.

Table 23:

Register programming guide

Command

Actions

set baud rate to VALUE1, VALUE2

read LCR (03), save in temp

set LCR (03) to 80

set DLL (00) to VALUE1

set DLM (01) to VALUE2

set LCR (03) to temp

set Xoff1, Xon1 to VALUE1, VALUE2

read LCR (03), save in temp

set LCR (03) to BF

set Xoff1 (06) to VALUE1

set Xon1 (04) to VALUE2

set LCR (03) to temp

set Xoff2, Xon2 to VALUE1, VALUE2

read LCR (03), save in temp

set LCR (03) to BF

set Xoff-2 (07) to VALUE1

set Xon-2 (05) to VALUE2

set LCR (03) to temp

set software flow control mode to VALUE

read LCR (03), save in temp

set LCR (03) to BF

set EFR (02) to VALUE

set LCR (03) to temp

set flow control threshold to VALUE

read LCR (03), save in temp1

set LCR (03) to BF

read EFR (02), save in temp2

set EFR (02) to 10 + temp2

set LCR (03) to 00

read MCR (04), save in temp3

set MCR (04) to 40 + temp3

set TCR (06) to VALUE

set MCR (04) to temp3

set LCR (03) to BF

set EFR (02) to temp2

set LCR (03) to temp1

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

34 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

[1]

sign here means bit-AND.

set TX FIFO and RX FIFO thresholds
to VALUE

read LCR (03), save in temp1

set LCR (03) to BF

read EFR (02), save in temp2

set EFR (02) to 10 + temp2

set LCR (03) to 00

read MCR (04), save in temp3

set MCR (04) to 40 + temp3

set TLR (07) to VALUE

set MCR (04) to temp3

set LCR (03) to BF

set EFR (02) to temp2

set LCR (03) to temp1

read FIFO Rdy register

read MCR (04), save in temp1

set temp2 = temp1

[1]

set MCR (04) = 40 + temp2

read FFR (07), save in temp2

pass temp2 back to host

set MCR (04) to temp1

set prescaler value to divide-by-1

read LCR (03), save in temp1

set LCR (03) to BF

read EFR (02), save in temp2

set EFR (02) to 10 + temp2

set LCR (03) to 00

read MCR (04), save in temp3

set MCR (04) to temp3

[1]

set LCR (03) to BF

set EFR (02) to temp2

set LCR (03) to temp1

set prescaler value to divide-by-4

read LCR (03), save in temp1

ret LCR (03) to BF

read EFR (02), save in temp2

set EFR (02) to 10 + temp2

set LCR (03) to 00

read MCR (04), save in temp3

set MCR (04) to temp3 + 80

set LCR (03) to BF

set EFR (02) to temp2

set LCR (03) to temp1

Table 23:

Register programming guide

...continued

Command

Actions

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

36 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

10. Static characteristics

[1]

Meets TTL levels, V

IO(min)

= 2 V and V

IH(max)

= 0.8 V on non-hysteresis inputs.

[2]

Applies for external output buffers.

[3]

These parameters apply for D7 to D0.

[4]

These parameters apply for DTRA, DTRB, INIA, INTB, RTSA, RTSB, RXRDYA, RXRDYB, TXRDYA, TXRDYB, TXA, TXB.

[5]

Except XTAL2, V

= 1 V typical.

[6]

These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150

C. The customer is

responsible for verifying junction temperature.

[7]

Applies to external clock; crystal oscillator max. 24 MHz.

[8]

Measurement condition, normal operation other than Sleep mode:

= 3.3 V; T

amb

= 25

C. Full duplex serial activity on all two serial (UART) channels at the clock frequency specified in the

recommended operating conditions with divisor of 1.

[9]

When using crystal oscillator. The use of an external clock will increase the sleep current.

Table 25:

Static characteristics

Tolerance of V

10 %, unless otherwise specified.

Symbol

Parameter

Conditions

= 2.5 V

= 3.3 V and 5 V

Unit

Min

Typ

Max

Min

Typ

Max

supply voltage

10 %

+ 10 % V

10 %

+ 10 % V

input voltage

HIGH-level input
voltage

[1]

1.6

2.0

LOW-level input
voltage

[1]

0.65

0.8

output voltage

[2]

HIGH-level
output voltage

8 mA

[3]

2.0

4 mA

[4]

2.0

800

[3]

1.85

400

[4]

1.85

LOW-level output
voltage

[5]

= 8 mA

[3]

0.4

= 4 mA

[4]

0.4

= 2 mA

[3]

0.4

= 1.6 mA

[4]

0.4

input capacitance

amb

ambient
temperature

operating in
free air

+25

+85

+25

+85

junction
temperature

[6]

125

(i)XTAL1

crystal input
frequency

[7]

MHz

clock duty cycle

supply current

f = 5 MHz

[8]

4.5

CCsleep

sleep current

[9]

200

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

37 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

11. Dynamic characteristics

[1]

Applies to external clock, crystal oscillator max 24 MHz.

Table 26:

Dynamic characteristics

amb

C to +85

C; tolerance of V

10 %, unless otherwise specified.

Symbol Parameter

Conditions

= 2.5 V

= 3.3 V

= 5.0 V

Unit

Min

Max

Min

Max

Min

Max

, t

clock pulse duration

XTAL

oscillator/clock frequency

[1] [2]

MHz

address setup time

address hold time

IOR delay from chip select

IOR strobe width

25 pF load

chip select hold time from IOR

read cycle delay

25 pF load

12d

delay from IOR to data

25 pF load

12h

data disable time

25 pF load

13d

IOW delay from chip select

13w

IOW strobe width

13h

chip select hold time from IOW

15d

write cycle delay

16s

data setup time

16h

data hold time

17d

delay from IOW to output

25 pF load

100

18d

delay to set interrupt from
Modem input

25 pF load

100

19d

delay to reset interrupt from
IOR

25 pF load

100

20d

delay from stop to set interrupt

RCLK

[3]

RCLK

[3]

RCLK

[3]

21d

delay from IOR to reset
interrupt

25 pF load

100

22d

delay from start to set interrupt

100

23d

delay from IOW to transmit
start

RCLK

[3]

24T

RCLK

[3]

RCLK

[3]

24T

RCLK

[3]

RCLK

[3]

24T

RCLK

[3]

24d

delay from IOW to reset
interrupt

100

25d

delay from stop to set RXRDY

RCLK

[3]

RCLK

[3]

RCLK

[3]

26d

delay from IOR to reset RXRDY

100

27d

delay from IOW to set TXRDY

100

28d

delay from start to reset
TXRDY

RCLK

[3]

RCLK

[3]

RCLK

[3]

RESET

RESET pulse width

200

baud rate divisor

1) 1

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

43 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

12. Package outline

Fig 25. Package outline SOT414-1 (LQFP64)

UNIT

max.

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

1.6

0.15
0.05

1.45
1.35

0.25

0.23
0.13

0.20
0.09

7.1
6.9

0.4

9.15
8.85

0.64
0.36

7
0

0.08

0.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75
0.45

SOT414-1

136E06

MS-026

00-01-19
03-02-20

(1)

7.1
6.9

9.15
8.85

0.64
0.36

detail X

(A )

Z D

Z E

pin 1 index

2.5

5 mm

scale

LQFP64: plastic low profile quad flat package; 64 leads; body 7 x 7 x 1.4 mm

SOT414-1

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

44 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Fig 26. Package outline SOT315-1 (LQFP80)

UNIT

max.

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

1.6

0.16
0.04

1.5
1.3

0.25

0.27
0.13

0.18
0.12

12.1
11.9

0.5

14.15
13.85

1.45
1.05

7
0

0.15

0.1

0.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75
0.30

SOT315-1

136E15

MS-026

00-01-19
03-02-25

(1)

12.1
11.9

14.15
13.85

1.45
1.05

detail X

(A )

Z D

Z E

pin 1 index

10 mm

scale

LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm

SOT315-1

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

45 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Fig 27. Package outline SOT188-2 (PLCC68)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

SOT188-2

detail X

(A )

Z D

Z E

pin 1 index

112E10

MS-018

EDR-7319

10 mm

scale

99-12-27
01-11-14

PLCC68: plastic leaded chip carrier; 68 leads

SOT188-2

UNIT

4.57
4.19

0.51

3.3

0.53
0.33

0.021
0.013

1.27

2.16

0.18

0.1

0.18

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

24.33
24.13

25.27
25.02

2.16

0.81
0.66

1.22
1.07

0.180
0.165

0.02

0.13

0.25

0.01

0.05

0.085

0.007 0.004

0.007

1.44
1.02

0.057
0.040

0.958
0.950

24.33
24.13

0.958
0.950

0.995
0.985

25.27
25.02

0.995
0.985

23.62
22.61

0.93
0.89

23.62
22.61

0.93
0.89

0.085

0.032
0.026

0.048
0.042

inches

min.

max.

(1)

max.

(1)

max.

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

46 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

13. Soldering

13.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of
soldering ICs can be found in our

Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is recommended.

13.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)
vary between 100 seconds and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215

C to 270

C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

below 225

C (SnPb process) or below 245

C (Pb-free process)

for all BGA, HTSSON..T and SSOP..T packages

for packages with a thickness

2.5 mm

for packages with a thickness < 2.5 mm and a volume

350 mm

so called

thick/large packages.

below 240

C (SnPb process) or below 260

C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm

so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

13.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically
developed.

If wave soldering is used the following conditions must be observed for optimal results:

Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

47 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

For packages with leads on four sides, the footprint must be placed at a 45

angle to

the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250

or 265

C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.

13.4 Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300

When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270

C and 320

13.5 Package related soldering information

[1]

For more detailed information on the BGA packages refer to the

(LF)BGA Application Note (AN01026);

order a copy from your Philips Semiconductors sales office.

[2]

All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal or
external package cracks may occur due to vaporization of the moisture in them (the so called popcorn
effect). For details, refer to the Drypack information in the

Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[3]

These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no
account be processed through more than one soldering cycle or subjected to infrared reflow soldering with
peak temperature exceeding 217

C measured in the atmosphere of the reflow oven. The package

body peak temperature must be kept as low as possible.

Table 27:

Suitability of surface mount IC packages for wave and reflow soldering methods

Package

[1]

Soldering method

Wave

Reflow

[2]

BGA, HTSSON..T

[3]

, LBGA, LFBGA, SQFP,

SSOP..T

[3]

, TFBGA, VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS

not suitable

[4]

suitable

PLCC

[5]

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

[5] [6]

suitable

SSOP, TSSOP, VSO, VSSOP

not recommended

[7]

suitable

CWQCCN..L

[8]

, PMFP

[9]

, WQCCN..L

[8]

not suitable

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

48 of 50

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

[4]

These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the
solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink
on the top side, the solder might be deposited on the heatsink surface.

[5]

If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6]

Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7]

Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger
than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8]

Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by
using a hot bar soldering process. The appropriate soldering profile can be provided on request.

[9]

Hot bar soldering or manual soldering is suitable for PMFP packages.

14. Revision history

Table 28:

Revision history

Document ID

Release date

Data sheet status

Change notice

Doc. number

Supersedes

SC16C754B_2

20050613

Product data sheet

9397 750 14668

SC16C754B_1

Modifications:

Section 1 "General description"

, 3rd paragraph: added `LQFP64'

Section 2 "Features"

, 4th bullet: changed `baud rate' to `data rate' (2 places)

Table 1 "Ordering information"

: added LQFP64 package offering

Figure 2 "Pin configuration for LQFP64"

added

Table 2 "Pin description"

added column for LQFP64 pinning

descriptions for CLKSEL, INTSEL, RXRDY, TXRDY modified to indicate the package-type to

which they apply

Table 10 "SC16C754B internal registers"

: shading removed, replaced with reference to

Table

note 2

Table 24 "Limiting values"

: table note removed (statement shown in

Section 17 "Disclaimers"

)

Table 25 "Static characteristics"

description following title changed from `V

= 2.5 V, 3.3 V

10 % or 5 V

10 %' to

`Tolerance of V

10 %; unless otherwise specified.'

Added `V

=' to value limits column headings

Table note 5

: changed `x

' to `XTAL2'

Table 26 "Dynamic characteristics"

symbol `t

' changed to `f

XTAL

'; added reference to (new)

Table note 2

under values for t

20d

, t

23d

, t

25d

, t

28d

: changed `RCLK cycles' to `T

RCLK

'; added reference to

Table note 3

; added unit `ns'

symbol N: removed `RCLK cycle(s)' from values (N is a number)

added (new)

Table note 2

Figure 25 "Package outline SOT414-1 (LQFP64)"

added

Section 18 "Trademarks"

added

SC16C754B_1

20050127

Product data sheet

9397 750 13114

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

9397 750 14668

Product data sheet

Rev. 02 -- 13 June 2005

49 of 50

15. Data sheet status

[1]

Please consult the most recently issued data sheet before initiating or completing a design.

[2]

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

16. Definitions

Short-form specification -- The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.

Application information -- Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.

17. Disclaimers

Life support -- These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status `Production'),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.

18. Trademarks

Notice -- All referenced brands, product names, service names and
trademarks are the property of their respective owners.

19. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com

Level

Data sheet status

[1]

Product status

[2] [3]

Definition

Objective data

Development

This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Qualification

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.

Date of release: 13 June 2005

Document number: 9397 750 14668

Published in The Netherlands

Philips Semiconductors

SC16C754B

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

20. Contents

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pinning information . . . . . . . . . . . . . . . . . . . . . . 4

5.1

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

Functional description . . . . . . . . . . . . . . . . . . . 9

6.1

Trigger levels. . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.2

Hardware flow control . . . . . . . . . . . . . . . . . . . 10

6.2.1

Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6.2.2

Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6.3

Software flow control . . . . . . . . . . . . . . . . . . . 12

6.3.1

RX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.3.2

TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.3.3

Software flow control example . . . . . . . . . . . . 13

6.3.3.1

Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.4

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.5

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.5.1

Interrupt mode operation . . . . . . . . . . . . . . . . 16

6.5.2

Polled mode operation . . . . . . . . . . . . . . . . . . 16

6.6

DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 17

6.6.1

Single DMA transfers (DMA mode 0/FIFO
disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.6.1.1

Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.6.1.2

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.6.2

Block DMA transfers (DMA mode 1). . . . . . . . 18

6.6.2.1

Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.6.2.2

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.7

Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.8

Break and time-out conditions . . . . . . . . . . . . 19

6.9

Programmable baud rate generator . . . . . . . . 19

Register descriptions . . . . . . . . . . . . . . . . . . . 21

7.1

Receiver Holding Register (RHR) . . . . . . . . . . 23

7.2

Transmit Holding Register (THR) . . . . . . . . . . 23

7.3

FIFO Control Register (FCR) . . . . . . . . . . . . . 24

7.4

Line Control Register (LCR) . . . . . . . . . . . . . . 25

7.5

Line Status Register (LSR) . . . . . . . . . . . . . . . 26

7.6

Modem Control Register (MCR) . . . . . . . . . . . 27

7.7

Modem Status Register (MSR). . . . . . . . . . . . 28

7.8

Interrupt Enable Register (IER) . . . . . . . . . . . 29

7.9

Interrupt Identification Register (IIR). . . . . . . . 30

7.10

Enhanced Feature Register (EFR) . . . . . . . . . 31

7.11

Divisor latches (DLL, DLH) . . . . . . . . . . . . . . . 31

7.12

Transmission Control Register (TCR) . . . . . . . 32

7.13

Trigger Level Register (TLR). . . . . . . . . . . . . . 32

7.14

FIFO ready register. . . . . . . . . . . . . . . . . . . . . 32

Programmer's guide . . . . . . . . . . . . . . . . . . . . 33

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 35

Static characteristics . . . . . . . . . . . . . . . . . . . 36

Dynamic characteristics . . . . . . . . . . . . . . . . . 37

11.1

Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 38

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 43

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

13.1

Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

13.2

Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 46

13.3

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 46

13.4

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 47

13.5

Package related soldering information . . . . . . 47

Revision history . . . . . . . . . . . . . . . . . . . . . . . 48

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 49

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Contact information . . . . . . . . . . . . . . . . . . . . 49

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SC16C754BIB80

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SC16C754BIB80