General description

The SC16IS752/SC16IS762 is an I

C-bus/SPI bus interface to a dual-channel high

performance UART offering data rates up to 5 Mbit/s, low operating and sleeping current;
it also provides the application with 8 additional programmable I/O pins. The device comes
in very small HVQFN32 and TSSOP28 packages, which makes it ideally suitable for
hand-held, battery operated applications. This chip enables seamless protocol conversion
from I

C-bus/SPI to RS-232/RS-485 and is fully bidirectional.

The SC16IS762 differs from the SC16IS752 in that it supports SPI clock speeds up to
15 Mbit/s instead of the 4 Mbit/s supported by the SC16IS752, and in that it supports IrDA
SIR up to 1.152 Mbit/s. In all other aspects, the SC16IS762 is functionally and electrically
the same as the SC16IS752.

The SC16IS752/SC16IS762's internal register set is backward compatible with the widely
used and widely popular 16C450. This allows the software to be easily written or ported
from another platform.

The SC16IS752/SC16IS762 also provides additional advanced features such as auto
hardware and software flow control, automatic RS-485 support and software reset. This
allows the software to reset the UART at any moment, independent of the hardware reset
signal.

Features

2.1 General features

Dual full-duplex UART

C-bus or SPI interface selectable

3.3 V or 2.5 V operation

Industrial temperature range:

C to +85

64 bytes FIFO (transmitter and receiver)

Fully compatible with industrial standard 16C450 and equivalent

Baud rates up to 5 Mbit/s in 16

clock mode

Auto hardware flow control using RTS/CTS

Auto software flow control with programmable Xon/Xoff characters

Single or double Xon/Xoff characters

Automatic RS-485 support (automatic slave address detection)

Up to eight programmable I/O pins

RS-485 driver direction control via RTS signal

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64 bytes of transmit

and receive FIFOs, IrDA SIR built-in support

Rev. 01 -- 4 January 2006

Product data sheet

9397 750 14333

Product data sheet

Rev. 01 -- 4 January 2006

2 of 59

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

RS-485 driver direction control inversion

Built-in IrDA encoder and decoder supporting IrDA SIR with speeds up to 115.2 kbit/s

SC16IS762 supports IrDA SIR with speeds up to 1.152 Mbit/s

Software reset

Transmitter and receiver can be enabled/disabled independent of each other

Receive and Transmit FIFO levels

Programmable special character detection

Fully programmable character formatting

5-bit, 6-bit, 7-bit or 8-bit character

Even, odd, or no parity

1, 1

, or 2 stop bit

Line break generation and detection

Internal Loopback mode

Sleep current less than 30

A at 3.3 V

Industrial and commercial temperature ranges

5 V tolerant inputs

Available in HVQFN32 and TSSOP28 packages

2.2 I

C-bus features

Noise filter on SCL/SDA inputs

400 kbit/s (maximum)

Compliant with I

C-bus Fast mode

Slave mode only

2.3 SPI features

SC16IS752 supports 4 Mbit/s maximum SPI clock speed

SC16IS762 supports 15 Mbit/s maximum SPI clock speed

Slave mode only

SPI Mode 0

Applications

Factory automation and process control

Portable and battery operated devices

Cellular data devices

Please note that IrDA SIR at 1.152 Mbit/s is not compatible with IrDA MIR at that speed. Please refer to application notes for usage
of IrDA SIR at 1.152 Mbit/s.

9397 750 14333

Product data sheet

Rev. 01 -- 4 January 2006

5 of 59

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Pinning information

6.1 Pinning

a. I

C-bus interface

b. SPI interface

Fig 2.

Pin configuration for TSSOP28

SC16IS752IPW
SC16IS762IPW

RTSA

CTSA

GPIO7/RIA

TXA

GPIO6/CDA

RXA

GPIO5/DTRA

RESET

GPIO4/DSRA

XTAL1

RXB

XTAL2

TXB

I2C

GPIO3/RIB

GPIO2/CDB

GPIO1/DTRB

n.c.

GPIO0/DSRB

SCL

RTSB

SDA

CTSB

002aab657

IRQ

SC16IS752IPW
SC16IS762IPW

RTSA

CTSA

GPIO7/RIA

TXA

GPIO6/CDA

RXA

GPIO5/DTRA

RESET

GPIO4/DSRA

XTAL1

RXB

XTAL2

TXB

SPI

GPIO3/RIB

GPIO2/CDB

GPIO1/DTRB

GPIO0/DSRB

SCLK

RTSB

CTSB

002aab599

IRQ

a. I

C-bus interface

b. SPI interface

Fig 3.

Pin configuration for HVQFN32

002aab658

SC16IS752IBS
SC16IS762IBS

Transparent top view

GPIO0/DSRB

GPIO1/DTRB

I2C

GPIO2/CDB

GPIO3/RIB

XTAL2

XTAL1

TXB

RESET

RXB

RXA

GPIO4/DSRA

n.c.

SCL

SDA

IRQ

CTSB

RTSB

TXA

CTSA

RTSA

GPIO7/RIA

GPIO6/CDA

GPIO5/DTRA

terminal 1

index area

002aab208

SC16IS752IBS
SC16IS762IBS

Transparent top view

GPIO0/DSRB

GPIO1/DTRB

SPI

GPIO2/CDB

GPIO3/RIB

XTAL2

XTAL1

TXB

RESET

RXB

RXA

GPIO4/DSRA

SCLK

IRQ

CTSB

RTSB

TXA

CTSA

RTSA

GPIO7/RIA

GPIO6/CDA

GPIO5/DTRA

terminal 1

index area

9397 750 14333

Product data sheet

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6 of 59

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

6.2 Pin description

Table 2:

Pin description

Symbol

Pin

Type

Description

TSSOP28

HVQFN32

CS/A0

SPI chip select or I

C-bus device address select A0. If SPI configuration

is selected by I2C/SPI pin, this pin is the SPI chip select pin
(Schmitt-trigger active LOW). If I

C-bus configuration is selected by

I2C/SPI pin, this pin along with A1 pin allows user to change the device's
base address.

To select the device address, please refer to

Table 32

CTSA

UART clear to send (active LOW). A logic 0 (LOW) on the CTSA pin
indicates the modem or data set is ready to accept transmit data from the
SC16IS752/SC16IS762. Status can be tested by reading MSR[4]. This
pin only affects the transmit and receive operations when Auto-CTS
function is enabled via the Enhanced Features Register EFR[7] for
hardware flow control operation.

CTSB

UART clear to send (active LOW), channel B. A logic 0 on the CTSB pin
indicates the modem or data set is ready to accept transmit data from the
SC16IS752/SC16IS762. Status can be tested by reading MSR[4]. This
pin only affects the transmit and receive operations when Auto-CTS
function is enabled via the Enhanced Features Register EFR[7] for
hardware flow control operation.

I2C/SPI

C-bus or SPI interface select. I

C-bus interface is selected if this pin is

at logic HIGH. SPI interface is selected if this pin is at logic LOW.

IRQ

Interrupt (open-drain, active LOW). Interrupt is enabled when interrupt
sources are enabled in the Interrupt Enable Register (IER). Interrupt
conditions include: change of state of the input pins, receiver errors,
available receiver buffer data, available transmit buffer space, or when a
modem status flag is detected. An external resistor (1 k

for 3.3 V,

1.5 k

for 2.5 V) must be connected between this pin and V

SI/A1

SPI data input pin or I

C-bus device address select A1. If SPI

configuration is selected by I2C/SPI pin, this is the SPI data input pin. If
I

C-bus configuration is selected by I2C/SPI pin, this pin along with the

A0 pin allows user to change the slave base address. To select the
device address, please refer to

Table 32

SPI data output pin. If SPI configuration is selected by I2C/SPI pin, this is
a 3-stateable output pin. If I

C-bus configuration is selected by the

I2C/SPI pin, this pin is undefined and must be left as no connect.

SCL/SCLK

C-bus or SPI input clock.

SDA

I/O

C-bus data input/output, open-drain if I

C-bus configuration is selected

by I2C/SPI pin. If SPI configuration is selected, this is not used and must
be connected to V

GPIO0/DSRB

I/O

Programmable I/O pin or modem DSRB

[1]

GPIO1/DTRB

I/O

Programmable I/O pin or modem DTRB

[1]

GPIO2/CDB

I/O

Programmable I/O pin or modem CDB

[1]

GPIO3/RIB

I/O

Programmable I/O pin or modem RIB

[1]

GPIO4/DSRA

I/O

Programmable I/O pin or modem DSRA

[2]

GPIO5/DTRA

I/O

Programmable I/O pin or modem DTRA

[2]

GPIO6/CDA

I/O

Programmable I/O pin or modem CDA

[2]

GPIO7/RIA

I/O

Programmable I/O pin or modem RIA

[2]

9397 750 14333

Product data sheet

Rev. 01 -- 4 January 2006

7 of 59

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

[1]

Selectable with IOControl register bit 2.

[2]

Selectable with IOControl register bit 1.

[3]

See

Section 7.4 "Hardware Reset, Power-On Reset (POR) and Software Reset"

[4]

XTAL2 should be left open when XTAL1 is driven by an external clock.

RESET

Hardware reset (active LOW)

[3]

RTSA

UART request to send (active LOW), channel A. A logic 0 on the RTSA
pin indicates the transmitter has data ready and waiting to send. Writing
a logic 1 in the Modem Control Register MCR[1] will set this pin to a
logic 0, indicating data is available. After a reset this pin is set to a logic 1.
This pin only affects the transmit and receive operations when Auto-RTS
function is enabled via the Enhanced Features Register (EFR[6]) for
hardware flow control operation.

RTSB

UART request to send (active LOW), channel B. A logic 0 on the RTSB
pin indicates the transmitter has data ready and waiting to send. Writing
a logic 1 in the Modem Control Register MCR[1] will set this pin to a
logic 0, indicating data is available. After a reset this pin is set to a logic 1.
This pin only affects the transmit and receive operations when Auto-RTS
function is enabled via the Enhanced Features Register (EFR[6]) for
hardware flow control operation.

RXA

Channel A receiver input. During the local Loopback mode, the RXA
input pin is disabled and TXA data is connected to the UART RXA input
internally.

RXB

Channel B receiver input. During the local Loopback mode, the RXB
input pin is disabled and TXB data is connected to the UART RXB input
internally.

TXA

Channel A transmitter output. During the local Loopback mode, the TXA
output pin is disabled and TXA data is internally connected to the UART
RXA input.

TXB

Channel B transmitter output. During the local Loopback mode, the TXB
output pin is disabled and TXB data is internally connected to the UART
RXB input.

5, 13, 28

Power supply

12, 21, 29

Ground

center pad -

The center pad on the back side of the HVQFN32 package is metallic
and should be connected to ground on the printed-circuit board.

XTAL1

Crystal input or external clock input. A crystal can be connected between
XTAL1 and XTAL2 to form an internal oscillator circuit (see

Figure 11

Alternatively, an external clock can be connected to this pin.

XTAL2

Crystal output. (See also XTAL1.) XTAL2 is used as a crystal oscillator
output

[4]

Table 2:

Pin description

...continued

Symbol

Pin

Type

Description

TSSOP28

HVQFN32

9397 750 14333

Product data sheet

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8 of 59

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Functional description

The UART will perform serial-to-I

C-bus conversion on data characters received from

peripheral devices or modems, and I

C-bus-to-serial conversion on data characters

transmitted by the host. The complete status the SC16IS752/SC16IS762 UART can be
read at any time during functional operation by the host.

The SC16IS752/SC16IS762 can be placed in an alternate mode (FIFO mode) relieving
the host of excessive software overhead by buffering received/transmitted characters.
Both the receiver and transmitter FIFOs can store up to 64 characters (including three
additional bits of error status per character for the receiver FIFO) and have selectable or
programmable trigger levels.

The SC16IS752/SC16IS762 has selectable hardware flow control and software flow
control. Hardware flow control significantly reduces software overhead and increases
system efficiency by automatically controlling serial data flow using the RTS output and
CTS input signals. Software flow control automatically controls data flow by using
programmable Xon/Xoff characters.

The UART includes a programmable baud rate generator that can divide the timing
reference clock input by a divisor between 1 and (2

1).

7.1 Trigger levels

The SC16IS752/SC16IS762 provides independently selectable and programmable trigger
levels for both receiver and transmitter interrupt generation. After reset, both transmitter
and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of
one character. The selectable trigger levels are available via the FIFO Control Register
(FCR). The programmable trigger levels are available via the Trigger Level Register (TLR).
If TLR bits are cleared, then selectable trigger level in FCR is used. If TLR bits are not
cleared, then programmable trigger level in TLR is used.

7.2 Hardware flow control

Hardware flow control is comprised of Auto-CTS and Auto-RTS (see

Figure 4

). Auto-CTS

and Auto-RTS can be enabled/disabled independently by programming EFR[7:6].

With Auto-CTS, CTS must be active before the UART can transmit data.

Auto-RTS only activates the RTS output when there is enough room in the FIFO to receive
data and de-activates the RTS output when the RX FIFO is sufficiently full. The halt and
resume trigger levels in the TCR determine the levels at which RTS is
activated/deactivated. If TCR bits are cleared, then selectable trigger levels in FCR are
used in place of TCR.

If both Auto-CTS and Auto-RTS are enabled, when RTS is connected to CTS, data
transmission does not occur unless the receiver FIFO has empty space. Thus, overrun
errors are eliminated during hardware flow control. If not enabled, overrun errors occur if
the transmit data rate exceeds the receive FIFO servicing latency.

9397 750 14333

Product data sheet

Rev. 01 -- 4 January 2006

9 of 59

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.2.1 Auto-RTS

Figure 5

shows RTS functional timing. The receiver FIFO trigger levels used in Auto-RTS

are stored in the TCR. RTS is active if the RX FIFO level is below the halt trigger level in
TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is deasserted. The
sending device (for example, another UART) may send an additional character after the
trigger level is reached (assuming the sending UART has another character to send)
because it may not recognize the deassertion of RTS until it has begun sending the
additional character. RTS is automatically reasserted once the receiver FIFO reaches the
resume trigger level programmed via TCR[7:4]. This reassertion allows the sending
device to resume transmission.

Fig 4.

Autoflow control (Auto-RTS and Auto-CTS) example

FIFO

FLOW

CONTROL

FIFO

PARALLEL

TO SERIAL

FIFO

UART 1

UART 2

RTS

CTS

RTS

002aab656

SERIAL TO

PARALLEL

SERIAL TO

PARALLEL

FLOW

CONTROL

FLOW

CONTROL

FLOW

CONTROL

PARALLEL

TO SERIAL

(1) N = receiver FIFO trigger level.

(2) The two blocks in dashed lines cover the case where an additional character is sent, as described in

Section 7.2.1

Fig 5.

RTS functional timing

start

character

start

character

N + 1

start

stop

RTS

receive

FIFO

read

N + 1

002aab040

9397 750 14333

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Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.2.2 Auto-CTS

Figure 6

shows CTS functional timing. The transmitter circuitry checks CTS before

sending the next data character. When CTS is active, the transmitter sends the next
character. To stop the transmitter from sending the following character, CTS must be
deasserted before the middle of the last stop bit that is currently being sent. The
Auto-CTS function reduces interrupts to the host system. When flow control is enabled,
CTS level changes do not trigger host interrupts because the device automatically
controls its own transmitter. Without Auto-CTS, the transmitter sends any data present in
the transmit FIFO and a receiver overrun error may result.

7.3 Software flow control

Software flow control is enabled through the Enhanced Features Register and the Modem
Control Register. Different combinations of software flow control can be enabled by setting
different combinations of EFR[3:0].

Table 3

shows software flow control options.

(1) When CTS is LOW, the transmitter keeps sending serial data out.

(2) When CTS goes HIGH before the middle of the last stop bit of the current character, the transmitter finishes sending the

current character, but it does not send the next character.

(3) When CTS goes from HIGH to LOW, the transmitter begins sending data again.

Fig 6.

CTS functional timing

start

bit 0 to bit 7

stop

CTS

002aab041

start

stop

bit 0 to bit 7

Table 3:

Software flow control options (EFR[3:0])

EFR[3]

EFR[2]

EFR[1]

EFR[0]

TX, RX software flow control

no transmit flow control

transmit Xon1, Xoff1

transmit Xon2, Xoff2

transmit Xon1 and Xon2, Xoff1 and Xoff2

no receive flow control

receiver compares Xon1, Xoff1

receiver compares Xon2, Xoff2

transmit Xon1, Xoff1

receiver compares Xon1 or Xon2, Xoff1 or Xoff2

transmit Xon2, Xoff2

receiver compares Xon1 or Xon2, Xoff1 or Xoff2

transmit Xon1 and Xon2, Xoff1 and Xoff2

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

no transmit flow control

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

9397 750 14333

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Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

There are two other enhanced features relating to software flow control:

Xon Any function (MCR[5]): Receiving any character will resume operation after
recognizing the Xoff character. It is possible that an Xon1 character is recognized as
an Xon Any character, which could cause an Xon2 character to be written to the
RX FIFO.

Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the
special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The
Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the
RX FIFO.

7.3.1 Receive flow control

When software flow control operation is enabled, the SC16IS752/SC16IS762 will
compare incoming data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1
and Xoff2 must be received sequentially). When the correct Xoff characters are received,
transmission is halted after completing transmission of the current character. Xoff
detection also sets IIR[4] (if enabled via IER[5]) and causes IRQ to go LOW.

To resume transmission, an Xon1/Xon2 character must be received (in certain cases
Xon1 and Xon2 must be received sequentially). When the correct Xon characters are
received, IIR[4] is cleared, and the Xoff interrupt disappears.

7.3.2 Transmit flow control

Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the halt trigger level
programmed in TCR[3:0], or the selectable trigger level in FCR[7:6].

Xon1/Xon2 character is transmitted when the RX FIFO reaches the resume trigger level
programmed in TCR[7:4], or falls below the lower selectable trigger level in FCR[7:6].

The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an
ordinary character from the FIFO. This means that even if the word length is set to be 5, 6,
or 7 bits, then the 5, 6, or 7 least significant bits of Xoff1/Xoff2, Xon1/Xon2 will be
transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but
this functionality is included to maintain compatibility with earlier designs.)

It is assumed that software flow control and hardware flow control will never be enabled
simultaneously.

Figure 7

shows an example of software flow control.

9397 750 14333

Product data sheet

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Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.4 Hardware Reset, Power-On Reset (POR) and Software Reset

These three reset methods are identical and will reset the internal registers as indicated in

Table 4

summarizes the state of register after reset.

[1]

Registers DLL, DLH, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the top-level reset signal
RESET, POR and Software Reset, that is, they hold their initialization values during reset.

Table 5

summarizes the state of output signals after reset.

Table 4:

Register reset

Register

Reset state

Interrupt Enable Register

all bits cleared

Interrupt Identification Register

bit 0 is set; all other bits cleared

FIFO Control Register

all bits cleared

Line Control Register

reset to 0001 1101 (0x1D)

Modem Control Register

all bits cleared

Line Status Register

bit 5 and bit 6 set; all other bits cleared

Modem Status Register

bits 3:0 cleared; bits 7:4 input signals

Enhanced Features Register

all bits cleared

Receive Holding Register

pointer logic cleared

Transmit Holding Register

pointer logic cleared

Transmission Control Register

all bits cleared

Trigger Level Register

all bits cleared

Transmit FIFO level

reset to 0100 0000 (0x40)

Receive FIFO level

all bits cleared

I/O direction

all bits cleared

I/O interrupt enable

all bits cleared

I/O control

all bits cleared

Extra Features Control Register

all bits cleared

Table 5:

Output signals after reset

Signal

Reset state

HIGH

RTS

HIGH

I/Os

inputs

IRQ

HIGH by external pull-up

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Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.5 Interrupts

The SC16IS752/SC16IS762 has interrupt generation and prioritization (seven prioritized
levels of interrupts) capability. The interrupt enable registers (IER and IOIntEna) enable
each of the seven types of interrupts and the IRQ signal in response to an interrupt
generation. When an interrupt is generated, the IIR indicates that an interrupt is pending
and provides the type of interrupt through IIR[5:0].

Table 6

summarizes the interrupt

control functions.

It is important to note that for the framing error, parity error, and break conditions, LSR[7]
generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO,
and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always
represent the error status for the received character at the top of the RX FIFO. Reading
the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of
the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.

For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt
is cleared by an Xon flow character detection. If a special character detection caused the
interrupt, the interrupt is cleared by a read of the IIR.

Table 6:

Summary of interrupt control functions

IIR[5:0]

Priority
level

Interrupt type

Interrupt source

000001

none

000110

receiver line status

OE, FE, PE, or BI errors occur in characters in the
RX FIFO

001100

RX time-out

stale data in RX FIFO

000100

RHR interrupt

receive data ready (FIFO disable) or
RX FIFO above trigger level (FIFO enable)

000010

THR interrupt

transmit FIFO empty (FIFO disable) or
TX FIFO passes above trigger level (FIFO enable)

000000

modem status

change of state of modem input pins

001110

I/O pins

input pins change of state

010000

Xoff interrupt

receive Xoff character(s)/special character

100000

CTS, RTS

RTS pin or CTS pin change state from active (LOW)
to inactive (HIGH)

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Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.6 Sleep mode

Sleep mode is an enhanced feature of the SC16IS752/SC16IS762 UART. It is enabled
when EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is
entered when:

The serial data input line, RX, is idle (see

Section 7.7 "Break and time-out

conditions"

The TX FIFO and TX shift register are empty.

There are no interrupts pending except THR.

Remark: Sleep mode will not be entered if there is data in the RX FIFO.

In Sleep mode, the clock to the UART is stopped. Since most registers are clocked using
these clocks, the power consumption is greatly reduced. The UART will wake up when any
change is detected on the RX line, when there is any change in the state of the modem
input pins, or if data is written to the TX FIFO.

Remark: Writing to the divisor latches DLL and DLH to set the baud clock must not be
done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4]
before writing to DLL or DLH.

7.7 Break and time-out conditions

When the UART receives a number of characters and these data are not enough to set off
the receive interrupt (because they do not reach the receive trigger level), the UART will
generate a time-out interrupt instead, 4 character times after the last character is
received. The time-out counter will be reset at the center of each stop bit received or each
time the receive FIFO is read.

A break condition is detected when the RX pin is pulled LOW for a duration longer than
the time it takes to send a complete character plus start, stop and parity bits. A break
condition can be sent by setting LCR[6], when this happens the TX pin will be pulled LOW
until LSR[6] is cleared by the software.

7.8 Programmable baud rate generator

The SC16IS752/SC16IS762 UART contains a programmable baud rate generator that
takes any clock input and divides it by a divisor in the range between 1 and (2

1). An

additional divide-by-4 prescaler is also available and can be selected by MCR[7], as
shown in

Figure 10

. The output frequency of the baud rate generator is 16

the baud rate.

The formula for the divisor is:

(1)

where:

prescaler = 1, when MCR[7] is set to `0' after reset (divide-by-1 clock selected)

prescaler = 4, when MCR[7] is set to `1' after reset (divide-by-4 clock selected).

Remark: The default value of prescaler after reset is divide-by-1.

divisor

XTAL1 crystal input frequency

prescaler

---------------------------------------------------------------------------

desired baud rate

---------------------------------------------------------------------------------

9397 750 14333

Product data sheet

Rev. 01 -- 4 January 2006

17 of 59

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Figure 10

shows the internal prescaler and baud rate generator circuitry.

DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the
least significant and most significant byte of the baud rate divisor. If DLL and DLH are both
zero, the UART is effectively disabled, as no baud clock will be generated.

Remark: The programmable baud rate generator is provided to select both the transmit
and receive clock rates.

Table 7

and

Table 8

show the baud rate and divisor correlation for crystal with frequency

1.8432 MHz and 3.072 MHz, respectively.

Figure 11

shows the crystal clock circuit reference.

Fig 10. Prescaler and baud rate generator block diagram

Table 7:

Baud rates using a 1.8432 MHz crystal

Desired baud rate
(bit/s)

Divisor used to generate
16

clock

Percent error difference
between desired and actual

2304

1536

110

1047

0.026

134.5

857

0.058

150

768

300

384

600

192

1200

1800

2000

0.69

2400

3600

4800

7200

9600

19200

38400

56000

2.86

BAUD RATE

GENERATOR

LOGIC

MCR[7] = 1

MCR[7] = 0

PRESCALER

LOGIC

(DIVIDE-BY-1)

INTERNAL

OSCILLATOR

LOGIC

002aaa233

XTAL1

XTAL2

input clock

PRESCALER

LOGIC

(DIVIDE-BY-4)

reference
clock

internal
baud rate
clock for
transmitter
and receiver

9397 750 14333

Product data sheet

Rev. 01 -- 4 January 2006

19 of 59

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Register descriptions

The programming combinations for register selection are shown in

Table 9

[1]

MCR[7] can only be modified when EFR[4] is set.

[2]

Accessible only when ERF[4] = 1 and MCR[2] = 1, that is, EFR[4] and MCR[2] are read/write enables.

[3]

Accessible only when LCR[7] is logic 1.

[4]

Accessible only when LCR is set to 1011 1111b (0xBF).

Table 9:

Register map - read/write properties

Register name Read mode

Write mode

RHR/THR

Receive Holding Register (RHR)

Transmit Holding Register (THR)

IER

Interrupt Enable Register (IER)

Interrupt Enable Register

IIR/FCR

Interrupt Identification Register (IIR)

FIFO Control Register (FCR)

LCR

Line Control Register (LCR)

Line Control Register

MCR

Modem Control Register (MCR)

[1]

Modem Control Register

[1]

LSR

Line Status Register (LSR)

n/a

MSR

Modem Status Register (MSR)

n/a

SPR

Scratchpad Register (SPR)

Scratchpad Register

TCR

Transmission Control Register (TCR)

[2]

Transmission Control Register

[2]

TLR

Trigger Level Register (TLR)

[2]

Trigger Level Register

[2]

TXLVL

Transmit FIFO Level register

n/a

RXLVL

Receive FIFO Level register

n/a

IODir

I/O pin Direction register

IOState

I/O pins State register

n/a

IOIntEna

I/O Interrupt Enable register

Interrupt Enable register

IOControl

I/O pins Control register

EFCR

Extra Features Control Register

DLL

Divisor Latch LSB (DLL)

[3]

Divisor Latch LSB

[3]

DLH

Divisor Latch MSB (DLH)

[3]

Divisor Latch MSB

[3]

EFR

Enhanced Features Register (EFR)

[4]

Enhanced Features Register

[4]

XON1

Xon1 word

[4]

Xon1 word

[4]

XON2

Xon2 word

[4]

Xon2 word

[4]

XOFF1

Xoff1 word

[4]

Xoff1 word

[4]

XOFF2

Xoff2 word

[4]

Xoff2 word

[4]

9397 750 14333

Product data sheet

Rev. 01 -- 4 January 2006

20 of 59

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Table 10:

SC16IS752/SC16IS762 internal registers

Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R/W

General register set

[1]

0x00

RHR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x00

THR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x01

IER

CTS
interrupt
enable

[2]

RTS
interrupt
enable

[2]

Xoff

[2]

Sleep
mode

[2]

modem
status
interrupt

receive line
status
interrupt

THR
empty
interrupt

RX data
available
interrupt

R/W

0x02

FCR

RX
trigger
level
(MSB)

RX
trigger
level
(LSB)

TX
trigger
level
(MSB)

[2]

TX trigger
level
(LSB)

[2]

reserved

[3]

TX FIFO
reset

[4]

RX FIFO
reset

[4]

FIFO
enable

0x02

IIR

[5]

FIFO
enable

interrupt
priority
bit 4

[2]

interrupt
priority
bit 3

[2]

interrupt
priority
bit 2

interrupt
priority
bit 1

interrupt
priority
bit 0

interrupt
status

0x03

LCR

divisor
latch
enable

set break

set parity

even
parity

parity
enable

stop bit

word
length
bit 1

word
length
bit 0

R/W

0x04

MCR

clock
divisor

[2]

IrDA
mode
enable

[2]

Xon
Any

[2]

loopback
enable

reserved

[3]

TCR and
TLR
enable

[2]

RTS

DTR/
(IO5)

R/W

0x05

LSR

FIFO
data
error

THR and
TSR
empty

THR
empty

break
interrupt

framing
error

parity error overrun

error

data in
receiver

0x06

MSR

DSR

CTS

DSR

CTS

0x07

SPR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

0x06

TCR

[6]

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

0x07

TLR

[6]

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

0x08

TXLVL

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x09

RXLVL

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x0A

IODir

[7]

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

0x0B

IOState

[7]

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

0x0C

IOIntEna

[7]

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

0x0D

reserved

[3]

reserved

[3]

reserved

[3]

reserved

[3]

reserved

[3]

reserved

[3]

reserved

[3]

reserved

[3]

reserved

[3]

0x0E

IOControl

[7]

reserved

[3]

reserved

[3]

reserved

[3]

reserved

[3]

UART
software
reset

I/O[3:0] or
RIB, CDB,
DTRB,
DSRB

I/O[7:4] or
RIA, CDA,
DTRA,
DSRA

latch

R/W

0x0F

EFCR

IrDA
mode
(slow/
fast)

[8]

reserved

[3]

auto
RS-485
RTS
output
inversion

auto
RS-485
RTS
direction
control

reserved

[3]

transmitter
disable

receiver
disable

9-bit
mode
enable

R/W

Special register set

[9]

0x00

DLL

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

0x01

DLH

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

9397 750 14333

Product data sheet

Rev. 01 -- 4 January 2006

21 of 59

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

[1]

These registers are accessible only when LCR[7] = 0.

[2]

This bit can only be modified if register bit EFR[4] is enabled.

[3]

These bits are reserved and should be set to 0.

[4]

After Receive FIFO or Transmit FIFO reset (through FCR [1:0]), the user must wait at least 2

clk

of XTAL1 before reading or writing

data to RHR and THR respectively.

[5]

Burst reads on the serial interface (that is, reading multiple elements on the I

C-bus without a STOP or repeated START condition, or

reading multiple elements on the SPI bus without de-asserting the CS pin), should not be performed on the IIR register.

[6]

These registers are accessible only when EFR[4] = 1, and MCR[2] = 1.

[7]

These registers apply to both channels.

[8]

IrDA mode slow/fast for SC16IS762, slow only for SC16IS752.

[9]

The Special Register set is accessible only when LCR[7] = 1 and not 0xBF.

[10] Enhanced Features Registers are only accessible when LCR = 0xBF.

8.1 Receive Holding Register (RHR)

The receiver section consists of the Receive Holding Register (RHR) and the Receive
Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data
from the RX terminal. The data is converted to parallel data and moved to the RHR. The
receiver section is controlled by the Line Control Register. If the FIFO is disabled, location
zero of the FIFO is used to store the characters.

8.2 Transmit Holding Register (THR)

The transmitter section consists of the Transmit Holding Register (THR) and the Transmit
Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and
shifts it into the TSR, where it is converted to serial data and moved out on the TX
terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are
lost if overflow occurs.

Enhanced register set

[10]

0x02

EFR

Auto
CTS

Auto RTS special

character
detect

enable
enhanced
functions

software
flow
control
bit 3

software
flow control
bit 2

software
flow
control
bit 1

software
flow
control
bit 0

R/W

0x04

XON1

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

0x05

XON2

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

0x06

XOFF1

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

0x07

XOFF2

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

Table 10:

SC16IS752/SC16IS762 internal registers

...continued

Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R/W

9397 750 14333

Product data sheet

Rev. 01 -- 4 January 2006

22 of 59

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.3 FIFO Control Register (FCR)

This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting
transmitter and receiver trigger levels.

Table 11

shows FIFO Control Register bit settings.

[1]

FIFO reset logic requires at least two XTAL1 clocks, therefore, they cannot be reset without the presence of
the XTAL1 clock.

Table 11:

FIFO Control Register bits description

Bit

Symbol

Description

7:6

FCR[7] (MSB),
FCR[6] (LSB)

RX trigger. Sets the trigger level for the RX FIFO.

00 = 8 characters

01 = 16 characters

10 = 56 characters

11 = 60 characters

5:4

FCR[5] (MSB),
FCR[4] (LSB)

TX trigger. Sets the trigger level for the TX FIFO.

00 = 8 spaces

01 = 16 spaces

10 = 32 spaces

11 = 56 spaces

FCR[5:4] can only be modified and enabled when EFR[4] is set. This
is because the transmit trigger level is regarded as an enhanced
function.

FCR[3]

reserved

FCR[2]

[1]

Reset TX FIFO.

logic 0 = no FIFO transmit reset (normal default condition)

logic 1 = clears the contents of the transmit FIFO and resets the
FIFO level logic (the Transmit Shift Register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO.

FCR[1]

[1]

Reset RX FIFO

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the
FIFO level logic (the Receive Shift Register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO.

FCR[0]

FIFO enable

logic 0 = disable the transmit and receive FIFO (normal default
condition)

logic 1 = enable the transmit and receive FIFO

9397 750 14333

Product data sheet

Rev. 01 -- 4 January 2006

23 of 59

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.4 Line Control Register (LCR)

This register controls the data communication format. The word length, number of stop
bits, and parity type are selected by writing the appropriate bits to the LCR.

Table 12

shows the Line Control Register bit settings.

Table 12:

Line Control Register bits description

Bit

Symbol

Description

LCR[7]

Divisor latch enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch enabled

LCR[6]

Break control bit. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0 state).
This condition exists until disabled by setting LCR[6] to a logic 0.

logic 0 = no TX break condition (normal default condition)

logic 1 = forces the transmitter output (TX) to a logic 0 to alert the
communication terminal to a line break condition

LCR[5]

Set parity. LCR[5] selects the forced parity format (if LCR[3] = 1).

logic 0 = parity is not forced (normal default condition).

LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1
for the transmit and receive data.

LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0
for the transmit and receive data.

LCR[4]

Parity type select.

logic 0 = odd parity is generated (if LCR[3] = 1)

logic 1 = even parity is generated (if LCR[3] = 1)

LCR[3]

Parity enable.

logic 0 = no parity (normal default condition)

logic 1 = a parity bit is generated during transmission and the receiver
checks for received parity

LCR[2]

Number of Stop bits. Specifies the number of stop bits.

0 to 1 stop bit (word length = 5, 6, 7, 8)

1 to 1.5 stop bits (word length = 5)

1 = 2 stop bits (word length = 6, 7, 8)

1:0

LCR[1:0]

Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see

Table 15

9397 750 14333

Product data sheet

Rev. 01 -- 4 January 2006

25 of 59

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.5 Line Status Register (LSR)

Table 16

shows the Line Status Register bit settings.

When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the
top of the RX FIFO (next character to be read). Therefore, errors in a character are
identified by reading the LSR and then reading the RHR.

LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when
there are no more errors remaining in the FIFO.

Table 16:

Line Status Register bits description

Bit

Symbol

Description

LSR[7]

FIFO data error.

logic 0 = no error (normal default condition)

logic 1 = at least one parity error, framing error, or break indication is in
the receiver FIFO. This bit is cleared when no more errors are present
in the FIFO.

LSR[6]

THR and TSR empty. This bit is the Transmit Empty indicator.

logic 0 = transmitter hold and shift registers are not empty

logic 1 = transmitter hold and shift registers are empty

LSR[5]

THR empty. This bit is the Transmit Holding Register Empty indicator.

logic 0 = Transmit Hold Register is not empty.

logic 1 = Transmit Hold Register is empty. The host can now load up to
64 characters of data into the THR if the TX FIFO is enabled.

LSR[4]

Break interrupt.

logic 0 = no break condition (normal default condition).

logic 1 = a break condition occurred and associated character is 00h
(RX was LOW for one character time frame)

LSR[3]

Framing error.

logic 0 = no framing error in data being read from RX FIFO (normal
default condition)

logic 1 = framing error occurred in data being read from RX FIFO
(received data did not have a valid stop bit)

LSR[2]

Parity error.

logic 0 = no parity error (normal default condition)

logic 1 = parity error in data being read from RX FIFO

LSR[1]

Overrun error.

logic 0 = no overrun error (normal default condition)

logic 1 = overrun error has occurred

LSR[0]

Data in receiver.

logic 0 = no data in receive FIFO (normal default condition)

logic 1 = at least one character in the RX FIFO

9397 750 14333

Product data sheet

Rev. 01 -- 4 January 2006

26 of 59

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.6 Modem Control Register (MCR)

The MCR controls the interface with the mode, data set, or peripheral device that is
emulating the modem.

Table 17

shows Modem Control Register bit settings.

[1]

MCR[7:5] and MCR[2] can only be modified when EFR[4] is set, that is, EFR[4] is a write enable.

Table 17:

Modem Control Register bits description

Bit

Symbol

Description

MCR[7]

[1]

Clock divisor.

logic 0 = divide-by-1 clock input

logic 1 = divide-by-4 clock input

MCR[6]

[1]

IrDA mode enable.

logic 0 = normal UART mode

logic 1 = IrDA mode

MCR[5]

[1]

Xon Any.

logic 0 = disable Xon Any function

logic 1 = enable Xon Any function

MCR[4]

Enable loopback.

logic 0 = normal operating mode

logic 1 = enable local Loopback mode (internal). In this mode the
MCR[1:0] signals are looped back into MSR[4:5] and the TX output is
looped back to the RX input internally.

MCR[3]

reserved

MCR[2]

TCR and TLR enable.

logic 0 = disable the TCR and TLR register

logic 1 = enable the TCR and TLR register

MCR[1]

RTS

logic 0 = force RTS output to inactive (HIGH)

logic 1 = force RTS output to active (LOW). In Loopback mode,
controls MSR[4]. If Auto-RTS is enabled, the RTS output is controlled
by hardware flow control.

MCR[0]

DTR. If GPIO5 or GPIO1 is selected as DTR modem pin through
IOControl register bit 1 or bit 2, the state of DTR pin can be controlled as
below. Writing to IOState bit 5 or bit 1 will not have any effect on the DTR
pin.

logic 0 = force DTR output to inactive (HIGH)

logic 1 = force DTR output to active (LOW)

9397 750 14333

Product data sheet

Rev. 01 -- 4 January 2006

27 of 59

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.7 Modem Status Register (MSR)

This 8-bit register provides information about the current state of the control lines from the
modem, data set, or peripheral device to the host. It also indicates when a control input
from the modem changes state.

Table 18

shows Modem Status Register bit settings per

channel.

Remark: The primary inputs RI, CD, CTS, DSR are all active LOW.

Table 18:

Modem Status Register bits description

Bit

Symbol

Description

MSR[7]

CD (active HIGH, logical 1). If GPIO6 or GPIO2 is selected as CD
modem pin through IOControl register bit 1 or bit 2, the state of CD pin
can be read from this bit. This bit is the complement of the CD input.
Reading IOState bit 6 or bit 2 does not reflect the true state of CD pin.

MSR[6]

RI (active HIGH, logical 1). If GPIO7 or GPIO3 is selected as RI modem
pin through IOControl register bit 1 or bit 2, the state of RI pin can be
read from this bit. This bit is the complement of the RI input. Reading
IOState bit 7 or bit 3 does not reflect the true state of RI pin.

MSR[5]

DSR (active HIGH, logical 1). If GPIO4 or GPIO0 is selected as DSR
modem pin through IOControl register bit 1 or bit 2, the state of DSR pin
can be read from this bit. This bit is the complement of the DSR input.
Reading IOState bit 4 or bit 0 does not reflect the true state of DSR pin.

MSR[4]

CTS (active HIGH, logical 1). This bit is the complement of the CTS
input.

MSR[3]

CD. Indicates that CD input has changed state. Cleared on a read.

MSR[2]

RI. Indicates that RI input has changed state from LOW to HIGH.

Cleared on a read.

MSR[1]

DSR. Indicates that DSR input has changed state. Cleared on a read.

MSR[0]

CTS. Indicates that CTS input has changed state. Cleared on a read.

9397 750 14333

Product data sheet

Rev. 01 -- 4 January 2006

28 of 59

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.8 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver
error, RHR interrupt, THR interrupt, Modem Status, Xoff received, or CTS/RTS change of
state from LOW to HIGH. The IRQ output signal is activated in response to interrupt
generation.

Table 19

shows Interrupt Enable Register bit settings.

[1]

IER[7:4] can only be modified if EFR[4] is set, that is, EFR[4] is a write enable. Re-enabling IER[1] will not
cause a new interrupt if the THR is below the threshold.

Table 19:

Interrupt Enable Register bits description

Bit

Symbol

Description

IER[7]

[1]

CTS interrupt enable.

logic 0 = disable the CTS interrupt (normal default condition)

logic 1 = enable the CTS interrupt

IER[6]

[1]

RTS interrupt enable.

logic 0 = disable the RTS interrupt (normal default condition)

logic 1 = enable the RTS interrupt

IER[5]

[1]

Xoff interrupt.

logic 0 = disable the Xoff interrupt (normal default condition)

logic 1 = enable the Xoff interrupt

IER[4

[1]

]

Sleep mode.

logic 0 = disable Sleep mode (normal default condition)

logic 1 = enable Sleep mode. See

Section 7.6 "Sleep mode"

for details.

IER[3]

Modem Status interrupt.

logic 0 = disable the Modem Status Register interrupt (normal default
condition)

logic 1 = enable the Modem Status Register interrupt

Remark: See IOControl register bit 1 or bit 2 (in

Table 30

) for the description

of how to program the pins as modem pins.

IER[2]

Receive Line Status interrupt.

logic 0 = disable the receiver line status interrupt (normal default condition)

logic 1 = enable the receiver line status interrupt

IER[1]

Transmit Holding Register interrupt.

logic 0 = disable the THR interrupt (normal default condition)

logic 1 = enable the THR interrupt

IER[0]

Receive Holding Register interrupt.

logic 0 = disable the RHR interrupt (normal default condition)

logic 1 = enable the RHR interrupt

9397 750 14333

Product data sheet

Rev. 01 -- 4 January 2006

29 of 59

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.9 Interrupt Identification Register (IIR)

The IIR is a read-only 8-bit register which provides the source of the interrupt in a
prioritized manner.

Table 20

shows Interrupt Identification Register bit settings.

[1]

Modem interrupt status must be read via MSR register and GPIO interrupt status must be read via IOState
register.

Table 20:

Interrupt Identification Register bits description

Bit

Symbol

Description

7:6

IIR[7:6]

Mirror the contents of FCR[0].

5:1

IIR[5:1]

5-bit encoded interrupt. See

Table 21

IIR[0]

Interrupt status.

logic 0 = an interrupt is pending

logic 1 = no interrupt is pending

Table 21:

Interrupt source

Priority
level

IIR[5]

IIR[4]

IIR[3]

IIR[2]

IIR[1]

IIR[0]

Source of the interrupt

Receive Line Status error

Receiver time-out interrupt

RHR interrupt

THR interrupt

modem interrupt

[1]

input pin change of state

[1]

received Xoff signal/special
character

CTS, RTS change of state
from active (LOW) to
inactive (HIGH)

9397 750 14333

Product data sheet

Rev. 01 -- 4 January 2006

30 of 59

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.10 Enhanced Features Register (EFR)

This 8-bit register enables or disables the enhanced features of the UART.

Table 22

shows

the Enhanced Features Register bit settings.

8.11 Division registers (DLL, DLH)

These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLH stores the most significant part of the divisor. DLL stores
the least significant part of the divisor.

Note that DLL and DLH can only be written to before Sleep mode is enabled (before
IER[4] is set).

Table 22:

Enhanced Features Register bits description

Bit

Symbol

Description

EFR[7]

CTS flow control enable.

logic 0 = CTS flow control is disabled (normal default condition)

logic 1 = CTS flow control is enabled. Transmission will stop when a
HIGH signal is detected on the CTS pin.

EFR[6]

RTS flow control enable.

logic 0 = RTS flow control is disabled (normal default condition)

logic 1 = RTS flow control is enabled. The RTS pin goes HIGH when
the receiver FIFO halt trigger level TCR[3:0] is reached, and goes
LOW when the receiver FIFO resume transmission trigger level
TCR[7:4] is reached.

EFR[5]

Special character detect.

logic 0 = special character detect disabled (normal default condition)

logic 1 = special character detect enabled. Received data is compared
with Xoff2 data. If a match occurs, the received data is transferred to
FIFO and IIR[4] is set to a logical 1 to indicate a special character has
been detected.

EFR[4]

Enhanced functions enable bit.

logic 0 = disables enhanced functions and writing to IER[7:4],
FCR[5:4], MCR[7:5].

logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and
MCR[7:5] so that they can be modified.

3:0

EFR[3:0]

Combinations of software flow control can be selected by programming
these bits. See

Table 3 "Software flow control options (EFR[3:0])"

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Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.12 Transmission Control Register (TCR)

This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission
during hardware/software flow control.

Table 23

shows Transmission Control Register bit

settings.

TCR trigger levels are available from 0 bytes to 60 characters with a granularity of four.

Remark: TCR can only be written to when EFR[4] = 1 and MCR[2] = 1. The programmer
must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware
check to make sure this condition is met. Also, the TCR must be programmed with this
condition before Auto-RTS or software flow control is enabled to avoid spurious operation
of the device.

8.13 Trigger Level Register (TLR)

This 8-bit register is used to store the transmit and received FIFO trigger levels used for
interrupt generation. Trigger levels from 4 to 60 can be programmed with a granularity
of four.

Table 24

shows Trigger Level Register bit settings.

Remark: TLR can only be written to when EFR[4] = 1 and MCR[2] = 1. If TLR[3:0] or
TLR[7:4] are logical 0, the selectable trigger levels via the FIFO Control Register (FCR)
are used for the transmit and receive FIFO trigger levels. Trigger levels from 4 characters
to 60 characters are available with a granularity of four. The TLR should be programmed
for

, where N is the desired trigger level.

When the trigger level setting in TLR is zero, the SC16IS752/SC16IS762 uses the trigger
level setting defined in FCR. If TLR has non-zero trigger level value, the trigger level
defined in FCR is discarded. This applies to both transmit FIFO and receive FIFO trigger
level setting.

When TLR is used for RX trigger level control, FCR[7:6] should be left at the default state
`00'.

8.14 Transmitter FIFO Level register (TXLVL)

This register is a read-only register. It reports the number of spaces available in the
transmit FIFO.

Table 23:

Transmission Control Register bits description

Bit

Symbol

Description

7:4

TCR[7:4]

RX FIFO trigger level to resume

3:0

TCR[3:0]

RX FIFO trigger level to halt transmission

Table 24:

Trigger Level Register bits description

Bit

Symbol

Description

7:4

TLR[7:4]

RX FIFO trigger levels (4 to 60), number of characters available

3:0

TLR[3:0]

TX FIFO trigger levels (4 to 60), number of spaces available

Table 25:

Transmitter FIFO Level register bits description

Bit

Symbol

Description

not used; set to zeros

6:0

TXLVL[6:0]

number of spaces available in TXFIFO, from 0 (0x00) to 64 (0x40)

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Philips Semiconductors

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Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.15 Receiver FIFO Level register (RXLVL)

This register is a read-only register, it reports the fill level of the receive FIFO, that is, the
number of characters in the RXFIFO.

8.16 Programmable I/O pins Direction register (IODir)

This register is used to program the I/O pins direction. Bit 0 to bit 7 controls GPIO0 to
GPIO7.

8.17 Programmable I/O pins State register (IOState)

When `read', this register returns the actual state of all I/O pins. When `write', each
register bit will be transferred to the corresponding I/O pin programmed as output.

8.18 I/O Interrupt Enable register (IOIntEna)

This register enables the interrupt due to a change in the I/O configured as inputs. If
GPIO[7:4] or GPIO[3:0] are programmed as modem pins, their interrupt generation must
be enabled via IER[3]. In this case, IOIntEna will have no effect on GPIO[7:4] or
GPIO[3:0].

Table 26:

Receiver FIFO Level register bits description

Bit

Symbol

Description

not used; set to zeros

6:0

RXLVL[6:0]

number of characters stored in RXFIFO, from 0 (0x00) to 64 (0x40)

Table 27:

IODir register bits description

Bit

Symbol

Description

7:0

IODir

Set GPIO pins [7:0] to input or output.

0 = input

1 = output

Table 28:

IOState register bits description

Bit

Symbol

Description

7:0

IOState

Write this register: set the logic level on the output pins

0 = set output pin to zero

1 = set output pin to one

Read this register: return states of all pins

Table 29:

IOIntEna register bits description

Bit

Symbol

Description

7:0

IOIntEna

Input interrupt enable.

0 = a change in the input pin will not generate an interrupt

1 = a change in the input will generate an interrupt

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Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.19 I/O Control register (IOControl)

Remark: As I/O pins, the direction, state, and interrupt enable of GPIO are controlled by
the following registers: IODir, IOState, IOIntEna, and IOControl. The state of CD, RI, DSR
pins will not be reflected in MSR[7:5] or MSR[3:1], and any change of state on these three
pins will not trigger a modem status interrupt (even if enabled via IER[3]), and the state of
the DTR pin cannot be controlled by MCR[0].

As modem CD, RI, DSR pins, the status at the input of these three pins can be read from
MSR[7:5] and MSR[3:1], and the state of the DTR pin can be controlled by MCR[0]. Also,
if modem status interrupt bit is enabled, IER[3], a change of state on RI, CD, DSR pins will
trigger a modem interrupt. The IODir, IOState, and IOIntEna registers will not have any
effect on these three pins.

Table 30:

IOControl register bits description

Bit

Symbol

Description

7:4

reserved

These bits are reserved for future use.

SRESET

Software Reset. A write to this bit will reset the device. Once the
device is reset this bit is automatically set to `0'.

GPIO[3:0] or
RIB, CDB,
DTRB, DSRB

This bit programs GPIO[3:0] as I/O pins or as modem's pins.

0 = I/O pins

1 = GPIO[3:0] emulate RIB, CDB, DTRB, DSRB

GPIO[7:4] or
RIA, CDA,
DTRA, DSRA

This bit programs GPIO[7:4] as I/O pins or as modem's pins.

0 = I/O pins

1 = GPIO[7:4] emulate RIA, CDA, DTRA, DSRA

IOLATCH

Enable/disable inputs latching.

0 = input value are not latched. A change in any input generates an
interrupt. A read of the input register clears the interrupt. If the input
goes back to its initial logic state before the input register is read,
then the interrupt is cleared.

1 = input values are latched. A change in the input generates an
interrupt and the input logic value is loaded in the bit of the
corresponding input state register (IOState). A read of the IOState
register clears the interrupt. If the input pin goes back to its initial
logic state before the interrupt register is read, then the interrupt is
not cleared and the corresponding bit of the IOState register keeps
the logic value that initiates the interrupt.

9397 750 14333

Product data sheet

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Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.20 Extra Features Control Register (EFCR)

[1]

For SC16IS762 only.

RS-485 features

9.1 Auto RS-485 RTS control

Normally the RTS pin is controlled by MCR bit 1, or if hardware flow control is enabled, the
logic state of the RTS pin is controlled by the hardware flow control circuitry. EFCR
register bit 4 will take the precedence over the other two modes; once this bit is set, the
transmitter will control the state of the RTS pin. The transmitter automatically asserts the
RTS pin (logic 0) once the host writes data to the transmit FIFO, and deasserts RTS pin
(logic 1) once the last bit of the data has been transmitted.

To use the auto RS-485 RTS mode the software would have to disable the hardware flow
control function.

Table 31:

Extra Features Control Register bits description

Bit

Symbol

Description

IRDA MODE

IrDA mode.

0 = IrDA SIR,

pulse ratio, data rate up to 115.2 kbit/s

1 = IrDA SIR,

pulse ratio, data rate up to 1.152 Mbit/s

[1]

reserved

RTSINVER

Invert RTS signal in RS-485 mode.

0: RTS = 0 during transmission and RTS = 1 during reception

1: RTS = 1 during transmission and RTS = 0 during reception

RTSCON

Enable the transmitter to control the RTS pin.

0: transmitter does not control RTS pin

1: transmitter controls RTS pin

reserved

TXDISABLE

Disable transmitter. UART does not send serial data out on the
transmit pin, but the transmit FIFO will continue to receive data from
host until full. Any data in the TSR will be sent out before the
transmitter goes into disable state.

0: transmitter is enabled

1: transmitter is disabled

RXDISABLE

Disable receiver. UART will stop receiving data immediately once this
bit is set to 1, and any data in the TSR will be sent to the receive FIFO.
User is advised not to set this bit during receiving.

0: receiver is enabled

1: receiver is disabled

9-BIT MODE

Enable 9-bit or Multidrop mode (RS-485).

0: normal RS-232 mode

1: enables RS-485 mode

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Philips Semiconductors

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Dual UART with I

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9.2 RS-485 RTS output inversion

EFCR bit 5 reverses the polarity of the RTS pin if the UART is in auto RS-485 RTS mode.
When the transmitter has data to be sent it deasserts the RTS pin (logic 1), and when the
last bit of the data has been sent out the transmitter asserts the RTS pin (logic 0).

9.3 Auto RS-485

EFCR bit 0 is used to enable the RS-485 mode (multidrop or 9-bit mode). In this mode of
operation, a `master' station transmits an address character followed by data characters
for the addressed `slave' stations. The slave stations examine the received data and
interrupt the controller if the received character is an address character (parity bit = 1).

To use the auto RS-485 RTS mode the software would have to disable the hardware flow
control function.

9.3.1 Normal multidrop mode

The 9-bit mode in EFCR (bit 0) is enabled, but not Special Character Detect (EFR bit 5).
The receiver is set to Force Parity 0 (LCR[5:3] = 111) in order to detect address bytes.

With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an
address byte is received (parity bit = 1). This address byte will cause the UART to set the
parity error. The UART will generate a line status interrupt (IER bit 2 must be set to `1' at
this time), and at the same time puts this address byte in the RXFIFO. After the controller
examines the byte it must make a decision whether or not to enable the receiver; it should
enable the receiver if the address byte addresses its ID address, and must not enable the
receiver if the address byte does not address its ID address.

If the controller enables the receiver, the receiver will receive the subsequent data until
being disabled by the controller after the controller has received a complete message from
the `master' station. If the controller does not disable the receiver after receiving a
message from the `master' station, the receiver will generate a parity error upon receiving
another address byte. The controller then determines if the address byte addresses its ID
address, if it is not, the controller then can disable the receiver. If the address byte
addresses the `slave' ID address, the controller take no further action; the receiver will
receive the subsequent data.

9.3.2 Auto address detection

If Special Character Detect is enabled (EFR[5] is set and XOFF2 contains the address
byte) the receiver will try to detect an address byte that matches the programmed
character in XOFF2. If the received byte is a data byte or an address byte that does not
match the programmed character in XOFF2, the receiver will discard these data. Upon
receiving an address byte that matches the XOFF2 character, the receiver will be
automatically enabled if not already enabled, and the address character is pushed into the
RXFIFO along with the parity bit (in place of the parity error bit). The receiver also
generates a line status interrupt (IER bit 2 must be set to 1 at this time). The receiver will
then receive the subsequent data from the `master' station until being disabled by the
controller after having received a message from the `master' station.

If another address byte is received and this address byte does not match XOFF2
character, the receiver will be automatically disabled and the address byte is ignored. If
the address byte matches XOFF2 character, the receiver will put this byte in the RXFIFO
along with the parity bit in the parity error bit (LSR[2]).

9397 750 14333

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Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

10. I

C-bus operation

The two lines of the I

C-bus are a serial data line (SDA) and a serial clock line (SCL). Both

lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the
bus is not busy. Each device is recognized by a unique address whether it is a
microcomputer, LCD driver, memory or keyboard interface and can operate as either a
transmitter or receiver, depending on the function of the device. A device generating a
message or data is a transmitter, and a device receiving the message or data is a
receiver. Obviously, a passive function like an LCD driver could only be a receiver, while a
microcontroller or a memory can both transmit and receive data.

10.1 Data transfers

One data bit is transferred during each clock pulse (see

Figure 12

). The data on the SDA

line must remain stable during the HIGH period of the clock pulse in order to be valid.
Changes in the data line at this time will be interpreted as control signals. A HIGH-to-LOW
transition of the data line (SDA) while the clock signal (SCL) is HIGH indicates a START
condition, and a LOW-to-HIGH transition of the SDA while SCL is HIGH defines a STOP
condition (see

Figure 13

). The bus is considered to be busy after the START condition and

free again at a certain time interval after the STOP condition. The START and STOP
conditions are always generated by the master.

The number of data bytes transferred between the START and STOP condition from
transmitter to receiver is not limited. Each byte, which must be eight bits long, is
transferred serially with the most significant bit first, and is followed by an acknowledge bit.
(see

Figure 14

). The clock pulse related to the acknowledge bit is generated by the

master. The device that acknowledges has to pull down the SDA line during the
acknowledge clock pulse, while the transmitting device releases this pulse (see

Figure 15

Fig 12. Bit transfer on the I

C-bus

Fig 13. START and STOP conditions

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

mba608

SDA

SCL

STOP condition

SDA

SCL

START condition

9397 750 14333

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Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

A slave receiver must generate an acknowledge after the reception of each byte, and a
master must generate one after the reception of each byte clocked out of the slave
transmitter. When designing a system, it is necessary to take into account cases when
acknowledge is not received. This happens, for example, when the addressed device is
busy in a real-time operation. In such a case the master, after an appropriate `time-out',
should abort the transfer by generating a STOP condition, allowing other transfers to take
place. These `other transfers' could be initiated by other masters in a multimaster system,
or by this same master.

There are two exceptions to the `acknowledge after every byte' rule. The first occurs when
a master is a receiver: it must signal an end of data to the transmitter by not signalling an
acknowledge on the last byte that has been clocked out of the slave. The acknowledge
related clock generated by the master should still take place, but the SDA line will not be
pulled down. In order to indicate that this is an active and intentional lack of
acknowledgement, we shall term this special condition as a `negative acknowledge'.

The second exception is that a slave will send a negative acknowledge when it can no
longer accept additional data bytes. This occurs after an attempted transfer that cannot be
accepted.

Fig 14. Data transfer on the I

C-bus

SDA

SCL

MSB

2 to 7

ACK

002aab012

START

condition

STOP

condition

acknowledgement signal
from receiver

byte complete,

interrupt within receiver

clock line held LOW
while interrupt is serviced

Fig 15. Acknowledge on the I

C-bus

002aab013

data output

by transmitter

data output

by receiver

SCL from master

START

condition

transmitter stays off of the bus
during the acknowledge clock

acknowledgement signal
from receiver

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Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

10.2 Addressing and transfer formats

Each device on the bus has its own unique address. Before any data is transmitted on the
bus, the master transmits on the bus the address of the slave to be accessed for this
transaction. A well-behaved slave with a matching address, if it exists on the network,
should of course acknowledge the master's addressing. The addressing is done by the
first byte transmitted by the master after the START condition.

An address on the network is seven bits long, appearing as the most significant bits of the
address byte. The last bit is a direction (R/W) bit. A zero indicates that the master is
transmitting (`write') and a one indicates that the master requests data (`read'). A complete
data transfer, comprised of an address byte indicating a `write' and two data bytes is
shown in

Figure 16

When an address is sent, each device in the system compares the first seven bits after the
START with its own address. If there is a match, the device will consider itself addressed
by the master, and will send an acknowledge. The device could also determine if in this
transaction it is assigned the role of a slave receiver or slave transmitter, depending on the
R/W bit.

Each node of the I

C-bus network has a unique seven-bit address. The address of a

microcontroller is of course fully programmable, while peripheral devices usually have
fixed and programmable address portions.

When the master is communicating with one device only, data transfers follow the format
of

Figure 16

, where the R/W bit could indicate either direction. After completing the

transfer and issuing a STOP condition, if a master would like to address some other
device on the network, it could start another transaction by issuing a new START.

Another way for a master to communicate with several different devices would be by using
a `Repeated START'. After the last byte of the transaction was transferred, including its
acknowledge (or negative acknowledge), the master issues another START, followed by
address byte and data--without effecting a STOP. The master may communicate with a
number of different devices, combining `reads' and `writes'. After the last transfer takes
place, the master issues a STOP and releases the bus. Possible data formats are
demonstrated in

Figure 17

. Note that the repeated START allows for both change of a

slave and a change of direction, without releasing the bus. We shall see later on that the
change of direction feature can come in handy even when dealing with a single device.

Fig 16. A complete data transfer

SDA

SCL

0 to 6

ACK

002aab046

START

condition

STOP

condition

address

R/W

0 to 6

data

ACK

0 to 6

data

ACK

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Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

In a single master system, the `Repeated START' mechanism may be more efficient than
terminating each transfer with a STOP and starting again. In a multimaster environment,
the determination of which format is more efficient could be more complicated, as when a
master is using repeated STARTs occupies the bus for a long time, and thus preventing
other devices from initiating transfers.

Fig 17. I

C-bus data formats

002aab458

DATA

SLAVE ADDRESS

master write:

DATA

data transferred

(n bytes + acknowledge)

START condition

STOP condition

acknowledge

write

DATA

SLAVE ADDRESS

master read:

DATA

data transferred

(n bytes + acknowledge)

START condition

STOP condition

acknowledge

not

acknowledge

read

DATA

SLAVE ADDRESS

combined

formats:

R/W

DATA

data transferred

(n bytes + acknowledge)

START condition

STOP condition

acknowledge

read or

write

SLAVE ADDRESS

R/W

repeated
START condition

acknowledge

read or

write

direction of transfer

may change at this point

data transferred

(n bytes + acknowledge)

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Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

10.3 Addressing

Before any data is transmitted or received, the master must send the address of the
receiver via the SDA line. The first byte after the START condition carries the address of
the slave device and the read/write bit.

Table 32

shows how the SC16IS752/SC16IS762's

address can be selected by using A1 and A0 pins. For example, if these 2 pins are
connected to V

, then the SC16IS752/SC16IS762's address is set to 0x90, and the

master communicates with it through this address.

[1]

X = logic 0 for write cycle; X = logic 1 for read cycle.

10.4 Use of sub-addresses

When a master communicates with the SC16IS752/SC16IS762 it must send a
sub-address in the byte following the slave address byte. This sub-address is the internal
address of the word the master wants to access for a single byte transfer, or the beginning
of a sequence of locations for a multi-byte transfer. A sub-address is an 8-bit byte. Unlike
the device address, it does not contain a direction (R/W) bit, and like any byte transferred
on the bus it must be followed by an acknowledge.

A register write cycle is shown in

Figure 18

. The START is followed by a slave address

byte with the direction bit set to `write', a sub-address byte, a number of data bytes, and a
STOP signal. The sub-address indicates which register the master wants to access. and
the data bytes which follow will be written one after the other to the sub-address location.

Table 32:

SC16IS752/SC16IS762 address map

SC16IS752/SC16IS762 I

C address (hex)

[1]

0x90 (1001 000X)

0x92 (1001 001X)

SCL

0x94 (1001 010X)

SDA

0x96 (1001 011X)

0x98 (1001 100X)

0x9A (1001 101X)

SCL

0x9C (1001 110X)

SDA

0x9E (1001 111X)

SCL

0xA0 (1010 000X)

SCL

0xA2 (1010 001X)

SCL

0xA4 (1010 010X)

SCL

SDA

0xA6 (1010 011X)

SDA

0xA8 (1010 100X)

SDA

0xAA (1010 101X)

SDA

SCL

0xAC (1010 110X)

SDA

0xAE (1010 111X)

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Dual UART with I

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The register read cycle (see

Figure 19

) commences in a similar manner, with the master

sending a slave address with the direction bit set to WRITE with a following sub-address.
Then, in order to reverse the direction of the transfer, the master issues a Repeated
START followed again by the device address, but this time with the direction bit set to
READ. The data bytes starting at the internal sub-address will be clocked out of the
device, each followed by a master-generated acknowledge. The last byte of the read cycle
will be followed by a negative acknowledge, signalling the end of transfer. The cycle is
terminated by a STOP signal.

White block: host to SC16IS752/SC16IS762

Grey block: SC16IS752/SC16IS762 to host

Fig 18. Master writes to slave

SLAVE ADDRESS

002aab047

nDATA

White block: host to SC16IS752/SC16IS762

Grey block: SC16IS752/SC16IS762 to host

Fig 19. Master read from slave

SLAVE ADDRESS

002aab048

SLAVE ADDRESS

nDATA

LAST DATA

Table 33:

Register address byte (I

Bit

Name

Function

not used

6:3

A[3:0]

UART's internal register select

2:1

CH1, CH0

Channel select.

00 = channel A

01 = channel B

10 = reserved

11 = reserved

not used

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xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x

9397 750 14333

oninklijk

e Philips Electronics N.V

. 2006. All r

ights reser

ed.

Pr
oduct data sheet

Re
v

.
01 -- 4 Jan

uar

y 2006

42 of 59

Philips Semiconductor

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Dual U

with I

C-b

us/SPI interface

, 64-b

yte FIFOs, IrD

A SIR

11.

SPI operation

R/W = 0; A[3:0] = register address; CH[1:0] = 00 for channel A, CH[1:0] = 01 for channel B

a. Register write

R/W = 1; A[3:0] = register address; CH[1:0] = 00 for channel A, CH[1:0] = 01 for channel B

b. Register read

R/W = 0; A[3:0] = 0000; CH[1:0] = 00 for channel A, CH[1:0] = 01 for channel B

c. FIFO write cycle

R/W = 1; A[3:0] = 0000; CH[1:0] = 00 for channel A, CH[1:0] = 01 for channel B

d. FIFO read cycle

Fig 20. SPI operation

R/W

SCLK

CH1

CH0

002aab433

R/W

SCLK

CH1

CH0

002aab434

R/W

SCLK

CH1

CH0

002aab435

last bit

R/W

SCLK

CH1

CH0

002aab436

last bit

9397 750 14333

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Philips Semiconductors

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Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

12. Limiting values

[1]

5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present.
4.6 V steady state voltage tolerance on inputs and outputs when no supply voltage is present.

Table 34:

Register address byte (SPI)

Bit

Name

Function

R/W

Read/write.

1 = read from UART

0 = write to UART

6:3

A[3:0]

UART's internal register select

2:1

CH1, CH0

Channel select.

00 = channel A

01 = channel B

10 = reserved

11 = reserved

not used

Table 35:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

supply voltage

0.3

+4.6

input voltage

any input

0.3

+5.5

[1]

input current

any input

+10

output current

any output

+10

tot

total power dissipation

300

P/out

power dissipation per output

amb

ambient temperature

operating

+85

stg

storage temperature

+150

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C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

13. Static characteristics

Table 36:

Static characteristics

= (2.5 V

0.2 V) or (3.3 V

0.3 V); T

amb

= 40

C to +85

C; unless otherwise specified.

Symbol

Parameter

Conditions

= 2.5 V

= 3.3 V

Unit

Min

Max

Min

Max

Supplies

supply voltage

2.3

2.7

3.0

3.6

supply current

operating; no load

6.0

Inputs I2C/SPI, RX, CTS

HIGH-state input voltage

1.6

5.5

[1]

2.0

5.5

[1]

LOW-state input voltage

0.6

0.8

leakage current

input; V

= 0 V or 5.5 V

[1]

input capacitance

Outputs TX, RTS, SO

HIGH-state output voltage

400

1.85

4 mA

2.4

LOW-state output voltage

= 1.6 mA

0.4

= 4 mA

0.4

output capacitance

Inputs/outputs GPIO0 to GPIO7

HIGH-state input voltage

1.6

5.5

[1]

2.0

5.5

[1]

LOW-state input voltage

0.6

0.8

HIGH-state output voltage

400

1.85

4 mA

2.4

LOW-state output voltage

= 1.6 mA

0.4

= 4 mA

0.4

leakage current

input; V

= 0 V or 5.5 V

[1]

output capacitance

Output IRQ

LOW-state output voltage

= 1.6 mA

0.4

= 4 mA

0.4

output capacitance

C-bus input/output SDA

HIGH-state input voltage

1.6

5.5

[1]

2.0

5.5

[1]

LOW-state input voltage

0.6

0.8

LOW-state output voltage

= 1.6 mA

0.4

= 4 mA

0.4

leakage current

input; V

= 0 V or 5.5 V

[1]

output capacitance

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Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

[1]

5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 3.8 V steady state voltage
tolerance on inputs and outputs when no supply voltage is present.

[2]

XTAL2 should be left open when XTAL1 is driven by an external clock.

C-bus inputs SCL, CS/A0, SI/A1

HIGH-state input voltage

1.6

5.5

[1]

2.0

5.5

[1]

LOW-state input voltage

0.6

0.8

leakage current

input; V

= 0 V or 5.5 V

[1]

input capacitance

Clock input XTAL1

[2]

HIGH-state input voltage

1.8

5.5

[1]

2.4

5.5

[1]

LOW-state input voltage

0.45

0.6

leakage current

input; V

= 0 V or 5.5 V

[1]

+30

input capacitance

Sleep current

DD(sleep)

Sleep mode supply current

inputs are at V

or ground

Table 36:

Static characteristics

...continued

= (2.5 V

0.2 V) or (3.3 V

0.3 V); T

amb

= 40

C to +85

C; unless otherwise specified.

Symbol

Parameter

Conditions

= 2.5 V

= 3.3 V

Unit

Min

Max

Min

Max

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Philips Semiconductors

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Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

14. Dynamic characteristics

[1]

Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if SDA is held LOW for a
minimum of 25 ms.

[2]

A detailed description of the I

C-bus specification, with applications, is given in brochure

"The I2C-bus and how to use it". This brochure

may be ordered using the code 9398 393 40011.

[3]

2 X1 clocks or 3

s, whichever is less.

Table 37:

C-bus timing specifications

All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
V

= (2.5 V

0.2 V) or (3.3 V

0.3 V); T

amb

C to +85

C; and refer to V

and V

with an input voltage of V

to V

All output load = 25 pF, except SDA output load = 400 pF.

Symbol

Parameter

Conditions

Standard mode

C-bus

Fast mode

C-bus

Unit

Min

Max

Min

Max

SCL

SCL clock frequency

[1]

100

400

kHz

BUF

bus free time between STOP condition and
START condition

4.7

1.3

HD;STA

START condition hold time

4.0

0.6

SU;STA

START condition set-up time

4.7

0.6

SU;STO

STOP condition set-up time

4.7

0.6

HD;DAT

data hold time

VD;ACK

data valid acknowledge time

0.6

VD;DAT

data valid time

SCL LOW to
data out valid

0.6

SU;DAT

data set-up time

250

150

LOW

SCL LOW time

4.7

1.3

HIGH

SCL HIGH time

4.0

0.6

fall time SDA and SCL

300

rise time SDA and SCL

1000

300

pulse width of spikes which must be
suppressed by the input filter

C-bus GPIO output valid time

0.5

C-bus modem input interrupt valid time

0.2

C-bus modem input interrupt clear time

0.2

I2C input pin interrupt valid time

0.2

I2C input pin interrupt clear time

0.2

C-bus receive interrupt valid time

0.2

C-bus receive interrupt clear time

0.2

C-bus transmit interrupt clear time

1.0

0.5

d15

SCL delay after reset

[3]

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Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Table 39:

SPI-bus timing specifications

All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
V

= (2.5 V

0.2 V) or (3.3 V

0.3 V); T

amb

C to +85

C; and refer to V

and V

with an input voltage of V

to V

All output load = 25 pF, unless otherwise specified.

Symbol

Parameter

Conditions

= 2.5 V

= 3.3 V

Unit

Min

Max

Min

Max

CS HIGH to SO 3-state

= 100 pF

100

CSS

CS to SCLK setup time

100

CSH

CS to SCLK hold time

SCLK fall to SO valid delay time

= 100 pF

SI to SCLK setup time

SI to SCLK hold time

SCLK period

+ t

SCLK HIGH time

SCLK LOW time

CSW

CS HIGH pulse width

200

SPI output data valid time

200

d10

SPI modem output data valid time

200

d11

SPI transmit interrupt clear time

200

d12

SPI modem input interrupt clear time

200

d13

SPI interrupt clear time

200

d14

SPI receive interrupt clear time

200

Fig 30. Detailed SPI-bus timing

CSH

CSS

CSH

SCLK

002aab066

CSW

9397 750 14333

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Philips Semiconductors

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Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

16. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.
However, to be totally safe, it is desirable to take precautions appropriate to handling MOS
devices. Advice can be found in

Data Handbook IC24 under "Handling MOS devices".

17. Soldering

17.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of
soldering ICs can be found in our

Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is recommended.

17.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)
vary between 100 seconds and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215

C to 270

C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

below 225

C (SnPb process) or below 245

C (Pb-free process)

for all BGA, HTSSON..T and SSOP..T packages

for packages with a thickness

2.5 mm

for packages with a thickness < 2.5 mm and a volume

350 mm

so called

thick/large packages.

below 240

C (SnPb process) or below 260

C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm

so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

17.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically
developed.

If wave soldering is used the following conditions must be observed for optimal results:

9397 750 14333

Product data sheet

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56 of 59

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

For packages with leads on four sides, the footprint must be placed at a 45

angle to

the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250

or 265

C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.

17.4 Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300

When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270

C and 320

17.5 Package related soldering information

[1]

For more detailed information on the BGA packages refer to the

(LF)BGA Application Note (AN01026);

order a copy from your Philips Semiconductors sales office.

Table 40:

Suitability of surface mount IC packages for wave and reflow soldering methods

Package

[1]

Soldering method

Wave

Reflow

[2]

BGA, HTSSON..T

[3]

, LBGA, LFBGA, SQFP,

SSOP..T

[3]

, TFBGA, VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS

not suitable

[4]

suitable

PLCC

[5]

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

[5] [6]

suitable

SSOP, TSSOP, VSO, VSSOP

not recommended

[7]

suitable

CWQCCN..L

[8]

, PMFP

[9]

, WQCCN..L

[8]

not suitable

9397 750 14333

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Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

[2]

All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal or
external package cracks may occur due to vaporization of the moisture in them (the so called popcorn
effect). For details, refer to the Drypack information in the

Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[3]

These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no
account be processed through more than one soldering cycle or subjected to infrared reflow soldering with
peak temperature exceeding 217

C measured in the atmosphere of the reflow oven. The package

body peak temperature must be kept as low as possible.

[4]

These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the
solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink
on the top side, the solder might be deposited on the heatsink surface.

[5]

If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6]

Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7]

Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger
than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8]

Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by
using a hot bar soldering process. The appropriate soldering profile can be provided on request.

[9]

Hot bar soldering or manual soldering is suitable for PMFP packages.

18. Abbreviations

19. Revision history

Table 41:

Abbreviations

Acronym

Description

CPU

Central Processing Unit

FIFO

First In, First Out

GPIO

General Purpose Input/Output

C-bus

Inter IC bus

IrDA

Infrared Data Association

LCD

Liquid Crystal Display

POR

Power-On Reset

SIR

Serial InfraRed

SPI

Serial Peripheral Interface

UART

Universal Asynchronous Receiver/Transmitter

Table 42:

Revision history

Document ID

Release date

Data sheet status

Change notice Doc. number

Supersedes

SC16IS752_SC16IS762_1 20060104

Product data sheet

9397 750 14333

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

9397 750 14333

Product data sheet

Rev. 01 -- 4 January 2006

58 of 59

20. Data sheet status

[1]

Please consult the most recently issued data sheet before initiating or completing a design.

[2]

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

21. Definitions

Short-form specification -- The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.

Application information -- Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
makes no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.

22. Disclaimers

Life support -- These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status `Production'),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.

23. Trademarks

Notice -- All referenced brands, product names, service names and
trademarks are the property of their respective owners.
I

C-bus -- logo is a trademark of Koninklijke Philips Electronics N.V.

24. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com

Level

Data sheet status

[1]

Product status

[2] [3]

Definition

Objective data

Development

This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Qualification

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.

Date of release: 4 January 2006

Document number: 9397 750 14333

Published in The Netherlands

Philips Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

25. Contents

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1

General features . . . . . . . . . . . . . . . . . . . . . . . . 1

2.2

C-bus features . . . . . . . . . . . . . . . . . . . . . . . . 2

2.3

SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pinning information . . . . . . . . . . . . . . . . . . . . . . 5

6.1

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

Functional description . . . . . . . . . . . . . . . . . . . 8

7.1

Trigger levels. . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.2

Hardware flow control . . . . . . . . . . . . . . . . . . . . 8

7.2.1

Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.2.2

Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7.3

Software flow control . . . . . . . . . . . . . . . . . . . 10

7.3.1

Receive flow control . . . . . . . . . . . . . . . . . . . . 11

7.3.2

Transmit flow control . . . . . . . . . . . . . . . . . . . . 11

7.4

Hardware Reset, Power-On Reset (POR) and
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . 13

7.5

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.5.1

Interrupt mode operation . . . . . . . . . . . . . . . . 15

7.5.2

Polled mode operation . . . . . . . . . . . . . . . . . . 15

7.6

Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.7

Break and time-out conditions . . . . . . . . . . . . 16

7.8

Programmable baud rate generator . . . . . . . . 16

Register descriptions . . . . . . . . . . . . . . . . . . . 19

8.1

Receive Holding Register (RHR) . . . . . . . . . . 21

8.2

Transmit Holding Register (THR) . . . . . . . . . . 21

8.3

FIFO Control Register (FCR) . . . . . . . . . . . . . 22

8.4

Line Control Register (LCR) . . . . . . . . . . . . . . 23

8.5

Line Status Register (LSR) . . . . . . . . . . . . . . . 25

8.6

Modem Control Register (MCR) . . . . . . . . . . . 26

8.7

Modem Status Register (MSR). . . . . . . . . . . . 27

8.8

Interrupt Enable Register (IER) . . . . . . . . . . . 28

8.9

Interrupt Identification Register (IIR). . . . . . . . 29

8.10

Enhanced Features Register (EFR) . . . . . . . . 30

8.11

Division registers (DLL, DLH) . . . . . . . . . . . . . 30

8.12

Transmission Control Register (TCR) . . . . . . . 31

8.13

Trigger Level Register (TLR). . . . . . . . . . . . . . 31

8.14

Transmitter FIFO Level register (TXLVL) . . . . 31

8.15

Receiver FIFO Level register (RXLVL) . . . . . . 32

8.16

Programmable I/O pins Direction register
(IODir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.17

Programmable I/O pins State register
(IOState). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.18

I/O Interrupt Enable register (IOIntEna) . . . . . 32

8.19

I/O Control register (IOControl) . . . . . . . . . . . 33

8.20

Extra Features Control Register (EFCR) . . . . 34

RS-485 features . . . . . . . . . . . . . . . . . . . . . . . . 34

9.1

Auto RS-485 RTS control . . . . . . . . . . . . . . . . 34

9.2

RS-485 RTS output inversion. . . . . . . . . . . . . 35

9.3

Auto RS-485. . . . . . . . . . . . . . . . . . . . . . . . . . 35

9.3.1

Normal multidrop mode . . . . . . . . . . . . . . . . . 35

9.3.2

Auto address detection. . . . . . . . . . . . . . . . . . 35

C-bus operation . . . . . . . . . . . . . . . . . . . . . . 36

10.1

Data transfers. . . . . . . . . . . . . . . . . . . . . . . . . 36

10.2

Addressing and transfer formats . . . . . . . . . . 38

10.3

Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

10.4

Use of sub-addresses . . . . . . . . . . . . . . . . . . 40

SPI operation . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 43

Static characteristics . . . . . . . . . . . . . . . . . . . 44

Dynamic characteristics . . . . . . . . . . . . . . . . . 46

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 53

Handling information . . . . . . . . . . . . . . . . . . . 55

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

17.1

Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

17.2

Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 55

17.3

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 55

17.4

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 56

17.5

Package related soldering information . . . . . . 56

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 57

Revision history . . . . . . . . . . . . . . . . . . . . . . . 57

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 58

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Contact information . . . . . . . . . . . . . . . . . . . . 58

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SC16IS762IPW

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SC16IS762IPW