Philips Semiconductors

Product specification

SCN2681T

Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04

8531002 19970

DESCRIPTION

The Philips Semiconductors SCN2681 Dual Universal
Asynchronous Receiver/Transmitter (DUART) is a single-chip
MOS-LSI communications device that provides two independent
full-duplex asynchronous receiver/transmitter channels in a single
package. The SCN2681T features a faster bus cycle time than the
standard SCN2681. The quick bus cycle eliminates or reduces the
need for wait states with fast CPUs and permits high throughput in
I/O intensive systems. Higher external clock rates may be used with
the transmitter, receiver and counter timer which in turn provide
greater versatility in baud rate generation. The SCN2681T
interfaces directly with microprocessors and may be used in a polled
or interrupt driven system.

The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of eighteen fixed
baud rates, a 16X clock derived from a programmable counter/timer,
or an external 1X or 16X clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly
attractive for dual-speed channel applications such as clustered
terminal systems.

Each receiver is quadruple buffered to minimize the potential of
receiver over-run or to reduce interrupt overhead in interrupt driven
systems. In addition, a flow control capability is provided to disable
a remote DUART transmitter when the receiver buffer is full.

Also provided on the SCN2681T are a multipurpose 7-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.

For a complete functional description and programming information
for the SCN2681T, refer to the SCN2681 product specification.

FEATURES

Fast bus cycle times reduce or eliminate CPU wait states

Dual full-duplex asynchronous receiver/transmitters

Quadruple buffered receiver data registers

Programmable data format

5 to 8 data bits plus parity

Odd, even, no parity or force parity

1, 1.5 or 2 stop bits programmable in 1/16-bit increments

16-bit programmable Counter/Timer

Programmable baud rate for each receiver and transmitter
selectable from:

22 fixed rates: 50 to 115.2k baud

Non-standard rates to 115.2

Non-standard user-defined rate derived from programmable

counter/timer

External 1X or 16X clock

Parity, framing, and overrun error detection

False start bit detection

Line break detection and generation

Programmable channel mode

Normal (full-duplex)

Automatic echo

Local loopback

Remote loopback

Multi-function programmable 16-bit counter/timer

Multi-function 7-bit input port

Can serve as clock or control inputs

Change of state detection on four inputs

100k

typical pull-up resistors

Multi-function 8-bit output port

Individual bit set/reset capability

Outputs can be programmed to be status/interrupt signals

Versatile interrupt system

Single interrupt output with eight maskable interrupting

conditions

Output port can be configured to provide a total of up to six

separate wire-ORable interrupt outputs

Maximum data transfer rates:
1X 1MB/sec transmitter and receiver; 16X 500kB/sec receiver
and 250kB/sec transmitter

Automatic wake-up mode for multidrop applications

Start-end break interrupt/status

Detects break which originates in the middle of a character

On-chip crystal oscillator

Single +5V power supply

Commercial and industrial temperature ranges available

ORDERING INFORMATION

DESCRIPTION

= +5V +10%, T

= 0

C to +70

DWG #

40-Pin Plastic Dual In-Line Package (600mil-wide DIP)

SCN2681TC1N40

SOT129-1

44-Pin Plastic Lead Chip Carrier (PLCC)

SCN2681TC1A44

SOT187-2

NOTE: For a full register description and programming information see the SCN2681.

Philips Semiconductors

Product specification

SCN2681T

Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04

PIN CONFIGURATIONS

PIN/FUNCTION PIN/FUNCTION

23 NC

24 INTRN

IP3

25 D6

26 D4

IP1

27 D2

28 D0

29 OP6

IP0

30 OP4

WRN

31 OP2

10 RDN

32 OP0

RxDB

33 TxDA

12 NC

34 NC

13 TxDB

35 RxDA

14 OP1

36 X1/CLK

15 OP3

37 X2

16 OP5

38 RESET

17 OP7

39 CEN

18 D1

40 IP2

19 D3

41 IP6

20 D5

42 IP5

21 D7

43 IP4

22 GND

44 VCC

DIP

VCC

IP4

IP5

IP6

IP2

CEN

RESET

X1/CLK

RxDA

TxDA

OP0

OP2

OP4

OP6

INTRN

IP3

IP1

IP0

WRN

RDN

RxDB

TxDB

OP1

OP3

OP5

OP7

GND

PLCC

TOP VIEW

INDEX

CORNER

SD00098

Figure 1. Pin Configurations

NOTE:
Refer to SCN2681 for functional description.

Philips Semiconductors

Product specification

SCN2681T

Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04

PIN DESCRIPTION

MNEMONIC

TYPE

NAME AND FUNCTION

D0D7

I/O

Data Bus: Bidirectional three-state data bus used to transfer commands, data and status between the DUART and
the CPU. D0 is the least significant bit.

CEN

Chip Enable: Active low input signal. When low, data transfers between the CPU and the DUART are enabled on
D0D7 as controlled by the WRN, RDN, and A0A3 inputs. When CEN is high, the DUART places the D0D7 lines in
the three-state condition.

WRN

Write Strobe: When low and CEN is also low, the contents of the data bus is loaded into the addressed register. The
transfer occurs on the rising edge of the signal.

RDN

Read Strobe: When low and CEN is also low, causes the contents of the addressed register to be presented on the
data bus. The read cycle begins on the falling edge of RDN.

A0A3

Address Inputs: Select the DUART internal registers and ports for read/write operations.

RESET

Reset: A high level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0OP7 in the high state,
stops the counter/timer, and puts channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark
(high) state. Clears Test modes, sets MR pointer to MR1.

INTRN

Interrupt Request: Active-low, open-drain output which signals the CPU that one or more of the eight maskable
interrupting conditions are true.

X1/CLK

Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency (nominally
3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock Timing.

Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin not connected although it
is permissible to ground it.

RxDA

Channel A Receiver Serial Data Input: The least significant bit is received first. `Mark' is high, `space' is low.

RxDB

Channel B Receiver Serial Data Input: The least significant bit is received first. `Mark' is high, `space' is low.

TxDA

Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the `mark'
condition when the transmitter is disabled, idle, or when operating in local loopback mode. `Mark' is high, `space' is low.

TxDB

Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the
`mark' condition when the transmitter is disabled, idle, or when operating in local loopback mode. `Mark' is high,
`space' is low.

OP0

Output 0: General purpose output, or channel A request to send (RTSAN, active-low). Can be deactivated
automatically on receive or transmit.

OP1

Output 1: General purpose output, or channel B request to send (RTSBN, active-low). Can be deactivated
automatically on receive or transmit.

OP2

Output 2: General purpose output, or channel A transmitter 1X or 16X clock output, or channel A receiver 1X clock output.

OP3

Output 3: General purpose output, or open-drain, active-low counter/timer output, or channel B transmitter 1X clock
output, or channel B receiver 1X clock output.

OP4

Output 4: General purpose output, or channel A open-drain, active-low, RxRDYA/FFULLA output.

OP5

Output 5: General purpose output, or channel B open-drain, active-low, RxRDYB/FFULLB output.

OP6

Output 6: General purpose output, or channel A open-drain, active-low, TxRDYA output.

OP7

Output 7: General purpose output, or channel B open-drain, active-low TxRDYB output.

IP0

Input 0: General purpose input, or channel A clear to send active-low input (CTSAN). Pin has an internal V

pull-up

device supplying 1 to 4

A of current.

IP1

Input 1: General purpose input, or channel B clear to send active-low input (CTSBN). Pin has an internal V

pull-up

device supplying 1 to 4

A of current.

IP2

Input 2: General purpose input, or counter/timer external clock input. Pin has an internal V

pull-up device supplying

1 to 4

A of current.

IP3

Input 3: General purpose input, or channel A transmitter external clock input (TxCA). When the external clock is used
by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal V

pull-up

device supplying 1 to 4

A of current.

IP4

Input 4: General purpose input, or channel A receiver external clock input (RxCA). When the external clock is used by
the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal V

pull-up device

supplying 1 to 4

A of current.

IP5

Input 5: General purpose input, or channel B transmitter external clock input (TxCB). When the external clock is used
by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal V

pull-up

device supplying 1 to 4

A of current.

IP6

Input 6: General purpose input, or channel B receiver external clock input (RxCB). When the external clock is used by
the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal V

pull-up device

supplying 1 to 4

A of current.

Power Supply: +5V supply input.

GND

Ground

Philips Semiconductors

Product specification

SCN2681T

Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

RATING

UNIT

Operating ambient temperature range

0 to +70

STG

Storage temperature range

-65 to +150

All voltages with respect to GND

-0.5 to +6.0

NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not
implied.

2. For operating at elevated temperatures, the device must be derated based on +150

C maximum junction temperature.

3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

DC ELECTRICAL CHARACTERISTICS

1, 2, 3

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

Min

Typ

Max

UNIT

Input low voltage

0.8

Input high voltage (except X1/CLK)

2.0

Input high voltage (X1/CLK)

3.5

Output low voltage

= 2.4mA

0.4

Output high voltage (except o.c. outputs)

= -400

2.4

Input leakage current

= 0 to V

-10

Data bus 3-state leakage current

= 0.4 to V

-10

X1L

X1/CLK low input current

= 0, X2 grounded

= 0, X2 floated

-4

-3

-2

-1.5

X1H

X1/CLK high input current

= V

, X2 = grounded

= V

, X2 floated

-1

0.2
3.5

mA
mA

X2L

X2 low input current

= 0, X1/CLK floated

-100

-30

X2H

X2 high input current

= V

, X1/CLK floated

+30

100

Open-collector output leakage current

= 0.4 to V

-10

Power supply current

150

NOTES:
1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and V

supply range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a

transition time of 20ns maximum. For X1/CLK this swing is between 0.4V and 4.0V. All time measurements are referenced at input voltages
of 0.8V and 2.0V and output voltages of 0.8V and 2.0V as appropriate.

3. Typical values are at +25

C, typical supply voltages, and typical processing parameters.

4. Test conditions for outputs: C

= 150pF, except interrupt outputs. Test conditions for interrupt outputs: C

= 50pF, R

= 2.7k

to V

5. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle

and the signal negated first terminates the cycle.

AC ELECTRICAL CHARACTERISTICS

1, 2, 3, 4

SD00028

RESET

tRES

Figure 3. Reset Timing

NOTES:
1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and V

supply range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a

3. Typical values are at +25

C, typical supply voltages, and typical processing parameters.

4. Test conditions for outputs: C

= 150pF, except interrupt outputs. Test conditions for interrupt outputs: C

= 50pF, R

= 2.7k

to V

Philips Semiconductors

Product specification

SCN2681T

Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04

SYMBOL

PARAMETER

LIMITS

UNIT

SYMBOL

PARAMETER

Min

Max

UNIT

RES

Reset pulse width

1.0

A0A3

CEN

(READ)

tAVEL

RDN

D0D7

(READ)

FLOAT

VALID

INVALID

CEN

(WRITE)

VALID

D0D7

(WRITE)

tELAX

tEHEL

tRLRH

tRHDF

tRHDI

tRLDV

tRLDA

tEHEL

tWLWH

WRN

tDVWH

tWHDI

SD00100

Figure 4. Bus Timing

SYMBOL

PARAMETER

LIMITS

UNIT

SYMBOL

PARAMETER

Min

Max

UNIT

AVEL

A0A3 setup to RDN and CEN, or WRN and CEN low

ELAX

RDN and CEN, or WRN and CEN low to A0A3 invalid

100

RLRH

RDN and CEN low to RDN or CEN high

120

EHEL

CEN high to CEN low

2, 3

110

RLDA

CEN and RDN low to data outputs active

RLDV

CEN and RDN low to data valid

100

RHDI

CEN or RDN high to data invalid

RHDF

CEN or RDN high to data outputs floating

WLWH

WRN and CEN low to WRN or CEN high

DVWH

Data input valid to WRN or CEN high

WHDI

WRN or CEN high to data invalid

NOTES:
1. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle

and the signal negated first terminates the cycle.

2. If CEN is used as the `strobing' input, the parameter defines the minimum high times between one CEN and the next. The RDN signal must

be negated for t

EHEL

to guarantee that any status register changes are valid. As a consequence, this minimum time must be met for the

RDN input even if the CEN is used as the strobing signal for bus operations.

3. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.

Philips Semiconductors

Product specification

SCN2681T

Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04

RDN

IP0IP6

WRN

OP0OP7

tPS

tPH

OLD DATA

NEW DATA

(a) INPUT PINS

tPD

(b) OUTPUT PINS

SD00101

Figure 5. Port Timing

SYMBOL

PARAMETER

LIMITS

UNIT

SYMBOL

PARAMETER

Min

Max

UNIT

Port input setup time before RDN low

Port input hold time after RDN high

Port output valid after WRN high

200

NOTE:
1. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle

and the signal negated first terminates the cycle.

NOTES:
1.

INTRN or OP3-OP7 when used as interrupt outputs.

The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching
signal, V

, to a point 0.5V above V

. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and

test environment are pronounced and can greatly affect the resultant measurement.

VOL

+0.5V

VOL

WRN

INTERRUPT

OUTPUT

tIR

SD00102

Figure 6. Interrupt Timing

SYMBOL

PARAMETER

LIMITS

UNIT

SYMBOL

PARAMETER

Min

Max

UNIT

INTRN (or OP3OP7 when used as interrupts) negated from:

Read RHR (RxRDY/FFULL interrupt)

200

Write THR (TxRDY interrupt)

200

Reset command (delta break interrupt)

200

Stop C/T command (counter interrupt)

200

Read IPCR (input port change interrupt)

200

Write IMR (clear of interrupt mask bit)

200

Philips Semiconductors

Product specification

SCN2681T

Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04

tCLK
tCTC
tRx
tTx

X1/CLK

CTCLK

RxC

TxC

+5V

3.6864MHz

DRIVING FROM

EXTERNAL SOURCE

SCN2681

74LS04

CLOCK
TO OTHER
CHIPS

+5V

CRYSTAL SERIES RESISTANCE3 SHOULD BE LESS THAN 180

R1: 100K - 1Meg (See design note)
C1 = C2: 0-5pF + (STRAY < 5pF)

tCLK
tCTC
tRx
tTx

OPEN

When using an external clock it is preferred to drive X2 and leave X1 open.
X2 is the input to the internal driver, while X1 is the output.

TO THE REST
OF THE DUART
CIRCUITS

R1 is only required if U1 will not drive to X2 high level.

Previous specifications indicated X2 should be grounded and X1
should be driven. This is still acceptable. It is electrically easier to drive
the amplifier input than to overdrive its output.

R2 = 50k

to 150k

SD00091

Figure 7. Clock Timing

SYMBOL

PARAMETER

LIMITS

UNIT

SYMBOL

PARAMETER

Min

Typ

Max

UNIT

X1/CLK high or low time

CLK

X1/CLK frequency

MHz

CLK

CTCLK (IP2) high or low time

CTC

CTCLK (IP2) frequency

MHz

CTC

RxC high or low time

RxC frequency (16X)

(1X)

0
0

3.6864

8
1

MHz
MHz

TxC high or low time

110

TxC frequency (16X)

(1X)

0
0

4
1

MHz
MHz

NOTE:
1. Minimum frequencies are not tested but are guaranteed by design.

SD00103

TxD

TxC

(INPUT)

TxC

(1X OUTPUT)

tTXD

tTCS

1 BIT TIME

(1 OR 16 CLOCKS)

Figure 8. Transmit

SYMBOL

PARAMETER

LIMITS

UNIT

SYMBOL

PARAMETER

Min

Max

UNIT

TXD

TxD output delay from TxC external clock input on IP pin

300

TCS

Output delay from TxC low at OP pin to TxD data output

100

Philips Semiconductors

Product specification

SCN2681T

Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04

RxD

D6, D7, D8 WILL BE LOST

RECEIVER

ENABLED

RxRDY

(SR0)

FFULL

(SR1)

RxRDY/

FFULL

(OP5)

RDN

D5 WILL
BE LOST

OVERRUN

(SR4)

RESET BY
COMMAND

RTS

(OP0)

OPR(0) = 1

NOTES:

1. Timing shown for MR1(7) = 1.

2. Shown for OPCR(4) = 1 and MR1(6) = 0.

S = STATUS
D = DATA

SD00105

Figure 11. Receiver Timing

TRANSMITTER

ENABLED

TxD

ADD#1

TxRDY

(SR2)

WRN

MR1(43) = 11

MR1(2) = 1

BIT 9

ADD#2 1

BIT 9

MASTER STATION

ADD#1 MR1(2) = 0 D0

MR1(2) = 1

ADD#2

RxD

ADD#1 1

BIT 9

ADD#2 1

BIT 9

PERIPHERAL STATION

BIT 9

RECEIVER

ENABLED

RxRDY

(SR0)

RDN/WRN

MR1(43) = 11

ADD#1

ADD#2

S = STATUS
D = DATA

SD00106

Figure 12. Wake-Up Mode

Philips Semiconductors

Product specification

SCN2681T

Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381

Date of release: 09-98

Document order number:

9397 750 04363

Philips

Semiconductors

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

[1]

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

Data sheet status

[1]

Please consult the most recently issued datasheet before initiating or completing a design.

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