SSTU32864

1.8 V configurable registered buffer
for DDR2 RDIMM applications

Rev. 01 -- 12 July 2004

Objective data

Description

The SSTU32864 is a 25-bit 1:1 or 14-bit 1:2 configurable registered buffer designed
for 1.7 V to 1.9 V V

operation.

All clock and data inputs are compatible with the JEDEC standard to SSTL_18. The
control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been
optimized to drive the DDR2 DIMM load.

The SSTU32864 operates from a differential clock (CK and CK). Data are registered
at the crossing of CK going HIGH, and CK going LOW.

The C0 input controls the pinout configuration of the 1:2 pinout from A configuration
(when LOW) to B configuration (when HIGH). The C1 input controls the pinout
configuration from 25-bit 1:1 (when LOW) to 14-bit 1:2 (when HIGH).

The device supports low-power standby operation. When the reset input (RESET) is
LOW, the differential input receivers are disabled, and undriven (floating) data, clock
and reference voltage (V

REF

) inputs are allowed. In addition, when RESET is LOW all

registers are reset, and all outputs are forced LOW. The LVCMOS RESET and Cn
inputs must always be held at a valid logic HIGH or LOW level.

To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.

In the DDR2 RDIMM application, RESET is specified to be completely asynchronous
with respect to CK and CK. Therefore, no timing relationship can be guaranteed
between the two. When entering reset, the register will be cleared and the data
outputs will be driven LOW quickly, relative to the time to disable the differential input
receivers. However, when coming out of reset, the register will become active quickly,
relative to the time to enable the differential input receivers. As long as the data inputs
are LOW, and the clock is stable during the time from the LOW-to-HIGH transition of
RESET until the input receivers are fully enabled, the design of the SSTU32864 must
ensure that the outputs will remain LOW, thus ensuring no glitches on the output.

The device monitors both DCS and CSR inputs and will gate the Qn outputs from
changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR
input is LOW, the Qn outputs will function normally. The RESET input has priority over
the DCS and CSR control and will force the outputs LOW. If the DCS-control
functionality is not desired, then the CSR input can be hardwired to ground, in which
case the setup time requirement for DCS would be the same as for the other D data
inputs.

The SSTU32864 is available in the LFBGA96 package.

Philips Semiconductors

SSTU32864

1.8 V configurable registered buffer for DDR2 RDIMM applications

Objective data

Rev. 01 -- 12 July 2004

2 of 19

9397 750 13339

Features

Configurable register supporting DDR2 Registered DIMM applications

Configurable to 25-bit 1:1 mode or 14-bit 1:2 mode

Controlled output impedance drivers enable optimal signal integrity and speed

Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching
propagation delay; 2.0 ns max. mass-switching)

Supports up to 450 MHz clock frequency of operation

Optimized pinout for high-density DDR2 module design

Chip-selects minimize power consumption by gating data outputs from changing
state

Supports SSTL_18 data inputs

Differential clock (CK and CK) inputs

Supports LVCMOS switching levels on the control and RESET inputs

Single 1.8 V supply operation

Available in 96-ball, 13.5

5.5 mm, 0.8 mm ball pitch LFBGA package

Ordering information

Table 1:

Ordering information

amb

= 0

C to +70

Type number

Package

Name

Description

Solder process

Version

SSTU32864EC/G LFBGA96

plastic low profile fine-pitch ball grid array
package; 96 balls; body 13.5

5.5

1.05 mm

Pb-free (SnAgCu solder ball
compound)

SOT536-1

SSTU32864EC

LFBGA96

plastic low profile fine-pitch ball grid array
package; 96 balls; body 13.5

5.5

1.05 mm

SnPb solder ball compound

SOT536-1

Philips Semiconductors

SSTU32864

1.8 V configurable registered buffer for DDR2 RDIMM applications

Objective data

Rev. 01 -- 12 July 2004

3 of 19

9397 750 13339

Pinning information

4.1 Pinning

Fig 1.

Ball mapping; 1:1 register (C0 = 0, C1 = 0); top view.

DCKE

n.c.

REF

QCKE

DNU

D15

GND

Q15

D16

Q16

DODT

n.c.

GND

QODT

DNU

D17

Q17

D18

GND

Q18

n.c.

RESET

DCS

GND

QCS

DNU

CSR

ZOH

ZOL

D19

GND

Q19

D20

Q20

D10

D21

GND

Q10

Q21

D11

D22

Q11

Q22

D12

D23

GND

Q12

Q23

D13

D24

Q13

Q24

D14

D25

REF

Q14

Q25

002aaa955

Philips Semiconductors

SSTU32864

1.8 V configurable registered buffer for DDR2 RDIMM applications

Objective data

Rev. 01 -- 12 July 2004

4 of 19

9397 750 13339

Fig 2.

Ball mapping; 1:2 register A (C0 = 0, C1 = 1); top view.

Fig 3.

Ball mapping; 1:2 register B (C0 = 1, C1 = 1); top view.

DCKE

n.c.

REF

QCKEA

QCKEB

DNU

GND

Q2A

Q2B

DNU

Q3A

Q3B

DODT

n.c.

GND

QODTA

QODTB

DNU

Q5A

Q5B

DNU

GND

Q6A

Q6B

n.c.

RESET

DCS

GND

QCSA

CSR

ZOH

ZOL

DNU

GND

Q8A

Q8B

DNU

Q9A

Q9B

D10

DNU

GND

Q10A

Q10B

D11

DNU

Q11A

Q11B

D12

DNU

GND

Q12A

Q12B

D13

DNU

Q13A

Q13B

D14

DNU

REF

Q14A

Q14B

002aaa956

QCSB

n.c.

REF

Q1A

Q1B

DNU

GND

Q2A

Q2B

DNU

Q3A

Q3B

n.c.

GND

Q4A

Q4B

DNU

Q5A

Q5B

DNU

GND

Q6A

Q6B

n.c.

RESET

DCS

GND

QCSA

CSR

ZOH

ZOL

DNU

GND

Q8A

Q8B

DNU

Q9A

Q9B

D10

DNU

GND

Q10A

Q10B

DODT

DNU

QODTA

QODTB

D12

DNU

GND

Q12A

Q12B

D13

DNU

Q13A

Q13B

DCKE

DNU

REF

QCKEA

QCKEB

002aaa957

QCSB

Philips Semiconductors

SSTU32864

1.8 V configurable registered buffer for DDR2 RDIMM applications

Objective data

Rev. 01 -- 12 July 2004

5 of 19

9397 750 13339

4.2 Pin description

[1]

Configurations:

Data inputs = D2, D3, D5, D6, D8-D25 when C0 = 0 and C1 = 0.

Data inputs = D2, D3, D5, D6, D8-D14 when C0 = 0 and C1 = 1.

Data inputs = D1-D6, D8-D10, D12, D13 when C0 = 1 and C1 = 1.

[2]

Configurations:

Data outputs = Q2, Q3, Q5, Q6, Q8-Q25 when C0 = 0 and C1 = 0.

Data outputs = Q2, Q3, Q5, Q6, Q8-Q14 when C0 = 0 and C1 = 1.

Data outputs = Q1-Q6, Q8-Q10, Q12, Q13 when C0 = 1 and C1 = 1.

Table 2:

Pin description

Symbol

Description

Electrical
characteristics

GND

Ground

ground input

Power supply voltage

1.8 V nominal

REF

Input reference voltage

0.9 V nominal

Reserved for future use

input

Reserved for future use

input

Positive master clock input

differential input

Negative master clock input

differential input

C0, C1

Configuration control inputs

LVCMOS inputs

RESET

Asynchronous reset input. Resets registers and disables
V

REF

data and clock differential-input receivers.

LVCMOS input

CSR, DCS

Chip select inputs. Disables data outputs switching when
both inputs are HIGH (see

Table note [1]

SSTL_18 input

D[1:25]

Data inputs. Clocked in on the crossing of the rising edge of
CK and the falling edge of CK.

SSTL_18 input

DODT

The outputs of this register will not be suspended by DCS
and CSR control.

SSTL_18 input

DCKE

The outputs of this register will not be suspended by DCS
and CSR control.

SSTL_18 input

Q[1:25]

The outputs that are suspended by DCS and CSR control
(see

Table note [2]

1.8 V CMOS

QCS

Data outputs that will not be suspended by DCS and CSR
control.

1.8 V CMOS

QODT

Data outputs that will not be suspended by DCS and CSR
control.

1.8 V CMOS

QCKE

Data outputs that will not be suspended by DCS and CSR
control.

1.8 V CMOS

n.c.

No-connect. Ball present but no internal connection to the
die.

DNU

Do-not-use. Ball internally connected to the die which should
be left open-circuit.

Philips Semiconductors

SSTU32864

1.8 V configurable registered buffer for DDR2 RDIMM applications

Objective data

Rev. 01 -- 12 July 2004

7 of 19

9397 750 13339

H -- HIGH voltage level

L -- LOW voltage level

-- HIGH-to-LOW transition

-- LOW-to-HIGH transition

X -- Don't care

Table 3:

Function table (each flip-flop)

Inputs

Outputs

RESET

DCS

CSR

Dn,

DODT,

DCKE

L or H

X or

floating

X or

floating

X or

floating

X or

floating

X or

floating

Philips Semiconductors

SSTU32864

1.8 V configurable registered buffer for DDR2 RDIMM applications

Objective data

Rev. 01 -- 12 July 2004

8 of 19

9397 750 13339

Limiting values

[1]

Stresses beyond those listed under `absolute maximum ratings' may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under `recommended operating
conditions' is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

[2]

The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

[3]

This value is limited to 2.5 V maximum.

Recommended operating conditions

[1]

The RESET and Cn inputs of the device must be held at valid logic levels (not floating) to ensure proper device operation. The
differential inputs must not be floating, unless RESET is LOW.

Table 4:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

supply voltage

0.5

+2.5

receiver input voltage

[2]

[3]

0.5

+2.5

driver output voltage

[2]

[3]

0.5

+ 0.5

input clamp current

< 0 V or V

> V

output clamp current

< 0 V or V

> V

continuous output current

0 < V

< V

CCC

continuous current through
each V

or GND pin

100

stg

storage temperature

+150

Table 5:

Recommended operating conditions

Symbol

Parameter

Conditions

Min

Nom

Max

Unit

supply voltage

1.7

1.9

REF

reference voltage

0.49

0.50

0.51

termination voltage

REF

40 mV

REF

+ 40 mV

input voltage

AC HIGH-level input voltage

Data inputs, CSR

REF

+ 250 mV

AC LOW-level input voltage

Data inputs, CSR

REF

250 mV

DC HIGH-level input voltage

Data inputs, CSR

REF

+ 125 mV

DC LOW-level input voltage

Data inputs, CSR

REF

125 mV

HIGH-level input voltage

RESET, Cn

0.65

LOW-level input voltage

RESET, Cn

0.35

ICR

common mode input voltage
range

CK, CK

0.675

1.125

differential input voltage

CK, CK

600

HIGH-level output current

LOW-level output current

amb

operating ambient temperature
in free air

+70

Philips Semiconductors

SSTU32864

1.8 V configurable registered buffer for DDR2 RDIMM applications

Objective data

Rev. 01 -- 12 July 2004

9 of 19

9397 750 13339

Static characteristics

Table 6:

DC electrical characteristics

Over recommended operating conditions, unless otherwise noted. Voltages are referenced to GND (ground = 0 V).
T

amb

= 0

C to +70

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

HIGH-level output voltage

6 mA; V

= 1.7 V

1.2

LOW-level output voltage

= 6 mA; V

= 1.7 V

0.5

input current

all inputs; V

= V

or GND;

= 1.9 V

static standby current

RESET = GND; I

= 0 mA;

= 1.9 V

100

static operating current

RESET = V

; I

= 0 mA;

= 1.9 V; V

= V

IH(AC)

or V

IL(AC)

DDD

dynamic operating current,
clock only

RESET = V

;

= V

IH(AC)

or V

IL(AC)

; CK and CK

switching at 50% duty cycle.
I

= 0 mA; V

= 1.9 V

A /

MHz

dynamic operating current,
per each data input, 1:1 mode

RESET = V

;

= V

IH(AC)

or V

IL(AC)

; CK and CK

switching at 50% duty cycle. One
data input switching at half clock
frequency, 50% duty cycle.
I

= 0 mA; V

= 1.9 V

A /

MHz

dynamic operating current,
per each data input, 1:2 mode

RESET = V

;

= V

IH(AC)

or V

IL(AC)

; CK and CK

switching at 50% duty cycle. One
data input switching at half clock
frequency, 50% duty cycle.
I

= 0 mA; V

= 1.9 V

A /

MHz

input capacitance, data inputs,
CSR

= V

REF

250 mV; V

= 1.8 V

2.5

3.5

input capacitance, CK and CK

ICR

= 0.9 V; V

= 600 mV;

= 1.8 V

input capacitance, RESET

= V

or GND; V

= 1.8 V

Philips Semiconductors

SSTU32864

1.8 V configurable registered buffer for DDR2 RDIMM applications

Objective data

Rev. 01 -- 12 July 2004

10 of 19

9397 750 13339

Dynamic characteristics

[1]

This parameter is not necessarily production tested.

[2]

Data inputs must be active below a minimum time of t

ACT

(max) after RESET is taken HIGH.

[3]

Data and clock inputs must be held at valid levels (not floating) a minimum time of t

INACT

(max) after RESET is taken LOW.

[1]

Includes 350 ps of test-load transmission line delay.

[2]

This parameter is not necessarily production tested.

[1]

Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).

Table 7:

Timing requirements

Over recommended operating conditions; V

= 1.8 V

0.1 V; T

amb

= 0

C to +70

C; unless otherwise noted.

See Figures

through

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

CLOCK

clock frequency

450

MHz

pulse duration, CK, CK HIGH or
LOW

ACT

differential inputs active time

[1]

[2]

INACT

differential inputs inactive time

[1]

[3]

set-up time

DCS before CK

, CK

CSR HIGH

0.7

DCS before CK

, CK

CSR LOW

0.5

CSR, ODT, CKE, and data
before CK

, CK

0.5

hold time

DCS, CSR, ODT, CKE,
and data after CK

, CK

0.5

Table 8:

Switching characteristics

Over recommended operating conditions; V

= 1.8 V

0.1 V; T

amb

= 0

C to +70

Class I, V

REF

= V

0.5 and CL = 10 pF (unless otherwise noted. See Figures

through

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

MAX

maximum input clock frequency

450

MHz

PDM

propagation delay

clock to output

[1]

1.41

1.8

PDMSS

propagation delay, simultaneous
switching

clock to output

[1]

[2]

2.0

PHL

propagation delay

reset to output

Table 9:

Output edge rates

Over recommended operating conditions, unless otherwise noted. V

= 1.8 V

0.1 V

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

dV/dt_r

rising edge slew rate

V/ns

dV/dt_f

falling edge slew rate

V/ns

dV/dt_

[1]

absolute difference between dV/dt_r
and dV/dt_f

V/ns

Philips Semiconductors

SSTU32864

1.8 V configurable registered buffer for DDR2 RDIMM applications

Objective data

Rev. 01 -- 12 July 2004

11 of 19

9397 750 13339

10. Test information

10.1 Test circuit

All input pulses are supplied by generators having the following characteristics:
PRR

10 MHz; Z

= 50

; input slew rate = 1 V/ns

20%, unless otherwise

specified.

The outputs are measured one at a time with one transition per measurement.

(1) C

includes probe and jig capacitance.

Fig 5.

Load circuit.

tested with clock and data inputs held at V

or GND, and I

= 0 mA.

Fig 6.

Voltage and current waveforms; inputs active and inactive times.

= 600 mV

= V

REF

+ 250 mV (AC voltage levels) for differential inputs. V

= V

for LVCMOS inputs.

= V

REF

250 mV (AC voltage levels) for differential inputs. V

= GND for LVCMOS inputs.

Fig 7.

Voltage waveforms; pulse duration.

RL = 100

RL = 1000

VDD

TL = 50

CK INPUTS

OUT

DUT

TEST POINT

002aaa371

TEST POINT

TL = 350 ps, 50

RL = 1000

CL = 30 pF

SEE NOTE (1)

LVCMOS

RESET

10%

IDD

(SEE NOTE)

tinact

VDD

VDD/2

tact

90%

0 V

002aaa372

VDD/2

VICR

VIH

VIL

INPUT

VID

002aaa373

Philips Semiconductors

SSTU32864

1.8 V configurable registered buffer for DDR2 RDIMM applications

Objective data

Rev. 01 -- 12 July 2004

12 of 19

9397 750 13339

= 600 mV

REF

= V

REF

+ 250 mV (AC voltage levels) for differential inputs. V

= V

for LVCMOS inputs.

= V

REF

250 mV (AC voltage levels) for differential inputs. V

= GND for LVCMOS inputs.

Fig 8.

Voltage waveforms; set-up and hold times.

PLH

and t

PHL

are the same as t

Fig 9.

Voltage waveforms; propagation delay times.

PLH

and t

PHL

are the same as t

= V

REF

+ 250 mV (AC voltage levels) for differential inputs. V

= V

for LVCMOS inputs.

= V

REF

250 mV (AC voltage levels) for differential inputs. V

= GND for LVCMOS inputs.

Fig 10. Voltage waveforms; propagation delay times.

tsu

VIH

VIL

VID

INPUT

VREF

VICR

002aaa374

VOH

VOL

OUTPUT

tPLH

002aaa375

VTT

VICR

tPHL

Vi(p-p)

tPHL

002aaa376

LVCMOS RESET

INPUT

OUTPUT

VTT

VDD/2

VIH

VIL

VOH

VOL

Philips Semiconductors

SSTU32864

1.8 V configurable registered buffer for DDR2 RDIMM applications

Objective data

Rev. 01 -- 12 July 2004

13 of 19

9397 750 13339

10.2 Output slew rate measurement

= 1.8 V

0.1 V.

All input pulses are supplied by generators having the following characteristics:
PRR

10 MHz; Z

= 50

; input slew rate = 1 V/ns

20 %, unless otherwise

specified.

(1) C

includes probe and jig capacitance.

Fig 11. Load circuit, HIGH-to-LOW slew measurement.

Fig 12. Voltage waveforms, HIGH-to-LOW slew rate measurement.

(1) C

includes probe and jig capacitance.

Fig 13. Load circuit, LOW-to-HIGH slew measurement.

Fig 14. Voltage waveforms, LOW-to-HIGH slew rate measurement.

CL = 10 pF

SEE NOTE (1)

VDD

OUT

DUT

TEST POINT

RL = 50

002aaa377

VOH

VOL

OUTPUT

80%

20%

dv_f

dt_f

002aaa378

CL = 10 pF

SEE NOTE (1)

OUT

DUT

TEST POINT

RL = 50

002aaa379

VOH

VOL

80%

20%

dv_r

dt_r

OUTPUT

002aaa380

Philips Semiconductors

SSTU32864

1.8 V configurable registered buffer for DDR2 RDIMM applications

Objective data

Rev. 01 -- 12 July 2004

14 of 19

9397 750 13339

11. Package outline

Fig 15. LFBGA96 package outline (SOT536-1).

0.8

UNIT

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

00-03-04
03-02-05

IEC

JEDEC

JEITA

1.5

0.41
0.31

1.2
0.9

5.6
5.4

13.6
13.4

0.51
0.41

0.1

0.2

DIMENSIONS (mm are the original dimensions)

SOT536-1

0.15

0.1

10 mm

scale

SOT536-1

LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm

max.

detail X

H
G

P
N

ball A1
index area

y1 C

1/2

Philips Semiconductors

SSTU32864

1.8 V configurable registered buffer for DDR2 RDIMM applications

Objective data

Rev. 01 -- 12 July 2004

15 of 19

9397 750 13339

12. Soldering

12.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our

Data Handbook IC26; Integrated Circuit

Packages (document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine
pitch SMDs. In these situations reflow soldering is recommended. In these situations
reflow soldering is recommended.

12.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215 to 270

C depending on solder

paste material. The top-surface temperature of the packages should preferably be
kept:

below 225

C (SnPb process) or below 245

C (Pb-free process)

for all BGA, HTSSON..T and SSOP..T packages

for packages with a thickness

2.5 mm

for packages with a thickness < 2.5 mm and a volume

350 mm

so called

thick/large packages.

below 240

C (SnPb process) or below 260

C (Pb-free process) for packages with

a thickness < 2.5 mm and a volume < 350 mm

so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all
times.

12.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically
developed.

If wave soldering is used the following conditions must be observed for optimal
results:

Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.

Philips Semiconductors

SSTU32864

1.8 V configurable registered buffer for DDR2 RDIMM applications

Objective data

Rev. 01 -- 12 July 2004

16 of 19

9397 750 13339

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

For packages with leads on four sides, the footprint must be placed at a 45

angle

to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250

C or

265

C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal of corrosive residues in
most applications.

12.4 Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300

When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320

12.5 Package related soldering information

[1]

For more detailed information on the BGA packages refer to the

(LF)BGA Application Note

(AN01026); order a copy from your Philips Semiconductors sales office.

[2]

All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the

Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods.

Table 10:

Suitability of surface mount IC packages for wave and reflow soldering
methods

Package

[1]

Soldering method

Wave

Reflow

[2]

BGA, HTSSON..T

[3]

, LBGA, LFBGA, SQFP,

SSOP..T

[3]

, TFBGA, USON, VFBGA

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS

not suitable

[4]

suitable

PLCC

[5]

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

[5][6]

suitable

SSOP, TSSOP, VSO, VSSOP

not recommended

[7]

suitable

CWQCCN..L

[8]

, PMFP

[9]

, WQCCN..L

[8]

not suitable

Philips Semiconductors

SSTU32864

1.8 V configurable registered buffer for DDR2 RDIMM applications

Objective data

Rev. 01 -- 12 July 2004

17 of 19

9397 750 13339

[3]

These transparent plastic packages are extremely sensitive to reflow soldering conditions and must
on no account be processed through more than one soldering cycle or subjected to infrared reflow
soldering with peak temperature exceeding 217

C measured in the atmosphere of the reflow

oven. The package body peak temperature must be kept as low as possible.

[4]

These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with
the heatsink on the top side, the solder might be deposited on the heatsink surface.

[5]

If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6]

Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7]

Wave soldering is suitable for SSOP, TSSOP, VSO and VSOP packages with a pitch (e) equal to or
larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than
0.5 mm.

[8]

Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex
foil by using a hot bar soldering process. The appropriate soldering profile can be provided on
request.

[9]

Hot bar soldering or manual soldering is suitable for PMFP packages.

13. Revision history

Table 11:

Revision history

Rev Date

CPCN

Description

20040712

Objective data (9397 750 13339)

9397 750 13339

Philips Semiconductors

SSTU32864

1.8 V configurable registered buffer for DDR2 RDIMM applications

Objective data

Rev. 01 -- 12 July 2004

18 of 19

Contact information

For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

14. Data sheet status

[1]

Please consult the most recently issued data sheet before initiating or completing a design.

[2]

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

15. Definitions

Short-form specification -- The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.

Application information -- Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.

16. Disclaimers

Life support -- These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status `Production'),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.

Level

Data sheet status

[1]

Product status

[2][3]

Definition

Objective data

Development

This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Qualification

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.

The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.

Date of release: 12 July 2004

Document order number: 9397 750 13339

Contents

Philips Semiconductors

SSTU32864

1.8 V configurable registered buffer for DDR2 RDIMM applications

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information . . . . . . . . . . . . . . . . . . . . . 2

Pinning information . . . . . . . . . . . . . . . . . . . . . . 3

4.1

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

Functional description . . . . . . . . . . . . . . . . . . . 6

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8

Recommended operating conditions. . . . . . . . 8

Static characteristics. . . . . . . . . . . . . . . . . . . . . 9

Dynamic characteristics . . . . . . . . . . . . . . . . . 10

Test information . . . . . . . . . . . . . . . . . . . . . . . . 11

10.1

Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

10.2

Output slew rate measurement. . . . . . . . . . . . 13

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

12.1

Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

12.2

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 15

12.3

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15

12.4

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 16

12.5

Package related soldering information . . . . . . 16

Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 18

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SSTU32864

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SSTU32864