General description

The SSTUA32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer designed
for 1.7 V to 2.0 V V

operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized
to drive the DDR2 DIMM load.

The SSTUA32864 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.

The C0 input controls the pinout configuration of the 1 : 2 pinout from A configuration
(when LOW) to B configuration (when HIGH). The C1 input controls the pinout
configuration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH).

The device supports low-power standby operation. When the reset input (RESET) is LOW,
the differential input receivers are disabled, and un-driven (floating) data, clock and
reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all
registers are reset, and all outputs are forced LOW. The LVCMOS RESET and Cn inputs
must always be held at a valid logic HIGH or LOW level.

To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.

In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the data outputs will be driven
LOW quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTUA32864 must ensure that the outputs will remain
LOW, thus ensuring no glitches on the output.

The device monitors both DCS and CSR inputs and will gate the Qn outputs from
changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is
LOW, the Qn outputs will function normally. The RESET input has priority over the DCS
and CSR control and will force the outputs LOW. If the DCS-control functionality is not
desired, then the CSR input can be hardwired to ground, in which case the setup time
requirement for DCS would be the same as for the other Dn data inputs.

The SSTUA32864 is available in a 96-ball, low profile fine-pitch ball grid array (LFBGA96)
package.

SSTUA32864

1.8 V configurable registered buffer for DDR2-667 RDIMM
applications

Rev. 01 -- 12 May 2005

Product data sheet

9397 750 14757

Product data sheet

Rev. 01 -- 12 May 2005

2 of 19

Philips Semiconductors

SSTUA32864

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

Features

Configurable register supporting DDR2 Registered DIMM applications

Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode

Controlled output impedance drivers enable optimal signal integrity and speed

Exceeds SSTUA32864 JEDEC specification speed performance (1.8 ns max.
single-bit switching propagation delay; 2.0 ns max. mass-switching)

Supports up to 450 MHz clock frequency of operation

Optimized pinout for high-density DDR2 module design

Chip-selects minimize power consumption by gating data outputs from changing state

Supports SSTL_18 data inputs

Differential clock (CK and CK) inputs

Supports LVCMOS switching levels on the control and RESET inputs

Single 1.8 V supply operation (1.7 V to 2.0 V)

Available in 96-ball, 13.5

5.5 mm, 0.8 mm ball pitch LFBGA package

Applications

400 MT/s to 667 MT/s DDR2 registered DIMMs without parity

Ordering information

Table 1:

Ordering information

amb

= 0

C to +70

Type number

Solder process

Package

Name

Description

Version

SSTUA32864EC/G

Pb-free (SnAgCu
solder ball compound)

LFBGA96

plastic low profile fine-pitch ball grid array package;
96 balls; body 13.5

5.5

1.05 mm

SOT536-1

SSTUA32864EC

SnPb solder ball
compound

LFBGA96

plastic low profile fine-pitch ball grid array package;
96 balls; body 13.5

5.5

1.05 mm

SOT536-1

9397 750 14757

Product data sheet

Rev. 01 -- 12 May 2005

4 of 19

Philips Semiconductors

SSTUA32864

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

Pinning information

6.1 Pinning

Fig 2.

Pin configuration for LFBGA96

Fig 3.

Ball mapping; 1 : 1 register (C0 = 0, C1 = 0); top view

002aab384

SSTUA32864EC/G

SSTUA32864EC

Transparent top view

ball A1
index area

DCKE

n.c.

VREF

QCKE

DNU

D15

GND

Q15

D16

Q16

DODT

n.c.

GND

QODT

DNU

D17

Q17

D18

GND

Q18

n.c.

RESET

DCS

GND

QCS

DNU

CSR

ZOH

ZOL

D19

GND

Q19

D20

Q20

D10

D21

GND

Q10

Q21

D11

D22

Q11

Q22

D12

D23

GND

Q12

Q23

D13

D24

Q13

Q24

D14

D25

VREF

Q14

Q25

002aaa955

9397 750 14757

Product data sheet

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Philips Semiconductors

SSTUA32864

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

Fig 4.

Ball mapping; 1 : 2 register A (C0 = 0, C1 = 1); top view

Fig 5.

Ball mapping; 1 : 2 register B (C0 = 1, C1 = 1); top view

DCKE

n.c.

VREF

QCKEA

QCKEB

DNU

GND

Q2A

Q2B

DNU

Q3A

Q3B

DODT

n.c.

GND

QODTA

QODTB

DNU

Q5A

Q5B

DNU

GND

Q6A

Q6B

n.c.

RESET

DCS

GND

QCSA

CSR

ZOH

ZOL

DNU

GND

Q8A

Q8B

DNU

Q9A

Q9B

D10

DNU

GND

Q10A

Q10B

D11

DNU

Q11A

Q11B

D12

DNU

GND

Q12A

Q12B

D13

DNU

Q13A

Q13B

D14

DNU

VREF

Q14A

Q14B

002aaa956

QCSB

n.c.

VREF

Q1A

Q1B

DNU

GND

Q2A

Q2B

DNU

Q3A

Q3B

n.c.

GND

Q4A

Q4B

DNU

Q5A

Q5B

DNU

GND

Q6A

Q6B

n.c.

RESET

DCS

GND

QCSA

CSR

ZOH

ZOL

DNU

GND

Q8A

Q8B

DNU

Q9A

Q9B

D10

DNU

GND

Q10A

Q10B

DODT

DNU

QODTA

QODTB

D12

DNU

GND

Q12A

Q12B

D13

DNU

Q13A

Q13B

DCKE

DNU

VREF

QCKEA

QCKEB

002aaa957

QCSB

9397 750 14757

Product data sheet

Rev. 01 -- 12 May 2005

6 of 19

Philips Semiconductors

SSTUA32864

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

6.2 Pin description

[1]

Depends on configuration. See

Figure 3

Figure 4

, and

Figure 5

for ball number.

[2]

Configurations:

Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.

Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.

Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.

[3]

Configurations:

Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0.

Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1.

Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.

Table 2:

Pin description

Symbol

Pin

Type

Description

GND

B3, B4, D3, D4, F3, F4,
H3, H4, K3, K4, M3,
M4, P3, P4

ground input

ground

A4, C3, C4, E3, E4,
G3, G4, J3, J4, L3, L4,
N3, N4, R3, R4, T4

1.8 V nominal

power supply voltage

VREF

A3, T3

0.9 V nominal

input reference voltage

ZOH

input

reserved for future use

ZOL

input

reserved for future use

differential input positive master clock input

differential input negative master clock input

C0, C1

G6, G5

LVCMOS inputs configuration control inputs

RESET

LVCMOS input

Asynchronous reset input (active LOW). Resets registers and
disables VREF data and clock differential-input receivers.

CSR, DCS

J2, H2

SSTL_18 input

Chip select inputs (active LOW). Disables data outputs
switching when both inputs are HIGH.

[2]

D1 to D25

[1]

SSTL_18 input

Data inputs. Clocked in on the crossing of the rising edge of
CK and the falling edge of CK.

DODT

[1]

SSTL_18 input

The outputs of this register will not be suspended by DCS and
CSR control.

DCKE

[1]

SSTL_18 input

The outputs of this register will not be suspended by DCS and
CSR control.

Q1 to Q25,
Q1A to Q14A,
Q1B to Q14B

[1]

1.8 V CMOS

The outputs that are suspended by DCS and CSR control

[3]

QCS, QCSA,
QCSB

[1]

1.8 V CMOS

Data outputs that will not be suspended by DCS and CSR
control.

QODT, QODTA,
QODTB

[1]

1.8 V CMOS

Data outputs that will not be suspended by DCS and CSR
control.

QCKE, QCKEA,
QCKEB

[1]

1.8 V CMOS

Data outputs that will not be suspended by DCS and CSR
control.

n.c.

A2, D2, G1

Not connected. Ball present but no internal connection to the
die.

DNU

[1]

Do-not-use. Ball internally connected to the die which should
be left open-circuit.

9397 750 14757

Product data sheet

Rev. 01 -- 12 May 2005

7 of 19

Philips Semiconductors

SSTUA32864

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

Functional description

7.1 Function table

[1]

is the previous state of the associated output.

Table 3:

Function table (each flip-flop)

L = LOW voltage level; H = HIGH voltage level; X = don't care;

= LOW-to-HIGH transition;

= HIGH-to-LOW transition

Inputs

Outputs

[1]

RESET

DCS

CSR

Dn,

DODT,

DCKE

QCS

QODT,

QCKE

L or H

X or

floating

X or

floating

X or

floating

X or

floating

X or

floating

9397 750 14757

Product data sheet

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Philips Semiconductors

SSTUA32864

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

Limiting values

[1]

The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

[2]

This value is limited to 2.5 V maximum.

Recommended operating conditions

[1]

The RESET and Cn inputs of the device must be held at valid logic levels (not floating) to ensure proper device operation.

[2]

The differential inputs must not be floating, unless RESET is LOW.

Table 4:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

supply voltage

0.5

+2.5

receiver input voltage

0.5

[1]

+2.5

[2]

driver output voltage

0.5

[1]

+ 0.5

[2]

input clamp current

< 0 V or V

> V

output clamp current

< 0 V or V

> V

continuous output current

0 V < V

< V

CCC

continuous current through each
V

or GND pin

100

stg

storage temperature

+150

Table 5:

Operating conditions

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

supply voltage

1.7

2.0

ref

reference voltage

0.49

0.50

0.51

termination voltage

ref

0.040

ref

+ 0.040

input voltage

IH(AC)

AC HIGH-level input voltage

data inputs (Dn), CSR

ref

+ 0.250

IL(AC)

AC LOW-level input voltage

data inputs (Dn), CSR

ref

0.250

IH(DC)

DC HIGH-level input voltage

data inputs (Dn), CSR

ref

+ 0.125

IL(DC)

DC LOW-level input voltage

data inputs (Dn), CSR

ref

0.125

HIGH-level input voltage

RESET, Cn

[1]

0.65

LOW-level input voltage

RESET, Cn

[1]

0.35

ICR

common mode input voltage
range

CK, CK

[2]

0.675

1.125

differential input voltage

CK, CK

[2]

600

HIGH-level output current

LOW-level output current

amb

ambient temperature

operating in free air

+70

9397 750 14757

Product data sheet

Rev. 01 -- 12 May 2005

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Philips Semiconductors

SSTUA32864

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

10. Characteristics

Table 6:

Characteristics

Recommended operating conditions; T

amb

= 0

C to +70

C; all voltages are referenced to GND (ground = 0 V);

unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

HIGH-level output voltage

6 mA; V

= 1.7 V

1.2

LOW-level output voltage

= 6 mA; V

= 1.7 V

0.5

input current

all inputs; V

= V

or GND;

= 2.0 V

static standby current

RESET = GND; I

= 0 mA;

= 2.0 V

100

static operating current

RESET = V

; I

= 0 mA;

= 2.0 V;

= V

IH(AC)

or V

IL(AC)

DDD

dynamic operating current per
MHz, clock only

RESET = V

;

= V

IH(AC)

or V

IL(AC)

; CK and

CK switching at 50 % duty cycle.
I

= 0 mA; V

= 2.0 V

dynamic operating current per
MHz, per each data input,
1 : 1 mode

RESET = V

;

= V

IH(AC)

or V

IL(AC)

; CK and

CK switching at 50 % duty cycle.
One data input switching at half
clock frequency, 50 % duty
cycle. I

= 0 mA; V

= 2.0 V

dynamic operating current per
MHz, per each data input,
1 : 2 mode

RESET = V

;

= V

IH(AC)

or V

IL(AC)

; CK and

CK switching at 50 % duty cycle.
One data input switching at half
clock frequency, 50 % duty
cycle. I

= 0 mA; V

= 2.0 V

input capacitance, data inputs,
CSR

= V

ref

250 mV; V

= 1.8 V

2.5

3.5

input capacitance, CK and CK

ICR

= 0.9 V; V

= 600 mV;

= 1.8 V

input capacitance, RESET

= V

or GND; V

= 1.8 V

9397 750 14757

Product data sheet

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Philips Semiconductors

SSTUA32864

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

[1]

This parameter is not necessarily production tested.

[2]

Data inputs must be active below a minimum time of t

ACT(max)

after RESET is taken HIGH.

[3]

Data and clock inputs must be held at valid levels (not floating) a minimum time of t

INACT(max)

after RESET is taken LOW.

[1]

Includes 350 ps of test-load transmission line delay.

[2]

This parameter is not necessarily production tested.

Table 7:

Timing requirements

Recommended operating conditions; T

amb

= 0

C to +70

C; V

= 1.8 V

0.1 V; unless otherwise specified.

See

Figure 6

through

Figure 11

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

clock

clock frequency

450

MHz

pulse duration, CK, CK HIGH or
LOW

ACT

differential inputs active time

[1] [2]

INACT

differential inputs inactive time

[1] [3]

setup time

DCS before CK

, CK

CSR HIGH

0.7

DCS before CK

, CK

CSR LOW

0.5

CSR, ODT, CKE, and data
before CK

, CK

0.5

hold time

DCS, CSR, ODT, CKE,
and data after CK

, CK

0.5

Table 8:

Switching characteristics

Recommended operating conditions; T

amb

= 0

C to +70

C; V

= 1.8 V

0.1 V;

Class I, V

ref

= V

0.5 and C

= 10 pF; unless otherwise specified. See

Figure 6

through

Figure 11

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

MAX

maximum input clock frequency

450

MHz

PDM

propagation delay

CK and CK to output

[1]

1.2

1.8

PDMSS

propagation delay, simultaneous
switching

CK and CK to output

[1] [2]

2.0

PHL

propagation delay

RESET to output

Table 9:

Output edge rates

Recommended operating conditions; V

= 1.8 V

0.1 V; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

dV/dt_r

rising edge slew rate

V/ns

dV/dt_f

falling edge slew rate

V/ns

dV/dt_

absolute difference between dV/dt_r
and dV/dt_f

V/ns

9397 750 14757

Product data sheet

Rev. 01 -- 12 May 2005

11 of 19

Philips Semiconductors

SSTUA32864

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

11. Test information

11.1 Test circuit

All input pulses are supplied by generators having the following characteristics:
PRR

10 MHz; Z

= 50

; input slew rate = 1 V/ns

20 %, unless otherwise specified.

The outputs are measured one at a time with one transition per measurement.

(1) C

includes probe and jig capacitance.

Fig 6.

Load circuit

(1) I

tested with clock and data inputs held at V

or GND, and I

= 0 mA.

Fig 7.

Voltage and current waveforms; inputs active and inactive times

= 600 mV

= V

ref

+ 250 mV (AC voltage levels) for differential inputs. V

= V

for LVCMOS inputs.

= V

ref

250 mV (AC voltage levels) for differential inputs. V

= GND for LVCMOS inputs.

Fig 8.

Voltage waveforms; pulse duration

= 100

= 1000

= 50

CK inputs

OUT

DUT

test point

002aaa371

test point

= 350 ps, 50

= 1000

= 30 pF

(1)

LVCMOS

RESET

10 %

(1)

INACT

ACT

90 %

0 V

002aaa372

ICR

input

002aaa373

9397 750 14757

Product data sheet

Rev. 01 -- 12 May 2005

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Philips Semiconductors

SSTUA32864

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

= 600 mV

ref

= V

ref

+ 250 mV (AC voltage levels) for differential inputs. V

= V

for LVCMOS inputs.

= V

ref

250 mV (AC voltage levels) for differential inputs. V

= GND for LVCMOS inputs.

Fig 9.

Voltage waveforms; setup and hold times

PLH

and t

PHL

are the same as t

Fig 10. Voltage waveforms; propagation delay times (clock to output)

PLH

and t

PHL

are the same as t

= V

ref

+ 250 mV (AC voltage levels) for differential inputs. V

= V

for LVCMOS inputs.

= V

ref

250 mV (AC voltage levels) for differential inputs. V

= GND for LVCMOS inputs.

Fig 11. Voltage waveforms; propagation delay times (reset to output)

input

ref

ICR

002aaa374

output

PLH

002aaa375

ICR

PHL

i(p-p)

PHL

002aaa376

LVCMOS

RESET

output

9397 750 14757

Product data sheet

Rev. 01 -- 12 May 2005

13 of 19

Philips Semiconductors

SSTUA32864

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

11.2 Output slew rate measurement

= 1.8 V

0.1 V.

All input pulses are supplied by generators having the following characteristics:
PRR

10 MHz; Z

= 50

; input slew rate = 1 V/ns

20 %, unless otherwise specified.

(1) C

includes probe and jig capacitance.

Fig 12. Load circuit, HIGH-to-LOW slew measurement

Fig 13. Voltage waveforms, HIGH-to-LOW slew rate measurement

(1) C

includes probe and jig capacitance.

Fig 14. Load circuit, LOW-to-HIGH slew measurement

Fig 15. Voltage waveforms, LOW-to-HIGH slew rate measurement

= 10 pF

(1)

OUT

DUT

test point

= 50

002aaa377

output

80 %

20 %

dv_f

dt_f

002aaa378

= 10 pF

(1)

OUT

DUT

test point

= 50

002aaa379

80 %

20 %

dv_r

dt_r

output

002aaa380

9397 750 14757

Product data sheet

Rev. 01 -- 12 May 2005

14 of 19

Philips Semiconductors

SSTUA32864

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

12. Package outline

Fig 16. Package outline SOT536-1 (LFBGA96)

0.8

UNIT

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

00-03-04
03-02-05

IEC

JEDEC

JEITA

1.5

0.41
0.31

1.2
0.9

5.6
5.4

13.6
13.4

0.51
0.41

0.1

0.2

DIMENSIONS (mm are the original dimensions)

SOT536-1

0.15

0.1

10 mm

scale

SOT536-1

LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm

max.

detail X

H
G

P
N

ball A1
index area

y1 C

1/2

9397 750 14757

Product data sheet

Rev. 01 -- 12 May 2005

15 of 19

Philips Semiconductors

SSTUA32864

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

13. Soldering

13.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of
soldering ICs can be found in our

Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is recommended.

13.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)
vary between 100 seconds and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215

C to 270

C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

below 225

C (SnPb process) or below 245

C (Pb-free process)

for all BGA, HTSSON..T and SSOP..T packages

for packages with a thickness

2.5 mm

for packages with a thickness < 2.5 mm and a volume

350 mm

so called

thick/large packages.

below 240

C (SnPb process) or below 260

C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm

so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

13.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically
developed.

If wave soldering is used the following conditions must be observed for optimal results:

Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

9397 750 14757

Product data sheet

Rev. 01 -- 12 May 2005

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Philips Semiconductors

SSTUA32864

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

For packages with leads on four sides, the footprint must be placed at a 45

angle to

the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250

or 265

C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.

13.4 Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300

When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270

C and 320

13.5 Package related soldering information

[1]

For more detailed information on the BGA packages refer to the

(LF)BGA Application Note (AN01026);

order a copy from your Philips Semiconductors sales office.

[2]

All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal or
external package cracks may occur due to vaporization of the moisture in them (the so called popcorn
effect). For details, refer to the Drypack information in the

Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[3]

These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no
account be processed through more than one soldering cycle or subjected to infrared reflow soldering with
peak temperature exceeding 217

C measured in the atmosphere of the reflow oven. The package

body peak temperature must be kept as low as possible.

Table 10:

Suitability of surface mount IC packages for wave and reflow soldering methods

Package

[1]

Soldering method

Wave

Reflow

[2]

BGA, HTSSON..T

[3]

, LBGA, LFBGA, SQFP,

SSOP..T

[3]

, TFBGA, VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS

not suitable

[4]

suitable

PLCC

[5]

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

[5] [6]

suitable

SSOP, TSSOP, VSO, VSSOP

not recommended

[7]

suitable

CWQCCN..L

[8]

, PMFP

[9]

, WQCCN..L

[8]

not suitable

9397 750 14757

Product data sheet

Rev. 01 -- 12 May 2005

17 of 19

Philips Semiconductors

SSTUA32864

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

[4]

These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the
solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink
on the top side, the solder might be deposited on the heatsink surface.

[5]

If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6]

Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7]

Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger
than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8]

Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by
using a hot bar soldering process. The appropriate soldering profile can be provided on request.

[9]

Hot bar soldering or manual soldering is suitable for PMFP packages.

14. Abbreviations

15. Revision history

Table 11:

Abbreviations

Acronym

Description

CMOS

Complementary Metal Oxide Silicon

DDR

Double Data Rate

DIMM

Dual In-line Memory Module

LVCMOS

Low Voltage Complementary Metal Oxide Silicon

PRR

Pulse Repetition Rate

RDIMM

Registered Dual In-line Memory Module

SSTL

Stub Series Terminated Logic

Table 12:

Revision history

Document ID

Release date

Data sheet status

Change notice

Doc. number

Supersedes

SSTUA32864_1

20050512

Product data sheet

9397 750 14757

Philips Semiconductors

SSTUA32864

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

9397 750 14757

Product data sheet

Rev. 01 -- 12 May 2005

18 of 19

16. Data sheet status

[1]

Please consult the most recently issued data sheet before initiating or completing a design.

[2]

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

17. Definitions

Short-form specification -- The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.

Application information -- Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.

18. Disclaimers

Life support -- These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status `Production'),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.

19. Trademarks

Notice -- All referenced brands, product names, service names and
trademarks are the property of their respective owners.

20. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com

Level

Data sheet status

[1]

Product status

[2] [3]

Definition

Objective data

Development

This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Qualification

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.

Date of release: 12 May 2005

Document number: 9397 750 14757

Published in The Netherlands

Philips Semiconductors

SSTUA32864

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

21. Contents

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information . . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

Pinning information . . . . . . . . . . . . . . . . . . . . . . 4

6.1

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

Functional description . . . . . . . . . . . . . . . . . . . 7

7.1

Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8

Recommended operating conditions. . . . . . . . 8

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Test information . . . . . . . . . . . . . . . . . . . . . . . . 11

11.1

Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

11.2

Output slew rate measurement. . . . . . . . . . . . 13

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

13.1

Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

13.2

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 15

13.3

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15

13.4

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 16

13.5

Package related soldering information . . . . . . 16

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 18

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Contact information . . . . . . . . . . . . . . . . . . . . 18

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SSTUA32864

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SSTUA32864