1995 Dec 08

Philips Semiconductors

Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

TDA1305T

FEATURES

Easy application

16f

Finite-duration Impulse-Response (FIR)

filter incorporated

Selectable system clock (f

sys

) 256f

or 384f

S-bus serial input format (at f

sys

= 256f

) or LSB fixed

16, 18 or 20 bits serial input mode (at f

sys

= 384f

)

Slave-mode clock system

Cascaded 4-stage digital filter incorporating 2-stage FIR
filter, linear interpolator and sample-and-hold

Smoothed transitions before and after muting
(soft mute)

Digital de-emphasis filter for three sampling rates of
32 kHz, 44.1 kHz and 48 kHz

12 dB attenuation via the attenuation input control

Double speed mode

2nd order noise shaper

96 (f

sys

= 384f

) or 128 (f

sys

= 256f

) times oversampling

in normal speed mode

48 (f

sys

= 384f

) or 64 (f

sys

= 256f

) times oversampling

in double speed mode

Bitstream continuous calibration concept

Small outline SO28 package

Voltage output 1.5 V (RMS) at line drive level

Low total harmonic distortion

No zero crossing distortion

Inherently monotonic

No analog post filtering required

Superior signal-to-noise ratio

Wide dynamic range (18-bit)

Single rail supply (3.4 to 5.5 V).

GENERAL DESCRIPTION

The TDA1305T is a new generation of filter-DAC which
features a unique combination of bitstream and continuous
calibration techniques. The converter functions as a

bitstream converter for low signals while large signals are
generated using the dynamic continuous calibration
technique, thus resulting in low power consumption, small
chip size and easy application.

The TDA1305T is a dual CMOS DAC with up-sampling
filter and noise shaper. The combination of high
oversampling up to 16f

, 2nd order noise shaping and

continuous calibration conversion ensures that only simple
1st order analog post filtering is required.

The TDA1305T supports the I

S-bus data input mode with

word lengths of up to 20 bits (at f

sys

= 256f

) and the LSB

fixed serial data input format with word lengths of 16, 18
and 20 bits (at f

sys

= 384f

). Four cascaded FIR filters

increase the oversampling rate to 16 times. A
sample-and-hold function increases the oversampling rate
to 96 times (f

sys

= 384f

) or 128 times (f

sys

= 256f

). A

2nd order noise shaper converts this oversampled data to
a bitstream for the 5-bit DACs.

The DACs are of the continuous calibration type and
incorporate a special date coding. This ensures an
extremely high signal-to-noise ratio, superior dynamic
range and immunity to process variation and component
ageing.

Two on-board operational amplifiers convert the
digital-to-analog current to an output voltage. Externally
connected capacitors perform the required 1st order
filtering so that no further post filtering is required.

The unique combination of bitstream and continuous
calibration techniques, together with a high degree of
analog and digital integration, results in a single filter-DAC
with 18-bit dynamic range, high linearity and simple low
cost application.

ORDERING INFORMATION

TYPE NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA1305T

SO28

plastic small outline package; 28 leads; body width 7.5 mm

SOT136-1

1995 Dec 08

Philips Semiconductors

Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

TDA1305T

QUICK REFERENCE DATA

Note

1. All V

and V

pins must be connected to the same supply.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

DDD

digital supply voltage

note 1

3.4

5.0

5.5

DDA

analog supply voltage

note 1

3.4

5.0

5.5

DDO

operational amplifier
supply voltage

note 1

3.4

5.0

5.5

DDD

digital supply current

DDD

= 5 V;

at code 00000H

DDA

analog supply current

DDA

= 5 V;

at code 00000H

5.5

DDO

operating amplifier supply
current

DDO

= 5 V;

at code 00000H

6.5

FS(rms)

full-scale output voltage
(RMS value)

DDD

= V

DDA

= V

DDO

= 5 V

1.425

1.5

1.575

(THD + N)/S

total harmonic distortion
plus noise-to-signal ratio

at 0 dB signal level

0.003

0.009

60 dB signal level

0.63

0.1

60 dB signal level;

A-weighted

0.5

S/N

signal-to-noise ratio at
bipolar zero

A-weighting;
at code 00000H

100

108

input bit rate at data input f

= 48 kHz; normal speed

3.072

Mbits

input bit rate at data input f

= 48 kHz; double speed

6.144

Mbits

sys

system clock frequency

6.4

18.432

MHz

full scale temperature
coefficient at analog
outputs (VOL and VOR)

100

amb

operating ambient
temperature

+85

1995 Dec 08

Philips Semiconductors

Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

TDA1305T

PINNING

SYMBOL

PIN

DESCRIPTION

DDA

analog supply voltage

SSA

analog ground

TEST1

test input; pin should be connected
to ground (internal pull-down
resistor)

BCK

bit clock input

word select input

DATA

data input

CLKS1

clock selection 1 input

CLKS2

clock selection 2 input

SSD

digital ground

DDD

digital supply voltage

TEST2

test input; pin should be connected
to ground (internal pull-down
resistor)

SYSCLKI

system clock input

n.c.

not connected (this pin should be left
open-circuit)

n.c.

not connected (this pin should be left
open-circuit)

SSD

digital ground

SYSCLKO

system clock output

DEEM1

de-emphasis on/off; f

DEEM

32 kHz,

44 kHz and 48 kHz

DEEM2

de-emphasis on/off; f

DEEM

32 kHz,

44 kHz and 48 kHz

MUSB

mute input (active LOW)

DSMB

double-speed mode input
(active LOW)

ATSB

12 dB attenuation input
(active LOW)

VOL

left channel output

FILTCL

capacitor for left channel 1st order
filter function should be connected
between pins 22 and 23

FILTCR

capacitor for right channel 1st order
filter function should be connected
between pins 25 and 24

VOR

right channel output

ref

internal reference voltage for output
channels (0.5V

)

SSO

operational amplifier ground

DDO

operational amplifier supply voltage

Fig.2 Pin configuration.

1995 Dec 08

Philips Semiconductors

Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

TDA1305T

FUNCTIONAL DESCRIPTION

The TDA1305T CMOS digital-to-analog bitstream
converter incorporates an up-sampling filter and noise
shaper which increase the oversampling rate of 1f

input

data to 96f

sys

= 192f

) or 128f

sys

= 256f

) in the

normal speed mode. In the double speed mode the
oversample rate of 1f

input data is increased to 48f

sys

= 384f

) or 64f

sys

= 256f

). This oversampling,

together with the 5-bit DAC, enables the filtering required
for waveform smoothing and out-of-band noise reduction
to be achieved by simple 1st order analog post filtering.

System clock and data input format

The TDA1305T accommodates slave mode only, this
means that in all applications the system devices must

provide a system clock of 256 or 384f

= 32, 44.1 or

48 kHz). The system frequency is selectable by means of
pin CLKS1 and pin CLKS2. The SYSCLKO output (pin 16)
provides the system clock for external use.

The TDA1305T supports the following data input modes:

S-bus with data word lengths of up to 20 bits

(at f

sys

= 256f

LSB fixed serial format with data word lengths of 16, 18
and 20 bits (at f

sys

= 384f

). As this format idles on the

MSB it is necessary to know how many bits are being
transmitted.

The input format is shown in Fig.3. Left and right
data-channel words are time-multiplexed.

Table 1

Data input format and system clock.

Note

1. Number of clock pulses within half an audio sample.

TEST1

CLKS1

CLKS2

DATA INPUT FORMAT

SYSTEM

CLOCK

DATA

CLOCK

(1)

SYSCLKO

S up to 20 bits

256f

>20

256f

LSB fixed 16 bits

384f

LSB fixed 18 bits

384f

LSB fixed 20 bits

384f

reserved

LSB fixed 16 bits

384f

LSB fixed 18 bits

384f

LSB fixed 20 bits

384f

1995 Dec 08

Philips Semiconductors

Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

TDA1305T

Mute

Soft mute is controlled by the MUSB at pin 9. When the
input is active LOW the value of the samples is decreased
smoothly to zero following a cosine curve. To step down
the value of the data 32 coefficients are used, each one
being used 31 times before stepping onto the next. When
MUTE is released (pin 19 = HIGH), the samples are
returned to the full level again following a cosine curve with
the same coefficients being used in the reverse order.
Mute is synchronized to prevent operation in the middle of
a word.

De-emphasis

A digital de-emphasis is implemented for three sample
rates (32, 44.1 and 48 kHz). By selecting DEEM1 and
DEEM2 de-emphasis can be applied by means of a FIR
filter. Time constants of the de-emphasis are 50

s and

s. De-emphasis is synchronized to prevent operation

in the middle of a word. The de-emphasis deviation from
ideal 50

s and 15

s de-emphasis is given in Table 4.

Table 2

De-emphasis.

Attenuation

Attenuation is controlled by the ATSB input (pin 21). When
the input is active LOW the sample is multiplied by a
coefficient that provides 12 dB attenuation. If the input is
HIGH the multiplication factor is 1. Attenuation is
synchronized to prevent operation in the middle of a word.

Double-speed mode

Double speed is controlled by the DSMB input (pin 20).
When the input is active LOW the device operates in the
double-speed mode.

DEEM1

DEEM2

CONDITION

de-emphasis disabled

de-emphasis for f

= 32 kHz

de-emphasis for f

= 4.1 kHz

de-emphasis for f

= 48 kHz

Oversampling filter (normal-speed mode)

In the normal-speed mode the oversampling filter
consists of:

A 91st order half-band low-pass FIR filter which
increases the oversampling rate from 1 time to 2 times.

A 23rd order quarter band low-pass FIR filter which
increases the oversampling rate from 2 times to 8 times.

A linear interpolation section which increases the
oversampling rate to 16 times. This removes the
spectral components around 8f

A sample-and-hold section which provides another
6 times oversampling to 96 times. The zero-order hold
characteristic of this sample-and-hold section plus the
1st order analog filtering remove the spectral
components around 16f

Pass-band ripple and stop-band attenuation for
normal-speed are given in Table 3.

Oversampling filter (double-speed mode)

In the double-speed mode the oversampling filter
consists of:

A 51st order half-band low-pass FIR filter which
increases the oversampling rate from 1 time to 2 times.

A 7th order half-band low-pass FIR filter which
increases the oversampling rate from 2 times to 4 times.

A linear interpolation section which increases the
oversampling rate to 8 times. This removes the spectral
components around 4f

A sample-and-hold section which provides another
6 times oversampling to 48 times. The zero-order hold
characteristic of this sample-and-hold section plus the
1st order analog filtering remove the spectral
components around 8f

Pass-band ripple and stop-band attenuation for
double-speed are given in Table 3.

1995 Dec 08

Philips Semiconductors

Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

TDA1305T

Noise shaper

In the normal speed mode the 2nd order digital noise
shaper operates at 96f

sys

= 384f

) or 128f

sys

= 256f

). The digital noise shaper operates at 48f

sys

= 384f

) or 64f

sys

= 256f

) in double-speed mode. It

shifts in-band quantization noise to frequencies well above
the audio band. This noise shaping technique used in
combination with a special data coding enables extremely
high signal-to-noise ratios to be achieved. The noise
shaper outputs a 5-bit pulse duration modulation (PDM)
bitstream signal to the DAC.

Continuous calibration DAC

The dual 5-bit DAC uses the continuous calibration
technique. This method, based on charge storage,
involves exact duplication of a single reference current
source. In the TDA1305T, 32 such current sources plus
1 spare source are continuously calibrated. The spare
source is included to allow continuous converter operation.

The DAC receives a 5-bit data bitstream from the noise
shaper. This data is then converted so that only small
currents are switched to the output during digital silence

(input 00000H). Using this technique extremely high
signal-to-noise performance is achieved.

Operational amplifiers

High precision, low-noise amplifiers together with the
internal conversion resistors R

CONV1

and R

CONV2

convert

the converter output current to a voltage capable of driving
a line output. This voltage is available at VOL and VOR
(1.5 V RMS typical).

Connecting external capacitors CEXT1 and CEXT2
between FILTCL and VOL and between FILTCR and VOR
respectively provides the required 1st order post filtering
for the left and right channels (see Fig.1). The
combinations of R

CONV1

with CEXT1 and R

CONV2

with

CEXT2 determine the 1st order fall-off frequencies.

Internal reference circuitry

Internal reference circuitry ensures that the output voltage
signal is proportional to the supply voltage, thereby
maintaining maximum dynamic range for supply voltages
from 3.4 to 5.5 V and making the circuit also suitable for
battery-powered applications.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. Human body model; C = 100 pF, R = 1500

, V = 2000 V, 3 pulses positive and 3 pulses negative.

2. Machine model; C = 200 pF, R = 10

, L = 0.5

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

DDD

digital supply voltage

7.0

DDA

analog supply voltage

7.0

DDO

operational amplifier supply voltage

7.0

xtal

maximum crystal temperature

+150

stg

storage temperature

+150

amb

ambient operating temperature

+85

electrostatic handling

note 1

2000

+2000

note 2

200

+200

SYMBOL

PARAMETER

VALUE

UNIT

th j-a

thermal resistance from junction to ambient in free air

K/W

1995 Dec 08

Philips Semiconductors

Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

TDA1305T

QUALITY SPECIFICATION

In accordance with

"SNW-FQ-611E". The number of this quality specification can be found in the "Quality Reference

Handbook". The handbook can be ordered using the code 9398 510 63011.

DIGITAL CHARACTERISTICS

= 3.4 to 5.5 V; V

= 0 V; T

amb

40 to +85

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

DDD

digital supply voltage

note 1

3.4

5.0

5.5

DDD

digital supply current

DDD

= 5 V;

at code 00000H

DDA

analog supply voltage

note 1

3.4

5.0

5.5

DDA

analog supply current

DDA

= 5 V;

at code 00000H

5.5

DDO

operational amplifier supply
voltage

note 1

3.4

5.0

5.5

DDO

operational amplifier supply
current

DDO

= 5 V;

at code 00000H

6.5

ripple rejection to V

DDA

note 2

System clock input

sys

system frequency

sys

= 384f

9.6

16.93

18.4

MHz

sys

= 256f

6.4

11.29

12.28

MHz

LOW level input voltage

note 3

0.5

0.2V

HIGH level input voltage

note 3

0.8V

+ 0.5

input leakage current

note 4

input capacitance

clock cycle time

sys

= 384f

104

59.1

54.2

sys

= 256f

156

88.6

81.3

Digital inputs; WS, BCK, DATA, DSMB, MUSB, DEEM1, DEEM2, ATSB, CLKS1, CLKS2, TEST1 and TEST2

LOW level input voltage

note 3

0.5

0.3V

HIGH level input voltage

note 3

0.7V

+ 0.5

input leakage current

note 4

input capacitance

Digital output; CDEC

LOW level output voltage

= 0.4 mA

0.5

HIGH level output voltage

0.2 mA

0.5

output rise time

note 5

output fall time

note 5

load capacitance

1995 Dec 08

Philips Semiconductors

Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

TDA1305T

Notes

1. All V

and V

pins must be connected externally to the same supply.

2. V

ripple

= 1% of supply voltage; f

ripple

= 100 Hz. Ripple rejection RR to V

DDA

is dependent on the value of the external

capacitor (C

EXT3

in Fig.1) connected to V

ref

. The value here assumes that C

EXT3

= 1

3. Minimum V

and maximum V

are peak values to allow for transients.

4. I

LImni

measured at V

= 0 V; I

LImax

measured at V

= 5.5 V.

5. Reference levels = 10% and 90%.

ANALOG CHARACTERISTICS

= V

DDA

= V

DDO

= 5 V; V

= 0 V; T

amb

= 25

C; unless otherwise specified.

Serial input data timing (see Fig.4)

BCK

bit-clock input (data input
rate) frequency

sys

= 384f

48f

MHz

sys

= 256f

64f

MHz

word select input frequency

normal speed

44.1

kHz

double speed

88.2

kHz

rise time

fall time

bit clock time HIGH

bit clock time LOW

data set-up time

data hold time

suWS

word select set-up time

hWS

word select hold time

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Reference values

ref

reference voltage level

2.45

2.5

2.55

CONV

current-to-voltage
conversion resistor

1.6

2.2

2.8

Analog outputs

RES

resolution

bit

FS(rms)

full-scale output voltage
(pins 23 and 25)
(RMS value)

1.425

1.5

1.575

OFF

output voltage DC offset with
respect to reference voltage
level V

ref

full scale temperature
coefficient

100

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1995 Dec 08

Philips Semiconductors

Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

TDA1305T

Notes

1. Measured with a 1 kHz, 0 dB, 18-bit sine wave generated at a sampling rate of 48 kHz. The (THD + N)/S measured

over a bandwidth of 20 Hz to 20 kHz.

2. Measured with a 1 kHz, -60 dB, 18-bit sine wave generated at a sampling rate of 48 kHz. The (THD + N)/S measured

over a bandwidth of 20 Hz to 20 kHz. For 16-bit input signals, the performance is limited to the theoretical maximum.

3. Measured with a 1 kHz, -60 dB, 18-bit sine wave generated at a sampling rate of 48 kHz. The (THD + N)/S measured

over a bandwidth of 20 Hz to 20 kHz and filtered with a A-weighted characteristic. For 16-bit input signals, the
performance is limited to the theoretical maximum.

4. Measured with a sine wave from 20 Hz to 20 kHz generated at a sampling rate of 48 kHz. The (THD + N)/S

measured over a bandwidth of 20 Hz to 20 kHz.

TEST AND APPLICATION INFORMATION

Filter characteristics (theoretical values)

Table 3

Normal speed filter characteristics.

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

at 0 dB input level;
note 1

0.003

0.009

60 dB input level;

note 2

0.63

1.0

60 dB input level;

A-weighted; note 3

0.5

at 0 dB input level;
(20 Hz to 20 kHz);
note 4

0.003

S/N

signal-to-noise ratio at
bipolar zero

A weighted;
at code (00000H)

100

108

channel separation

100

unbalance between outputs

0.2

0.3

dynamic output impedance

output load resistance

output load capacitance

200

ITEM

SAMPLE FREQUENCY

RANGE

CONDITIONS

CHARACTERISTICS

Pass band

44.1 kHz

0 to 20 kHz

0.025 dB

32 kHz

14.5 to 15 kHz

0.15 dB (min.)

Stop band

44.1 kHz

24.1 to 150 kHz

typical

60 dB (max.)

worst case

57 dB (max.)

150 kHz to infinity

typical

57 dB (max.)

worst case

47 dB (max.)

32 kHz

17 to 17.5 kHz

40 dB (max.)

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1995 Dec 08

Philips Semiconductors

Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

TDA1305T

A typical application diagram is illustrated in Fig.5. The left
and right channel outputs can drive a line output directly.
The series inductor (L) in the digital supply line, though not
strictly necessary, helps to reduce crosstalk between the
digital and analog circuits.

In Fig.6 measurements were taken with an 18-bit sine
wave generated at a sampling rate of 48 kHz. The
(THD + N)/S was measured over a bandwidth of
20 Hz to 20 kHz. The graph was constructed from average

measurement values of a small amount of engineering
samples. No guarantee for typical values is implied.

In Fig.6 measurements were taken with an 18-bit sine
wave generated at a sampling rate of 48 kHz. The
(THD + N)/S was measured over a bandwidth of
20 Hz to 20 kHz and filtered with A-weighted
characteristics. The graph was constructed from average
measurement values of a small amount of engineering
samples. No guarantee for typical values is implied.

Fig.6 Total harmonic distortion as a function of signal frequency.

(1) Level =

60 dB.

(2) Level = 0 dB.

1995 Dec 08

Philips Semiconductors

Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

TDA1305T

PACKAGE OUTLINE

UNIT

max.

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

inches

2.65

0.30
0.10

2.45
2.25

0.49
0.36

0.32
0.23

18.1
17.7

7.6
7.4

1.27

10.65
10.00

1.1
1.0

0.9
0.4

8
0

0.25

0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

1.1
0.4

SOT136-1

detail X

(A )

0.25

075E06

MS-013AE

pin 1 index

0.10

0.012
0.004

0.096
0.089

0.019
0.014

0.013
0.009

0.71
0.69

0.30
0.29

0.050

1.4

0.055

0.419
0.394

0.043
0.039

0.035
0.016

0.01

0.25

0.01

0.004

0.043
0.016

0.01

10 mm

scale

SO28: plastic small outline package; 28 leads; body width 7.5 mm

SOT136-1

95-01-24
97-05-22

1995 Dec 08

Philips Semiconductors

Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

TDA1305T

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all SO
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45

Wave soldering

Wave soldering techniques can be used for all SO
packages if the following conditions are observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

The longitudinal axis of the package footprint must be
parallel to the solder flow.

The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

1995 Dec 08

Philips Semiconductors

Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

TDA1305T

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Philips Semiconductors a worldwide company

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Fax. (021)577035/5874546

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Tel. (0 212)279 27 70, Fax. (0212)282 67 07

Ukraine: Philips UKRAINE, 2A Akademika Koroleva str., Office 165,

252148 KIEV, Tel. 380-44-4760297, Fax. 380-44-4766991

United Kingdom: Philips Semiconductors LTD.,

276 Bath Road, Hayes, MIDDLESEX UB3 5BX,
Tel. (0181)730-5000, Fax. (0181)754-8421

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Uruguay: Coronel Mora 433, MONTEVIDEO,

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Internet: http://www.semiconductors.philips.com/ps/

For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-2724825

SCD47

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The information presented in this document does not form part of any quotation
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other industrial or intellectual property rights.

Printed in The Netherlands

513061/50/02/pp20

Date of release: 1995 Dec 08

Document order number:

9397 750 00517

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