1999 Aug 20

Philips Semiconductors

Product specification

QPSK receiver

TDA8051

FEATURES

High operating input sensitivity

Gain controlled amplifier

PLL controlled carrier frequency

Low crosstalk between I and Q channel outputs

3-wire transmission bus

5 V supply voltage.

APPLICATIONS

BPSK/QPSK demodulation.

GENERAL DESCRIPTION

This TDA8051 is a monolithic bipolar IC intended for
Quadrature Phase Shift Key (QPSK) demodulation. It
includes:

Low noise RF and gain controlled amplifier

Two matched mixers

Symmetrical Voltage Controlled Oscillator (VCO) with
0 to 90

signal generator whose frequency is controlled

by an integrated Phase Lock Loop (PLL) circuit.

Two matched amplifiers for output base-band active
filtering and output buffers

The gain control is produced by output level detection
compared with an external pre-fixed reference. The PLL
consists of:

Divide by four preamplifier

12-bit programmable main divider

Crystal oscillator with 8-bit programmable reference
divider

Phase/frequency detector combined with charge pump
to drive tuning amplifier

30 V output

QUICK REFERENCE DATA
All AC units are RMS values unless otherwise specified.

ORDERING INFORMATION

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

supply voltage range

4.75

5.00

5.25

I(LNA)

input carrier frequency at LNA input

130

MHz

I(LNA)

input level at LNA input

dBmV

I-Q

phase error between I and Q channels

deg

I-Q

gain error between I and Q channels

CT(I-Q)

crosstalk between I and Q channels

dBc

IM3

3rd-order intermodulation distortion in
I and Q channels (0 dBmV at LNA_IN)

dBc

voltage output on pin I_OUT and Q_OUT

dBmV

step

step at output

250

kHz

xtal

crystal frequency

MHz

amb

operating ambient temperature

TYPE NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA8751T

SO32

plastic small outline package; 32 leads; body width 7.5 mm

SOT287-1

1999 Aug 20

Philips Semiconductors

Product specification

QPSK receiver

TDA8051

PINNING

SYMBOL

PIN

DESCRIPTION

I_OUT

I data buffered balanced output

I_OUTC

I data buffered balanced output

I_OUT2

I data filtered output

I_IN1

input to active filter amplifier for
I data

I_OUT1

I data raw output

A1VCC

analog supply voltage 1

DEMOD_IN

demodulator RF input

LNA_OUT

low noise amplifier RF output

LNA_IN

low noise amplifier RF input

A1GND

analog ground 1

AGC_IN

AGC control voltage input

OSC_IN

oscillator input

DVCC

digital supply voltage

CLK

3-wire bus serial control clock

DATA

3-wire bus serial control data

3-wire bus serial control enable
(active LOW)

TEST

not connected

charge pump output for PLL loop
filter

TUNE

tuning voltage output

DGND

digital ground

TKB

VCO tank circuit input

TKA

VCO tank circuit input

A2VCC

analog supply voltage 2

A2GND

analog ground 2

A3VCC

analog supply voltage 3

OUTGND

output amplifiers ground

OUTVCC

output amplifiers supply voltage

Q_OUT1

Q data raw output

Q_IN1

input to active filter amplifier for
Q data

Q_OUT2

Q data filtered output

Q_OUTC

Q data buffered balanced output

Q_OUT

Q data buffered balanced output

handbook, halfpage

TDA8051

FCE171

I_OUT

I_OUTC

I_OUT2

I_IN1

I_OUT1

A1VCC

DEMOD_IN

LNA_OUT

LNA_IN

A1GND

AGC_IN

OSC_IN

DVCC

CLK

Q_OUT

Q_OUTC

Q_OUT2

Q_IN1

OUTVCC

OUTGND

Q_OUT1

A3VCC

A2GND

A2VCC

TKA

TKB

DGND

TUNE

DATA

TEST

Fig.2 Pin configuration.

1999 Aug 20

Philips Semiconductors

Product specification

QPSK receiver

TDA8051

FUNCTIONAL DESCRIPTION

The QPSK modulated signal is applied to the input as an
asymmetrical RF signal in the bandwidth 44 to 130 MHz.
The spectrum extension to this waveform must be limited
by a band-pass filter superseding the IC.

The RF input is either the LNA input, if the level is

30 to 0 dBmVrms, or the DEMOD input if the level is

20 to +10 dBmVrms. The amplified RF signal is then

mixed with two clocks in quadrature to provide the
base-band demodulated In-phase (I) and Quad-phase (Q)
signals.

The VCO operates at twice the RF carrier frequency in the
bandwidth 88 - 260 MHz (one octave), therefore the
0 to 90

clocks are generated by a divider by 2.

The VCO frequency can be programmed by an integrated
PLL that tunes the external LC tank circuit.

The raw I and Q generated signals contain spurious
spikes, therefore each signal is passed through a third
order active low-pass filter (RC cell + Sallen-Key
structure), whose cut-off frequency is set by external
components. The filtered I and Q data signals are then
amplified to provide balanced buffer outputs.

The data sent to the PLL is loaded in bursts, framed by
signal EN. Programming clock edges, together with their
relevant data bits, are ignored until EN becomes active
(LOW). The internal latches are updated with the latest
programming data when EN returns to inactive (HIGH).
The last 14 bits only are retained within the programming
register. No check is made on the number of clock pulses
received while programming is enabled. An active clock
edge causing a shift of the data bits is generated when
EN goes HIGH while CLOCK is still LOW. The main divider
ratio and the reference divider ratio are provided via the
serial bus (see Table 1).

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).

HANDLING

HBM ESD: The IC pins withstand 2 kV except pin 26 (1750 V).

MM ESD: The IC pins withstand 100 V except pins 2 and 31 (75 V).

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

supply voltage

0.3

6.0

(max)

maximum voltage on all pins except pin 9 (5 V)

0.3

maximum short circuit duration on outputs

stg

storage temperature

+150

j(max)

maximum junction temperature

150

amb

operating ambient temperature

CC(tune)

tuning voltage supply

0.3

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th(j-a)

thermal resistance from junction to ambient

in free air

K/W

1999 Aug 20

Philips Semiconductors

Product specification

QPSK receiver

TDA8051

CHARACTERISTICS
Measured in application circuit with the following conditions: V

= 5 V; T

amb

= 25

C. All AC units are RMS values,

unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

CCA1

analog supply voltage

4.75

5.25

CCA1

analog supply current

CCA2

analog supply voltage

4.75

5.25

CCA2

analog supply current

CCA3

analog supply voltage

4.75

5.25

CCA3

analog supply current

cc(o)

output supply voltage

4.75

5.25

cc(o)

output supply current

CCD

digital supply voltage

4.75

5.25

CCD

digital supply current

CC(tune)

tuning supply voltage

Low noise amplifier: R

= 75

unless otherwise specified

I(DC)

DC input level

internally set

0.85

input level

dBmV

input carrier frequency

130

MHz

input resistance

input capacitance

2.5

LLNA

input return loss

LNA

noise figure

leak(LO)

LO leakage on pin at LNA_IN

= 140

860 MHz;

pin LNA_OUT connected to
DEMOD_IN

dBmV

LO/2

= 70

130 MHz;

pin LNA_OUT connected to
DEMOD_IN

dBmV

LNA

LNA gain

f = 100 MHz;
V

I(LNA)

= 0 dBmV

output level

+10

dBmV

output flatness

in 1 MHz bandwidth;
V

I(LNA)

= 0 dBmV

0.25

0.5

44 to 70 MHz;
V

I(LNA)

= 0 dBmV

0.50

70 to 130 MHz;
V

I(LNA)

= 0 dBmV

1.3

1.5

IM3

3rd-order intermodulation

2 carriers at +10 dBmV each

dBc

at pin LNA_IN

at 103 to 105 MHz

1999 Aug 20

Philips Semiconductors

Product specification

QPSK receiver

TDA8051

o(DC)

DC output level

1.3

output resistance

Quadrature demodulator: R

= 75

= 20 k

unless otherwise specified

I(DC)

DC input level

internally set

input level

+10

dBmV

input carrier frequency

130

MHz

input resistance

input capacitance

2.5

input Return Loss

o(I-Q)

output level on pin I_OUT1 or
Q_OUT1

dBmV

o(I-Q)

output 3 dB bandwidth

LO = 200 MHz;
RF = 100 to 130 MHz

MHz

C/N

carrier to noise ratio at
500 kHz on pin at I_OUT1 or
Q_OUT1

20 dBmV;

o(I and Q)

= 22 dBmV

dBc/Hz

= 10 dBmV;

o(I and Q)

= 22 dBmV

dBc/Hz

leak(LO)

LO leakage on pin
DEMOD_IN

= 140 to 260 MHz;

LO/2

= 70 to 130 MHz

dBmV

AGC(r)

AGC range

= 200 MHz;

= 100.25 MHz at

20 to +10 dBmV;

= 250 kHz at 22 dBmV

AGC(s)

AGC slope maximum

= 200 MHz;

= 100.25 MHz at

20 to +10 dBmV;

= 250 kHz at 22 dBmV

dB/V

AGC

gain control voltage at
AGC_IN

10% V

CCA

90% V

CCA

max

max. conversion gain

= 260 MHz;

= 130.25 MHz at

20 dBmV; V

AGC

= 4.5 V

min

min. conversion gain

= 140 MHz;

= 70.25 MHz at

10 dBmV V

AGC

= 0.5 V

I-Q

phase error between I and Q
channels

= 140 to 260 MHz;

= 70.25 to 130.25 MHz;

= 250 kHz at 22 dBmV

over specified input range

deg

I-Q

gain error between I and Q
channels

= 140 to 260 MHz;

= 70.25 to 130.25 MHz;

= 250 kHz at 22 dBmV

over specified input range

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1999 Aug 20

Philips Semiconductors

Product specification

QPSK receiver

TDA8051

I-Q

phase error between I and Q
channels

= 88 to 140 MHz;

= 44.25 to 70.25 MHz;

= 250 kHz at 22 dBmV

over specified input range

deg

I-Q

gain error between I and Q
channels

= 88 to 140 MHz;

= 44.25 to 70.25 MHz;

= 250 kHz at 22 dBmV

over specified input range

IM3

3rd-order intermodulation in
I and Q channels

see Fig.3

dBc

IM2

2nd-order intermodulation in
I and Q channels

see Fig.3

dBc

AMREJ

AM rejection at I and Q
channels

guaranteed by design;
see Fig.4

dBc

o(I/Q)

output flatness at I and Q
outputs

in 1 MHz bandwidth

0.25

f = 40 to 70 MHz

f = 70 to 130 MHz

o(DC)

DC output level

2.5

output resistance

400

Output section: R

= 400

= 4 k

/R on pin I_OUT2 or Q_OUT2 = 20 k

unless otherwise specified

I(DC)

DC input voltage

3.6

input level

dBmV

input resistance

17.5

input capacitance

0.4

gain from
I-Q_IN1 to I-Q_OUT2

= 1 MHz at 22 dBmV

3.8

o(I-Q_out2)

output flatness on
pins I_OUT2 and Q_OUT2

= 0 to 1.5 MHz

0.25

= 0 to 6 MHz at 22 dBmV

input

o(flt)

DC output level at filter output

2.6

output resistance

f < 20 MHz

250

2nd harmonic

= 1 MHz at 48 dBmV

output

dBc

3rd harmonic

= 1 MHz at 48 dBmV

output

dBc

IM3

3rd-order intermodulation at
pins I_OUT and Q_OUT

see Fig.5

dBc

CT(I-Q)

crosstalk between I and Q
channels

f = 5 MHz; see Fig.6

dBc

output noise power at
500 kHz from carrier

see Fig.7

dBmv/Hz

I-Q

gain from
I-Q_IN1 to I-Q_OUT

= 1 MHz at 22 dBmV

input

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1999 Aug 20

Philips Semiconductors

Product specification

QPSK receiver

TDA8051

1(I-Q)

DC output level on
pin I-Q_OUT

3.1

o(dif)

output differential resistance

460

Overall: R

= 75

= 4 k

unless otherwise specified

voltage output on
pins I_OUT and Q_OUT

see Fig.8

dBmV

lev

LO level on
pins I_OUT and Q_OUT

see Fig.8

dBc

spurious emission on
pins I_OUT and Q_OUT

f = 0 to 5 MHz; see Fig.8

dBc

I-Q

gain error on
pins I_OUT and Q_OUT

see Fig.8

AMR

AM rejection in I and Q
channels

guaranteed by design; see
Fig.9

dBc

IM3

3rd-order intermodulation

guaranteed by design; see
Fig.10

dBc

Voltage Controlled Oscillator (VCO)

vco(min)

min. oscillation frequency

note 1

MHz

vco(max)

max. oscillation frequency

note 1

260

MHz

(osc)

oscillator phase noise

at 10 kHz

dBc/Hz

at 100 kHz

dBc/Hz

Phase Locked Loop (PLL)

Step

frequency step size

at pin VCO output

100

500

kHz

fixed reference divider ratio

RDR

programmable reference
divider ratio

programmable fix main divider
ratio

NDR

main divider ratio

128

2600

(CP)

charge pump current

300

Crystal oscillator

xtal

crystal frequency

xtal

= 25 to 200

MHz

crystal oscillator input
impedance (absolute value)

xtal

= 4 MHz

600

120
0

I(DC)

DC input level

2.9

input level

mVrms

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1999 Aug 20

Philips Semiconductors

Product specification

QPSK receiver

TDA8051

Notes

1. The frequency range of the receiver is 44 to 130 MHz. The local oscillator (LO) operates at twice the output

frequency (88 to 260 MHz). Frequency control by varicap diodes allows a variation over one octave.

2. Crystal oscillator. The crystal oscillator uses a 4, 2 or 1 MHz crystal in series with a capacitor. The crystal is parallel

resonant with load capacitance of 18 to 20 pF. Connection to V

is preferred but can also be to GND.

Note to characteristics

3-wire bus

input Low level

guaranteed by design

0.8

input High level

guaranteed by design

2.4

clk

clock frequency

guaranteed by design

330

kHz

input data to CLK set-up time

guaranteed by design

input data to CLK hold time

guaranteed by design

d(strt)

delay to rising clock edge

guaranteed by design

d(stp)

delay from last clock edge

guaranteed by design

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

handbook, full pagewidth

FCE172

f (MHz)

105

maximum

input

level

10 dB above max. input level

= 20 dBmVrms each tone

103

f (MHz)

nominal

output level

= 22 dBmVrms

each tone

10 dB = 32 dBmVrms each tone

IM3 IM2

105 MHz

DEMOD_IN

0¡ 90¡

5 V

103 MHz

I_OUT1

Q_OUT1

VCO 200 MHz

Fig.3 IM2 and IM3 measurement of the demodulator.

1999

Aug

Philips Semiconductors

Product specification

QPSK receiv

TD
A8051

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APPLICA

TION INFORMA

TION

handbook, full pagewidth

FCE113

TDA8051

1/NDR

CMP

I DATA BUFFERED

BALANCED OUTPUT

Q DATA BUFFERED

BALANCED OUTPUT

BUS

1/RDR

1/2

0¡

90¡

1/4

I CHANNEL

FILTERING

Q CHANNEL
FILTERING

CHARGE

PUMP

A1VCC

OUTVCC

OUTGND

A3VCC

A2GND

A2VCC

TEST
n.c.

TKA

TKB

Voltage

Controlled

Oscillator

DGND

30 V

A1GND

AGC_IN

OSC_IN

LNA_IN

I_OUT1

I_OUT2

I_OUTC

I_OUT

I_IN1

Q_OUT1

TUNE

Q_OUT2

Q_OUTC

Q_OUT

Q_IN1

DEMOD_IN

LNA_OUT

DVCC

CLK

DATA

3-WIRE BUS

RF INPUT

Fig.12 Application diagram.

1999 Aug 20

Philips Semiconductors

Product specification

QPSK receiver

TDA8051

SOLDERING

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250

C. The top-surface temperature of the

packages should preferable be kept below 230

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

For packages with leads on four sides, the footprint must
be placed at a 45

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

1999 Aug 20

Philips Semiconductors

Product specification

QPSK receiver

TDA8051

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PACKAGE

SOLDERING METHOD

WAVE

REFLOW

(1)

HLQFP, HSQFP, HSOP, SMS

not suitable

(2)

suitable

PLCC

(3)

, SO

suitable

LQFP, QFP, TQFP

not recommended

(3)(4)

suitable

SQFP

not suitable

suitable

SSOP, TSSOP, VSO

not recommended

(5)

suitable

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

1999

Philips Semiconductors a worldwide company

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

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Belgium: see The Netherlands

Brazil: see South America

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Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811

Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341

Pakistan: see Singapore

Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327

Portugal: see Spain

Romania: see Italy

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382

Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777

Printed in The Netherlands

545004/25/02/pp

Date of release:

1999 Aug 20

Document order number:

9397 750 04691

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA8051T

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA8051T