2004 Dec 02

Philips Semiconductors

Product specification

Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer

TDA8261TW

FEATURES

Direct conversion Quadrature Phase Shift Keying
(QPSK) and 8PSK demodulation (Zero-IF)

950 to 2175 MHz frequency range

High-level asymmetrical RF input

0 to 50 dB variable gain on RF input

Loop-controlled 0

to 90

phase shifter

High AGC linearity (<1 dB per bit with an 8-bit DAC),
AGC between 0 and 3 V

External baseband filters for In-phase (I) and
Quadrature (Q) signal paths

C-bus controlled PLL frequency synthesizer

Low phase noise

Operation from a 4 MHz crystal (allowing the use of an
SMD crystal)

Five frequency steps from 125 kHz to 2 MHz

Crystal frequency output to drive demodulator IC

Compatible with 5, 3.3 and 2.5 V I

C-bus

Fully compatible and easy to interface with digital
satellite demodulators of the Philips Semiconductors
family

5 V DC supply voltage

32-pin high heat-dissipation package.

APPLICATIONS

Direct Broadcasting Satellite (DBS) QPSK
demodulation

Digital Video Broadcasting (DVB) QPSK demodulation

BS digital 8PSK demodulation.

GENERAL DESCRIPTION

The direct conversion QPSK demodulator is the front-end
receiver dedicated to digital TV broadcasting, satisfying
both DVB and DBS TV standards. The wide range
oscillator (from 950 to 2175 MHz) covers the American,
European and Asian satellite bands, as well as the
Satellite Master Antennae (SMA) TV US standard.

The Zero-IF concept discards traditional IF filtering and
intermediate conversion techniques. It also simplifies the
signal path.

Optimum signal level is guaranteed by gain controlled
amplifiers in the RF path. The 0 to 50 dB variable gain is
controlled by the signal returned from the Satellite
Demodulator and Decoder (SDD) and applied to
pin AGCIN.

The PLL synthesizer is built on a dual-loop concept. The
first loop controls a fully integrated L-band oscillator, using
the LC VCO as a reference which runs at a quarter of the
synthesized frequency.

The second loop controls the tuning voltage of the VCO
and improves the phase noise of the carrier within the loop
bandwidth. The step size is equal to the comparison
frequency. The input of the main divider of the PLL
synthesizer is connected internally to the VCO output.

The comparison frequency of the second loop is obtained
from an oscillator driven by an external 4 MHz crystal. The
4 MHz output available at pin XTOUT may be used to drive
the crystal inputs of the SDD, saving an additional crystal
in the application.

Both the divided and the comparison frequencies of the
second loop are compared in a fast phase detector which
drives the charge pump. The TDA8261TW includes a loop
amplifier with an internal high-voltage transistor to drive an
external 33 V tuning voltage.

Control data is entered via the I

C-bus. The I

C-bus

voltage can be 5, 3.3 or 2.5 V, allowing compatibility with
most of the existing microcontrollers.

A 5-byte frame is required to address the device and to
program the main divider ratio, the reference divider ratio,
the charge pump current and the operating mode.

A flag is set when the loop is `in-lock'. This flag can be read
during read operations, as well as the Power-On Reset
(POR) flag.

The device has four selectable I

C-bus addresses. The

selection is done by applying a specific voltage to pin AS.
This feature gives the possibility to use up to four
TDA8261TW ICs in the same system.

2004 Dec 02

Philips Semiconductors

Product specification

Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer

TDA8261TW

Performance summary

TDA8261TW performance:

Noise figure at maximum gain = +18 dB

High linearity; IP2 = +19 dBm and IP3 = +14 dBm

Low phase noise on baseband outputs:

78 dBc/Hz

offset

= 1 and 10 kHz; f

COMP

= 1 MHz)

0 to 50 dB variable gain with AGC control

AGC linearity <1 dB/bit with an 8-bit DAC

Maximum I-to-Q amplitude mismatch = 1 dB

Maximum I-to-Q phase mismatch = 3

Signal rates from 1 to 45 Msymbol/s (depending on the
external filter).

System performance, for example, in a tuner application
with the TDA8261TW placed after a low-cost discrete
LNA:

Noise figure at maximum gain = 8 dB

High linearity; IP2 = 15 dBm and IP3 = 5 dBm

0 to 50 dB variable gain with AGC control.

Specification limitation

Please note that this data sheet applies to versions C2 and
above only, it does not apply to version C1. For further
information, please contact your Philips Semiconductors
representative.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

supply voltage

4.75

5.0

5.25

supply current

130

o(p-p)

output voltage
(peak-to-peak value)

750

quadrature error

deg

osc

oscillator frequency

950

2175

MHz

phase noise on baseband
outputs

offset

= 1 and 10 kHz;

COMP

= 1 MHz with

appropriate loop filter and
charge pump

dBc/Hz

dynamic range of voltage gain from pins RFA or RFB to

pins IBBOUT or QBBOUT

XTOUT(p-p)

crystal oscillator output
voltage on pin XTOUT
(peak-to-peak value)

T2 = 1; T1 = 0; T0 = 0;
driving a load of
C

= 10 pF; R

= 1 M

500

650

amb

ambient temperature

+85

TYPE NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA8261TW

HTSSOP32

plastic, thermal enhanced thin shrink small outline package;
32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad

SOT549-3

2004 Dec 02

Philips Semiconductors

Product specification

Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer

TDA8261TW

BLOCK DIAGRAM

handbook, full pagewidth

AGC

CONTROL

VCO

fDIV

fXTAL

fCOMP

FAST PHASE/

FREQUENCY

COMPARATOR

DIGITAL PHASE

COMPARATOR

REFERENCE

DIVIDER

POWER-ON

RESET

CONTROL LOGIC

AND LATCH

OSCILLATOR

CHARGE PUMP

DIVIDE-BY-4

15-BIT DIVIDER

33 V

AMP

integrated
oscillator

C-BUS

TDA8261TW

MBL859

XTOUT

SDA

SCL

BVS

VCC(VCO)

TKA

TKB

VCOGND

BIASN2

IOUT

BBGND2

IBBIN

IBBOUT

XT1

XT2

VCC(PLL)

PLLGND

AGCIN

BIASN1

RFGND1

VCC(RF)

RFA

RFB

RFGND2

QOUT

BBGND1

QBBIN

VCC(BB)

QBBOUT

Fig.1 Block diagram.

2004 Dec 02

Philips Semiconductors

Product specification

Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer

TDA8261TW

PINNING

SYMBOL

PIN

DESCRIPTION

XT1

4 MHz crystal oscillator input 1

XT2

4 MHz crystal oscillator input 2

CC(PLL)

supply voltage for PLL circuit (5 V)

PLLGND

ground for PLL circuit

AGCIN

AGC input from satellite
demodulator and decoder

BIASN1

RF isolation input 1 (5 V)

RFGND1

ground 1 for RF circuit

CC(RF)

supply voltage for RF stage (5 V)

RFA

RF signal input A

RFB

RF signal input B

RFGND2

ground 2 for RF circuit

QOUT

quadrature output for external
filtering

BBGND1

ground 1 for baseband stage

QBBIN

quadrature baseband input after
external filtering

CC(BB)

supply voltage for baseband stage
(5 V)

QBBOUT

quadrature baseband output to
satellite demodulator and decoder

IBBOUT

in-phase baseband output to
satellite demodulator and decoder

BIASN2

RF isolation input 2 (5 V)

IBBIN

in-phase baseband input after
external filtering

BBGND2

ground 2 for baseband stage

IOUT

in-phase output for external filtering

VCOGND

ground for VCO circuit

TKB

VCO tank circuit input B

TKA

VCO tank circuit input A

CC(VCO)

supply voltage for VCO circuit (5 V)

BVS

bus voltage select input

tuning voltage output for VCO

charge pump output

address selection input

SCL

C-bus clock input

SDA

C-bus data input and output

XTOUT

4 MHz crystal oscillator output to
satellite demodulator and decoder

handbook, halfpage

TDA8261TW

MBL855

XT1

XT2

VCC(PLL)

PLLGND

AGCIN

BIASN1

RFGND1

VCC(RF)

RFA

RFB

RFGND2

QOUT

BBGND1

QBBIN

VCC(BB)

QBBOUT

XTOUT

SDA

SCL

BVS

VCC(VCO)

TKA

TKB

VCOGND

IOUT

BBGND2

IBBIN

BIASN2

IBBOUT

Fig.2 Pin configuration.

2004 Dec 02

Philips Semiconductors

Product specification

Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer

TDA8261TW

FUNCTIONAL DESCRIPTION

The TDA8261TW contains the core of the RF analog part
of a digital satellite receiver. The signal coming from the
Low Noise Block (LNB) is coupled through a Low Noise
Amplifier (LNA) to the RF inputs. The circuitry in the
TDA8261TW performs the Zero-IF quadrature frequency
conversion and the two in-phase (IBBOUT) and
quadrature (QBBOUT) output signals can be used directly
to feed a SDD circuit.

The relative phase of I and Q signals is measured on the
baseband outputs, when a sine wave unmodulated carrier
at f

+ 1 MHz is present at the RF input of the

TDA8261TW (see Fig.3).

The TDA8261TW has a gain controlled amplifier which is
controlled by the SDD.

An external VCO tank circuit is connected between
pins TKA and TKB. The main elements of the external
tank circuit are an SMD coil and a varactor diode. The
tuning voltage of 0 to 30 V covers the whole frequency
range from 237.5 to 543.75 MHz. The internal loop
controls a fully integrated VCO to cover the range
950 to 2175 MHz. The VCO provides both in-phase and
quadrature signals to drive the two mixers.

The TDA8261TW integrates all elements necessary to
control the varactor tuned oscillator except a 4 MHz crystal
and a loop filter. It includes a fast phase detector with high
comparison frequency to get the lowest phase noise level
in the local oscillator.

The f

DIV

output of the15-bit programmable divider passes

through the fast phase comparator where it is compared in
both phase and frequency with the comparison frequency
(f

COMP

). f

COMP

is derived from the signal present at the

pins XT1 and XT2 (f

XTAL

) divided-down by the reference

divider. The buffered XTOUT signal can drive the crystal
frequency input of the SDD, saving a crystal in the
application.

The output of the phase comparator drives the charge
pump and loop amplifier section. The loop amplifier
includes a high voltage transistor to handle the 30 V tuning
voltage at pin VT, this drives a variable capacitance diode
in the external circuit of the voltage controlled oscillator.
Pin CP is the output of the charge pump. The loop filter is
connected between pins CP and VT and the post-filter
section is connected between pin VT and the variable
capacitance diode.

For test and alignment purposes, it is possible to release
the tuning voltage output and apply an external voltage on
pin VT and to select the charge pump function to sink
current, source current or to be switched off.

handbook, halfpage

input

spectrum

output phase

output

signal

channel I

frequency

flo

fRF = flo

1 MHz

channel Q

MBL864

Fig.3 Relative phase of I and Q signals.

2004 Dec 02

Philips Semiconductors

Product specification

Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer

TDA8261TW

PROGRAMMING

Programming of the TDA8261TW is performed via the
I

C-bus. The read or write selection is made with bit R/W

(address LSB). The TDA8261TW fulfils the I

C-bus fast

mode, according to the Philips I

C-bus specification.

C-bus voltage

The I

C-bus lines SCL and SDA can be connected to an

C-bus system tied to either 2.5, 3.3 or 5.0 V, that will

allow direct connection to most of the existing
microcontrollers. The choice of the threshold voltage for
the I

C-bus lines is made with pin BVS that needs to be

connected to the supply voltage, to ground or needs an
open-circuit; see Table 1.

Table 1

C-bus voltage selection

C-bus write mode

C-bus write mode: bit R/W = 0; see Table 2.

After the transmission of the address (first byte), four data
bytes can be sent to fully program the TDA8261TW. The
bus transceiver has an auto-increment facility that permits
to program the TDA8261TW with a single transmission:
one address byte followed by four data bytes (PD1, PD2,
CD1 and CD2).

The TDA8261TW can be partly programmed provided that
the first data byte following the address is PD1 or CD1.
The first bit of the first data byte transmitted indicates
whether PD1 (first bit = 0) or CD1 (first bit = 1) will follow.
Until an I

C-bus STOP condition is sent by the controller,

additional data bytes can be entered without the need to
re-address the device. Each byte is loaded after the
corresponding 8th clock pulse. Programmable divider data
(contents of PD1 and PD2) becomes valid only after the
8th clock pulse of PD2, or after a STOP condition if only
PD1 needs to be programmed.

PIN BVS

C-BUS VOLTAGE

GND

2.5 V

Open-circuit

3.3 V

5 V

Table 2

C-bus write data format

Notes

1. MSB is transmitted first.

2. X = undefined.

3. Acknowledge bit (A).

BYTE

MSB

(1)

BITS

(2)

LSB

ACK

(3)

Programmable address

MA1

MA0

Programmable Divider 1 (PD1)

N14

N13

N12

N11

N10

Programmable Divider 2 (PD2)

Control Data 1 (CD1)

Control Data 2 (CD2)

2004 Dec 02

Philips Semiconductors

Product specification

Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer

TDA8261TW

ROGRAMMABLE ADDRESS

The programmable address bits MA1 and MA0 offer the
possibility of having up to four TDA8260TW devices in the
same system. The relationship between the voltage
applied on pin AS and the value of bits MA1 and MA0 is
given in Table 3.

Table 3

C-bus address selection

ROGRAMMABLE MAIN DIVIDER RATIO

Program bytes PD1 and PD2 contain the fifteen bits
N14 to N0 that set the main divider ratio. The ratio
N = N14

+ N13

+...+ N1

2 + N0.

PERATING AND TEST MODES

The mode of operation is set using bits T2, T1 and T0 in
control byte CD1; see Table 4.

Table 4

Mode selection

Note

1. Status at power-on: the tuning voltage output is

released and pin VT is in the high-impedance mode.

EFERENCE DIVIDER

Five reference divider ratios allow to adjust the
comparison frequency to different values, depending on
the compromise which has to be found between step size
and phase noise. The reference divider ratios and the
corresponding comparison frequencies are programmed
using bits R2, R1 and R0, as described in Table 5.

Table 5

Reference divider ratio

HARGE PUMP CURRENT

Four values of charge pump current can be chosen using
bits C1 and C0, according to Table 6.

Table 6

Typical charge pump current

MA1

MA0

0 to 0.1V

open-circuit

0.4V

to 0.6V

0.9V

to V

TEST MODE

XTOUT

normal operation

off

POR state = CP sink

(1)

XTAL

DIV

CP sink

XTAL

normal operation

XTAL

ref

CP off

XTAL

CP source

XTAL

DIVIDER RATIO

COMPARISON

FREQUENCY

2 MHz

1 MHz

500 kHz

not allowed

250 kHz

not allowed

125 kHz

(ABSOLUTE VALUE)

420

900

1320

2320

2004 Dec 02

Philips Semiconductors

Product specification

Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer

TDA8261TW

C-bus read mode

If bit R/W = 1 the data can be read from the TDA8261TW
(see Table 7). After recognition of its slave address, the
TDA8261TW generates an acknowledge pulse and
transfers the status byte onto the SDA line (MSB first).
Data is valid on the SDA line when the SCL clock signal is
HIGH.

A second data byte can be read from the TDA8261TW if
the microcontroller generates an acknowledge on the SDA
line. End of transmission will occur if no acknowledge is
received from the microcontroller. The TDA8261TW will

then release the data line to allow the microcontroller to
generate a STOP condition.

The POR flag is set to logic 1 at power-on and when
V

< 2.7 V. It is reset to logic 0 when an end-of-data

condition is detected by the TDA8261TW (end of a read
sequence).

The in-lock flag FL indicates that the loop is phase-locked
when set to logic 1.

When a read sequence is started, all eight bits of the status
byte must be read.

Table 7

C-bus read data format

Notes

1. X can be 1 or 0 and needs to be masked in the microcontrollers' software; MSB is transmitted first.

2. Acknowledge bit (A).

3. FL is valid only in normal mode.

OWER

-O

ESET

At power-on (bit POR = 1) or when the supply voltage drops below 2.7 V, internal registers are set according to Table 8.

Table 8

Status at POR

Note

1. X = not set.

BYTE

MSB

BITS

(1)

LSB

ACK

(2)

Address

MA1

MA0

Status byte

POR

(3)

BYTE

MSB

BITS

(1)

LSB

Programmable divider 1 (PD1)

N14 = X

N13 = X

N12 = X

N11 = X

N10 = X

N9 = X

N8 = X

Programmable divider 2 (PD2)

N7 = X

N6 = X

N5 = X

N4 = X

N3 = X

N12 = X

N1 = X

N0 = X

Control data 1 (CD1)

T2 = 0

T1 = 0

T0 = 1

R2 = X

R1 = X

R0 = X

Control data 1 (CD2)

C1 = X

C0 = X

2004 Dec 02

Philips Semiconductors

Product specification

Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer

TDA8261TW

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); note 1.

Note

1. Maximum ratings cannot be exceeded, not even momentarily without causing irreversible damages to the

TDA8261TW. Maximum ratings cannot be accumulated.

THERMAL CHARACTERISTICS

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe, it
is desirable to take normal precautions appropriate to handle integrated circuits. Every pin withstands 2000 V in the ESD
test in accordance with

"JEDEC Specification EIA/JESD22-A114A", HBM model (category 1c), except for pin 1 (XT1)

which withstands 500 V, pin 2 (XT2) which withstands 1000 V and pin 8 (V

CC(RF)

) which withstands 1500 V. Identically,

every pin withstands 200 V in the ESD test in accordance with

"JEDEC Specification EIA/JESD22-A115A", MM model

(category A).

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

supply voltage

0.3

+6.0

input voltage

pin SDA

0.3

+6.0

pin SCL

0.3

+6.0

all other pins

0.3

+ 0.3

output voltage

pin SDA

0.3

+6.0

pin VT

0.3

+35

all other pins

0.3

+ 0.3

amb

ambient temperature

+85

stg

storage temperature

+150

junction temperature

150

short-circuit time

each pin short-circuited to
V

or GND

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th(j-a)

thermal resistance from junction to ambient

in free air

41.4

K/W

2004 Dec 02

Philips Semiconductors

Product specification

Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer

TDA8261TW

CHARACTERISTICS
T

amb

= 25

C; V

= 5 V; unless otherwise specified; R

= 1 k

on base band output IBBOUT and QBBOUT;

o(p-p)

= 750 mV on IBBOUT and QBBOUT.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

supply voltage

4.75

5.00

5.25

supply current

130

POR

voltage limit where POR active

2.7

Performances from pins RFA or RFB to pins IBBOUT or QBBOUT

leak

LO leakage through pins RFA
and RFB

dBm

dynamic voltage gain range

AGC

= 0 to 3 V

v(max)

maximum voltage gain

AGC

= 3 V;

see Figs 4 and 5

o(p-p)

output voltage (peak-to-peak)

recommended value

750

IP2i

2nd-order interception point

at RF input; V

AGC

= 0 V

dBm

IP3i

3rd-order interception point

at RF input; V

AGC

= 0 V

dBm

noise figure

at maximum gain;
V

AGC

= 3 V; see Fig.6

output impedance on pin IOUT
and QOUT

input impedance on pin IBBIN
and QBBIN

1.0

v(I-Q)

voltage gain mismatch between
I and Q

in 22.5 MHz band with
bypass capacity 100 nF
between IOUT and IBBIN,
QOUT and QBBIN

absolute quadrature error

AGC

= 1.5 V;

= 750 mV (peak to

peak value); measured in
baseband

deg

Pulling sensitivity

3/4LO

sensitivity to pulling on the third
harmonic of the external VCO

see Table 9 and Fig.8

dBc

5/4LO

sensitivity to pulling on the fifth
harmonic of the external VCO

see Table 9 and Fig.8

dBc

VCO and synthesizer

osc

oscillator frequency

950

2175

MHz

n(osc)

oscillator phase noise in the
satellite band

offset

= 100 kHz; out of

PLL loop bandwidth

100

dBc/Hz

phase noise on baseband
outputs

offset

= 1 and 10 kHz;

COMP

= 1 MHz; see Fig.7

dBc/Hz

MDR

main divider ratio

32767

2004 Dec 02

Philips Semiconductors

Product specification

Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer

TDA8261TW

osc

crystal oscillator negative
impedance (absolute value)

1.0

1.5

xtal

crystal frequency

MHz

xtal

crystal series resistance

recommended value

200

XTOUT(p-p)

crystal oscillator output voltage
on pin XTOUT (peak-to-peak
value)

T2 = 1; T1 = 0; T0 = 0;
driving a load of
CL = 10 pF; R

= 1 M

500

650

Charge pump output; pin CP

leakage current

T2 = 1; T1 = 1; T0 = 0

+10

Tuning voltage output; pin VT

L(off)

leakage current when switch off T2 = 0; T1 = 0; T0 = 1;

tune

= 33 V

o(VT)

output voltage when the loop is
locked

normal mode;
V

tune

= 33 V

0.2

32.7

Bus voltage select input; pin BVS

LIH

HIGH-level leakage current

BVS

= V

100

LIL

LOW-level leakage current

BVS

= 0 V

100

SCL and SDA inputs

LOW-level input voltage

BVS

= open

0.2V

BVS

= 0 V

0.15V

BVS

= 5 V

0.3V

HIGH-level input voltage

BVS

= open

0.46V

BVS

= 0 V

0.35V

BVS

= 5 V

0.6V

LIH

HIGH-level leakage current

= 5.5 V; V

= 5.5 V

= 5.5 V; V

= 0 V

LIL

LOW-level leakage current

= 0 V; V

= 5.5 V

SCL

SCL input frequency

400

kHz

SDA output

ACK

output voltage during
acknowledge

sink

= 3 mA

0.4

AS input

HIGH-level input current

= V

LOW-level input current

= 0 V

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2004 Dec 02

Philips Semiconductors

Product specification

Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer

TDA8261TW

handbook, full pagewidth

MBL860

RF SIGNAL

GENERATOR

wanted signal

RF SIGNAL

GENERATOR

ANZAC

TDA8261TW

SPECTRUM

ANALYSER

unwanted signal

Fig.8 Measurement method for pulling sensitivity.

Table 9

Test signal conditions for pulling measurements

The level of the wanted and unwanted signal mentioned in the table are measured at the outputs of the RF signal
generators. The sensitivity to pulling is measured in baseband by the difference expressed in dB (

) between the level

of the wanted signal and the spurious generated by pulling. The ANZAC reference is HH128.

SIGNAL

FREQUENCY

LEVEL

REMARK

3/4LO test

wanted

= 2161 MHz

10 dBm

= f

+ 11 MHz

unwanted

= 1613 MHz

2 dBm

= f

3/4 + 500 kHz

local oscillator

= 2150 MHz

5/4LO test

wanted

= 1761 MHz

10 dBm

= f

+ 11 MHz

unwanted

= 2188 MHz

2 dBm

= f

5/4 + 500 kHz

local oscillator

= 1750 MHz

handbook, halfpage

MGU794

wanted

signal

11.5

spurious

signal

f (MHz)

Vsignal

Fig.9 Base band spectrum.

2004 Dec 02

Philips Semiconductors

Product specification

Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer

TDA8261TW

APPLICATION INFORMATION

handbook, full pagewidth

RFIN

XT1

XT2

VCC(PLL)

PLLGND

AGCIN

BIASN1

RFGND1

VCC(RF)

RFA

RFB

RFGND2

QOUT

BBGND1

QBBIN

VCC(BB)

QBBOUT

MBL858

R4
4.7 k

R2
1.5 k

4.7 k

22 k

R10

C38
39 pF

39 pF

4 MHz

C3
330 pF

L1
18 nH

D1
BB178

C10

2.2 pF

12 nF

330 pF

C21

82 pF

C22

82 pF

TDA8261TW

4MHz

5 V

VAGC

5 V

30 V

5 V

HEATSINK

XTOUT

SDA

SCL

BVS

VCC(VCO)

TKA

TKB

VCOGND

IOUT

BBGND2

IBBIN

BIASN2

IBBOUT

Fig.10 Typical application.

handbook, halfpage

MBL856

33 pF

R1
1 k

82 pF

68 pF

470 nH

680 nH

100 nF

coupling

LPF

Zin

Zout

Fig.11 Typical 36 MHz low-pass filter.

2004 Dec 02

Philips Semiconductors

Product specification

Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer

TDA8261TW

andbook, full pagewidth

MBL857

C-bus

IBBOUT

4 MHz

4 MHz clock

MPEG2 TS

AGCIN

PWM

LNA

RFA

TDA8261TW

TDA10086

INPUT

MATCHING

QBBOUT

Fig.12 Tuner configuration with a TDA8261TW.

Application design

The performance of the application using the TDA8261TW
strongly depends on the application design itself.
Furthermore the printed-circuit board design and the
soldering conditions should take into account the exposed
die pad underneath the device, as this requires an
optimum electrical ground path for electrical performance,
together with the capability to dissipate into the application
the heat created in the device. Philips Semiconductors can
provide support through reference designs and application

notes for TDA8261TW together with associated channel
decoders. Please contact your local Philips
Semiconductors sales office for more information.

Wave soldering is not suitable for the TDA8261TW
package. This is because the heatsink needs to be
soldered to the printed-circuit board underneath the
package but with wave soldering the solder cannot
penetrate between the printed-circuit board and the
heatsink.

2004 Dec 02

Philips Semiconductors

Product specification

Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer

TDA8261TW

PACKAGE OUTLINE

UNIT

(1)

(2)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

0.15
0.05

8
0

0.1

DIMENSIONS (mm are the original dimensions).

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

SOT549-3

04-01-22

detail X

exposed die pad side

(A3)

0.25

0.95
0.85

0.30
0.19

3.65
3.45

2.85
2.65

0.20
0.09

11.1
10.9

6.2
6.0

8.3
7.9

0.65

0.2

0.78
0.48

0.1

0.75
0.50

HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads;
body width 6.1 mm; lead pitch 0.65 mm; exposed die pad

SOT549-3

max.

1.1

2.5

5 mm

scale

pin 1 index

2004 Dec 02

Philips Semiconductors

Product specification

Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer

TDA8261TW

SOLDERING

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
worldwide use of lead-free solder pastes is increasing.

Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 seconds and 200 seconds
depending on heating method.

Typical reflow peak temperatures range from
215

C to 270

C depending on solder paste material. The

top-surface temperature of the packages should
preferably be kept:

below 225

C (SnPb process) or below 245

C (Pb-free

process)

for all BGA, HTSSON..T and SSOP..T packages

for packages with a thickness

2.5 mm

for packages with a thickness < 2.5 mm and a

volume

350 mm

so called thick/large packages.

below 240

C (SnPb process) or below 260

C (Pb-free

process) for packages with a thickness < 2.5 mm and a
volume < 350 mm

so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

For packages with leads on four sides, the footprint must
be placed at a 45

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time of the leads in the wave ranges from
3 seconds to 4 seconds at 250

C or 265

C, depending

on solder material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 seconds to 5 seconds
between 270

C and 320

2004 Dec 02

Philips Semiconductors

Product specification

Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer

TDA8261TW

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. For more detailed information on the BGA packages refer to the

"(LF)BGA Application Note" (AN01026); order a copy

from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account

be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217

C measured in the atmosphere of the reflow oven. The package body peak temperature

must be kept as low as possible.

4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder

cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.

5. If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

6. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not

suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted

on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar
soldering process. The appropriate soldering profile can be provided on request.

9. Hot bar soldering or manual soldering is suitable for PMFP packages.

PACKAGE

(1)

SOLDERING METHOD

WAVE

REFLOW

(2)

BGA, HTSSON..T

(3)

, LBGA, LFBGA, SQFP, SSOP..T

(3)

, TFBGA,

VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN, HVSON, SMS

not suitable

(4)

suitable

PLCC

(5)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(5)(6)

suitable

SSOP, TSSOP, VSO, VSSOP

not recommended

(7)

suitable

CWQCCN..L

(8)

, PMFP

(9)

, WQCCN..L

(8)

not suitable

2004 Dec 02

Philips Semiconductors

Product specification

Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer

TDA8261TW

DATA SHEET STATUS

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

LEVEL

DATA SHEET

STATUS

(1)

PRODUCT

STATUS

(2)(3)

DEFINITION

Objective data

Development

This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.

Preliminary data Qualification

This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.

III

Product data

Production

This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).

DEFINITIONS

Short-form specification

The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition

Limiting values given are in

accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information

Applications that are

described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.

DISCLAIMERS

Life support applications

These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes

Philips Semiconductors

reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status `Production'), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.

SCA76

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Philips Semiconductors a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

Printed in The Netherlands

R25/04/pp

Date of release:

2004 Dec 02

Document order number:

9397 750 14376

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA8261TW

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA8261TW