DATA SHEET
Product specification
Supersedes data of April 1994
File under Integrated Circuits, IC02
1996 Sep 12
INTEGRATED CIRCUITS
TDA8760
10-bit high-speed analog-to-digital
converter
1996 Sep 12
2
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
FEATURES
10-bit resolution
Sampling rate up to 40 MHz
Total Harmonic Distortion (THD):
-
65 dB at 4.43 MHz
full-scale and a 40 MHz clock frequency
High signal-to-noise ratio over a large analog input
frequency range (8.8 effective bits at 10 MHz full-scale
input at a 40 MHz clock frequency)
+5 V power supplies
Binary or two's complement 3-state TTL outputs
In-range 3-state TTL output
TTL compatible digital inputs
LOW-level AC clock input signal allowed
Power dissipation 850 mW (typical)
Low analog input capacitance (typ. 4.5 pF), no buffer
amplifier required
No external sample-and-hold circuit required
Analog Input; single or differential
External amplitude range control
Voltage controlled regulator included.
APPLICATIONS
High-speed analog-to-digital conversion for
Video signal digitizing
High Definition TV (HDTV)
Digital video broadcasting (satellite and cable)
Transient signal analysis
High energy physics research
Sigma-delta (SD) modulators
Medical imaging
Radar pulse digitizing.
GENERAL DESCRIPTION
The TDA8760 is a monolithic bipolar 10-bit
Analog-to-Digital Converter (ADC) for video or other
applications. It converts the analog input signal into 10-bit
binary coded digital words at a maximum sampling rate of
40 MHz. All digital inputs and outputs are TTL compatible.
However, a sine wave clock input signal is allowed.
1996 Sep 12
3
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
QUICK REFERENCE DATA
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
CCA
analog supply voltage
4.75
5.0
5.25
V
V
CCD
digital supply voltage
4.75
5.0
5.25
V
V
CCO
output supply voltage
4.75
5.0
5.25
V
I
CCA
analog supply current
-
95
100
mA
I
CCD
digital supply current
-
40
45
mA
I
CCO
output supply current
-
35
40
mA
ILE
DC integral linearity error
f
clk
= 4 MHz
-
1.0
2.0
LSB
DLE
DC differential linearity error
f
clk
= 4 MHz
-
0.6
1.0
LSB
AILE
AC integral linearity error
f
clk
= 40 MHz;
f
i
= 4.43 MHz
-
1.2
2.0
LSB
f
clk(max)
maximum clock frequency
TDA8760K/2
20
-
-
MHz
TDA8760K/4
40
-
-
MHz
P
tot
total power dissipation
-
850
970
mW
T
amb
operating ambient temperature
0
-
+70
C
TYPE
NUMBER
PACKAGE
SAMPLING
FREQUENCY
(MHz)
NAME
DESCRIPTION
VERSION
TDA8760K/2
PLCC44
plastic leaded chip carrier; 44 leads
SOT187-2
20
TDA8760K/4
40
1996
Sep
12
4
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
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BLOCK DIAGRAM
handbook, full pagewidth
MBD222 - 2
TTL
OUTPUTS
27
D9 (MSB)
29
D8
31
D7
32
D6
33
D5
34
D4
35
D3
36
D2
40
D1
41
D0 (LSB)
26
IR
data outputs
43
VCCO4
42
VCCO3
25
VCCO1
28
CCO2
23
22
CS
OTC
V
ERROR
CORECTION
FINE
ADC
FINE
DAC
COARSE
ADC
AMP
SAMPLE
AND
HOLD
10
11
AMP
VrefH
VrefL
15
14
V
I
V
I
CCD1
V
3
CCD2
V
21
CLK
2
CLK
1
CCA3
V
17
CCA2
V
13
CCA1
V
7
24
OGND1
output ground
30
OGND2
output ground
37
OGND3
output ground
44
OGND4
output ground
TDA8760
8
AGND1
9
AGND2
12
AGND3
16
AGND4
4
DGND1
20
DGND2
digital ground
analog ground
Fig.1 Block diagram for SO187 package.
1996 Sep 12
5
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
PINNING
SYMBOL
PIN
DESCRIPTION
CLK
1
clock input
CLK
2
complementary clock input
V
CCD1
3
digital supply voltage (+5 V)
DGND1
4
digital ground
n.c.
5
not connected
n.c.
6
not connected
V
CCA1
7
analog supply voltage (+5 V)
AGND1
8
analog ground
AGND2
9
analog ground
V
I
10
analog input voltage
V
I
11
complementary analog input voltage
AGND3
12
analog ground
V
CCA2
13
analog supply voltage (+5 V)
V
refL
14
reference voltage LOW
V
refH
15
reference voltage HIGH
AGND4
16
analog ground
V
CCA3
17
analog supply voltage (+5 V)
n.c.
18
not connected
n.c.
19
not connected
DGND2
20
digital ground
V
CCD2
21
digital supply voltage (+5 V)
CS
22
chip select input (TTL level input; active HIGH)
OTC
23
output two's complement
OGND1
24
output ground
V
CCO1
25
output supply voltage (+5 V)
IR
26
in-range output
D9
27
data output, bit 9 (MSB)
V
CCO2
28
output supply voltage (+5 V)
D8
29
data output, bit 8
OGND2
30
output ground
D7
31
data output, bit 7
D6
32
data output, bit 6
D5
33
data output, bit 5
D4
34
data output, bit 4
D3
35
data output, bit 3
D2
36
data output, bit 2
OGND3
37
output ground
n.c.
38
not connected
n.c.
39
not connected
D1
40
data output, bit 1
1996 Sep 12
6
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
D0
41
data output, bit 0 (LSB)
V
CCO3
42
output supply voltage (+5 V)
V
CCO4
43
output supply voltage (+5 V)
OGND4
44
output ground
SYMBOL
PIN
DESCRIPTION
Fig.2 Pin configuration for SOT187-2.
handbook, full pagewidth
MGA928-1
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
6
5
4
3
2
1
44
43
42
41
40
OGND2
D2
D3
D4
D5
D6
D7
D8
OGND3
TDA8760
refH
V
refL
V
VI
AGND2
VCCA1
V
I
VCCA2
VCCA3
AGND4
AGND3
AGND1
n.c.
n.c.
V
CCO4
D0 (LSB)
D1
DGND1
CLK
V
CCD1
CLK
n.c.
n.c.
V
CCO3
OGND4
V
CCO2
D9 (MSB)
IR
V
CCO1
OTC
CS
DGND2
V
CCD2
n.c.
n.c.
OGND1
1996 Sep 12
7
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CCA
analog supply voltage
-
0.3
+7.0
V
V
CCD
digital supply voltage
-
0.3
+7.0
V
V
CCO
output supply voltage
-
0.3
+7.0
V
V
CC1
supply voltage difference between
V
CCA
and V
CCD
-
0.5
+0.5
V
V
CC2
supply voltage difference between
V
CCO
and V
CCD
-
0.5
+0.5
V
V
CC3
supply voltage difference between
V
CCA
and V
CCO
-
0.5
0.5
V
V
I
input voltage
referenced to AGND
0.3
V
CCA
V
V
I(p-p)
input voltage for differential clock
drive (peak-to-peak value)
-
V
CCD
V
I
O
output current
-
10
mA
T
stg
storage temperature
-
55
+150
C
T
amb
operating ambient temperature
0
+70
C
T
j
junction temperature
-
+150
C
SYMBOL
PARAMETER
THERMAL RESISTANCE
R
th j-a
Thermal resistance from junction to ambient in free air
TDA8760K/4
35 K/W
TDA8760K/2
46 K/W
1996 Sep 12
8
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
CHARACTERISTICS
V
CCA
= V
CCD
= V
CCO
= 4.75 to 5.25 V; AGND and DGND shorted together;
V
CCA
-
V
CCD
= V
CCO
-
V
CCD
= V
CCA
-
V
CCO
=
-
0.25 to +0.25 V; T
amb
= 0 to +70
C; unless otherwise specified.
Typical values measured at V
CCA
= V
CCD
= V
CCO
= 5 V; T
amb
= 25
C.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
CCA
analog supply voltage
4.75
5.0
5.25
V
V
CCD
digital supply voltage
4.75
5.0
5.25
V
V
CCO
output supply voltage
4.75
5.0
5.25
V
I
CCA
analog supply current
-
95
100
mA
I
CCD
digital supply current
-
40
45
mA
I
CCO
output supply current
all outputs LOW
-
35
40
mA
Inputs
CLK
AND
CLK (
REFERENCED TO
DGND); note 1
V
IL
LOW level input voltage
0
-
0.8
V
V
IH
HIGH level input voltage
2.0
-
V
CCD
V
I
IL
LOW level input current
V
clk
or V
clk
= 0.4 V
-
400
-
-
mA
I
IH
HIGH level input current
V
clk
or V
clk
= 2.0 V
-
-
100
mA
V
clk
or V
clk
= V
CCD
-
-
300
mA
Z
I
input impedance
f
clk
= 40 MHz
-
2
-
k
C
I
input capacitance
f
clk
= 40 MHz
-
4.5
-
pF
V
clk
AC input voltage for
switching (V
clk
-
V
clk
)
DC level = 1.5 V
0.5
-
2.0
V
DC level = 2.5 V
1.5
-
5.0
V
OTC
AND
CS (
REFERENCED TO
DGND); see Table 3
V
IL
LOW level input voltage
0
-
0.8
V
V
IH
HIGH level input voltage
2.0
-
V
CCD
V
I
IL
LOW level input current
V
IL
= 0.8 V
-
400
-
-
A
I
IH
HIGH level input current
V
IH
= 2.0 V
-
-
20
A
1996 Sep 12
9
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
V
I
AND
V
I
(
REFERENCED TO
AGND); see also Tables 1 and 2
I
IL
LOW level input current
V
refH
-
V
refL
= 1.5 V
-
7
-
A
I
IH
HIGH level input current
V
refH
-
V
refL
= 1.5 V
-
22
-
A
Z
I
input impedance
f
i
= 4.43 MHz
-
2
-
k
C
I
input capacitance
f
i
= 4.43 MHz
-
4.5
-
pF
V
Ioffset(d)
input offset voltage
differential mode; V
I
= V
I
;
output code 511; Table 1
V
CCA
= 5 V
3.3
3.4
3.6
V
V
CCA
= 4.75 V
3.2
-
3.45
V
V
CCA
= 5.25 V
3.3
-
3.8
V
V
Ioffset(s)
input offset voltage
single mode; V
I
= V
Ioffset(s)
;
output code 511; Table 2
V
CCA
= 5 V
3.6
3.7
3.8
V
V
CCA
= 4.75 V
3.5
-
3.65
V
V
CCA
= 5.25 V
3.6
-
4.0
V
Voltage controlled regulator inputs V
refH
and V
refL
(referenced to AGND); differential input
V
refH
reference voltage HIGH
4.0
4.5
V
CCA
V
V
refL
reference voltage LOW
2.5
3.0
3.5
V
V
I(p-p)
input voltage amplitude
(peak-to-peak value)
1.4
1.5
1.6
V
I
refH
input current at V
refH
-
10
-
A
I
refL
input current at V
refL
-
10
-
A
Voltage controlled regulator inputs V
refH
and V
refL
(referenced to AGND); single input
V
refH
reference voltage HIGH
4.0
4.4
V
CCA
V
V
refL
reference voltage LOW
2.5
3.0
3.5
V
V
I(p-p)
input voltage amplitude
(peak-to-peak value)
1.3
1.4
1.5
V
I
refH
input current at V
refH
-
10
-
A
I
refL
input current at V
refL
-
10
-
A
Outputs (referenced to DGND)
D
IGITAL OUTPUTS
D9
TO
D0
AND
IR (
REFERENCED TO
DGND)
V
OL
LOW level output voltage
I
O
= 2 mA
0
-
0.4
V
V
OH
HIGH level output voltage
I
O
=
-
0.4 mA
2.4
-
V
CCD
V
I
O
output current in 3-state
mode
0.4 V < V
O
< V
CCO
-
20
-
+20
A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1996 Sep 12
10
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
Switching characteristics
C
LOCK FREQUENCY
f
clk
(note 1; see Fig.3)
f
clk(min)
minimum clock frequency
-
-
1
MHz
f
clk(max)
maximum clock frequency
TDA8760K/4
40
-
-
MHz
TDA8760K/2
20
-
-
MHz
t
CPH
clock pulse width HIGH
note 7
10
-
-
ns
t
CPL
clock pulse width LOW
8
-
-
ns
Analog signal processing in differential input mode; see Table 1; 50% clock duty factor;
V
I(p-p)
= V
refH
-
V
refL
= 1.5 V
L
INEARITY
ILE
DC integral linearity error
f
clk
= 4 MHz
-
1.0
2.0
LSB
DLE
DC differential linearity error
f
clk
= 4 MHz
-
0.6
1.0
LSB
AILE
AC integral linearity error
note 3
-
1.2
2.0
LSB
OFE
offset error
V
CCA
= V
CCD
= V
CCO
= 5 V;
V
I
= V
I
; T
amb
= 25
C;
output code = 511
-
3
-
+3
LSB
GE
gain error; amplitude spread
between devices
V
CCA
= V
CCD
= V
CCO
= 5 V;
T
amb
= 25
C;
V
refH
-
V
refL
= 1.5 V
-
10
-
+10
LSB
B
ANDWIDTH
(f
clk
= 40 MH
Z
); note 9
B
Analog bandwidth
-
1 dB
-
140
-
MHz
-
3 dB
-
220
-
MHz
H
ARMONICS
(f
clk
= 40 MH
Z
); see Figs 6, 8 and 9
f
1
fundamental harmonics
(full scale)
f
i
= 4.43 MHz
-
-
0
dB
f
all
harmonics (full scale);
all components
f
i
= 4.43 MHz
second harmonics
-
-
70
-
63
dB
third harmonics
-
-
70
-
63
dB
THD
total harmonic distortion
f
i
= 4.43 MHz; note 2
-
-
65
-
60
dB
S
IGNAL
-
TO
-
NOISE RATIO
; notes 4 and 5; see Figs 6, 8 and 9
SNR
signal-to-noise ratio
without harmonics;
f
clk
= 40 MHz;
f
i
= 4.43 MHz; T
amb
= 25
C
54
56
-
dB
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1996 Sep 12
11
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
E
FFECTIVE BITS
; notes 4 and 5; see Figs 6, 8 and 9
EB
effective bits
TDA8760K/2 (f
clk
= 20 MHz)
f
i
= 4.43 MHz
-
8.90
-
bits
f
i
= 7.5 MHz
-
8.70
-
bits
effective bits
TDA8760K/4 (f
clk
= 40 MHz)
f
i
= 4.43 MHz
-
8.80
-
bits
f
i
= 10 MHz
-
8.80
-
bits
f
i
= 15 MHz
-
8.70
-
bits
T
WO
-
TONE
Two-tone
two-tone intermodulation
rejection
f
clk
= 40 MHz; note 8
-
-
65
-
dB
B
IT ERROR RATE
BER
bit error rate
f
clk
= 40 MHz;
f
i
= 4.43 MHz; V
I
=
16 LSB
at code 512
-
2
10
-
12
-
times/
samples
D
IFFERENTIAL GAIN
;
SEE
Fig.5
G
diff
differential gain
f
clk
= 20 MHz; f
i
= 4.43 MHz
-
0.5
-
%
f
clk
= 40 MHz; f
i
= 4.43 MHz
-
1.0
-
%
D
IFFERENTIAL PHASE
diff
differential phase
f
clk
= 40 MHz; f
i
= 4.43 MHz
-
0.1
0.2
deg
Analog signal processing in single input mode; see Table 2; 50% clock duty factor; V
I(p-p)
= V
refH
-
V
refL
= 1.4 V
L
INEARITY
ILE
DC integral linearity error
f
clk
= 4 MHz
-
1.0
2.0
LSB
DLE
DC differential linearity error
f
clk
= 4 MHz
-
0.6
1.0
LSB
AILE
AC integral linearity error
note 3
-
1.2
2.0
LSB
B
ANDWIDTH
(f
clk
= 40 MH
Z
); note 9
B
Analog bandwidth
-
1 dB
-
140
-
MHz
-
3 dB
-
220
-
MHz
H
ARMONICS
(f
clk
= 40 MH
Z
); see Fig.7
f
1
fundamental harmonics
(full scale)
f
i
= 4.43 MHz
-
-
0
dB
f
all
harmonics (full scale);
all components
f
i
= 4.43 MHz
second harmonics
-
-
61
-
dB
third harmonics
-
-
62
-
dB
THD
total harmonic distortion
f
i
= 4.43 MHz; note 2
-
-
59
-
dB
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1996 Sep 12
12
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
S
IGNAL
-
TO
-
NOISE RATIO
; notes 4 and 5; see Fig.7
SNR
signal-to-noise ratio
without harmonics;
f
clk
= 40 MHz;
f
i
= 4.43 MHz; T
amb
= 25
C
54
56
-
dB
E
FFECTIVE BITS
; notes 4 and 5; see Fig.7
EB
effective bits
TDA8760K/2 (f
clk
= 20 MHz)
f
i
= 4.43 MHz
-
8.70
-
bits
f
i
= 7.5 MHz
-
8.50
-
bits
effective bits
TDA8760K/4 (f
clk
= 40 MHz)
f
i
= 4.43 MHz
-
8.50
-
bits
f
i
= 10 MHz
-
8.20
-
bits
T
WO
-
TONE
Two-tone
two-tone intermodulation
rejection
f
clk
= 40 MHz; note 8
-
-
60
-
dB
B
IT ERROR RATE
BER
bit error rate
f
clk
= 40 MHz;
f
i
= 4.43 MHz; V
I
=
16 LSB
at code 512
-
2
10
-
12
-
times/
samples
D
IFFERENTIAL GAIN
; see Fig.5
G
diff
differential gain
f
clk
= 20 MHz; f
i
= 4.43 MHz
-
0.5
-
%
f
clk
= 40 MHz; f
i
= 4.43 MHz
-
1.0
-
%
D
IFFERENTIAL PHASE
diff
differential phase
f
clk
= 40 MHz; f
i
= 4.43 MHz
-
0.1
0.2
deg
Timing (note 6; see Fig.3; CL = 15 pF)
t
ds
sampling delay time
-
-
2
ns
t
h
output hold time
8
-
-
ns
t
d
output delay time
-
12
16
ns
3-state output delay times (see Fig.4)
t
dZH
enable HIGH
-
12
16
ns
t
dZL
enable LOW
-
12
16
ns
t
dHZ
disable HIGH
-
8
12
ns
t
dLZ
disable LOW
-
16
20
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1996 Sep 12
13
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
Notes
1. The circuit has two clock inputs: CLK and CLK. There are three modes of operation:
a) TTL mode 1:
CLK input is at TTL level with a threshold voltage of 1.5 V and sampling is taken on the falling edge of the clock
input signal. CLK decoupled to DGND via a 100 nF capacitor.
b) TTL mode 2:
CLK input is at TTL level with threshold voltage of 1.5 V and sampling is taken on the rising edge of the clock
input signal. CLK decoupled to DGND via a 100 nF capacitor.
c) TTL mode 3:
CLK and CLK inputs are at differential TTL levels.
d) AC driving modes:
When driving the CLK input directly and with any AC signal of minimum 0.5 V (p-p) and with a DC level of 1.5 V,
the sampling takes place at the falling edge of the clock signal.
When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal.It is
recommended to decouple the CLK or CLK input to DGND via a 100 nF capacitor.
2. THD (total harmonic distortion) is obtained with the addition of the first five harmonics:
a)
b) F being the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.
3. AC linearity: full-scale differential sine wave (f
i
= 4.43 MHz; f
clk
= 40 MHz).
4. Effective bits with differential input and single input are respectively executed with full scale differential input and
full-scale single sine wave.
5. Effective bits are obtained via a Fast Fourier Transformer (FFT) treatment taking 8K acquisition points per period.
The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency).
Conversion to SNR: SNR = EB
6.02 + 1.76 dB.
6. Output data acquisition: the output data is available after the maximum delay of t
d
.
7. t
CPH
of 9 ns (minimum) can be applied at the penalty of 0.5 effective bit drop compared to typical values.
8. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two
input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter.
9. The
-
3 dB (or
-
1 dB) analog bandwidth is determined by the 3 dB (or 1 dB) reduction in the reconstructed output,
the input being a full-scale sine wave.
THD
20 log
F
(2nd)
2
(3rd)
2
(4th)
2
(5th)
2
(6th)
2
+
+
+
+
---------------------------------------------------------------------------------------------------------------
=
1996 Sep 12
14
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
Table 1 Output coding with differential inputs (typical values to AGND); V
I(p-p)
= V
refH
-
V
refL
= 1.5 V
Table 2 Output coding with single inputs (typical values to AGND); V
I(p-p)
= V
refH
-
V
refL
= 1.4 V; V
I(p-p)
= 3.7 V
Table 3 Mode selection.
Note
1. Where: X = don't care.
CODE
V
I(p-p)
V
I(p-p)
IR
BINARY OUTPUTS
TWO'S COMPLEMENT
OUTPUTS
D9 TO D0
D9 TO D0
underflow
<3.025
>3.775
0
0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
0
3.025
3.775
1
0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
1
-
-
1
0 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 1
-
-
511
3.40
3.40
1
0 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
-
-
1022
-
-
1
1 1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 1 0
1023
3.775
3.025
1
1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1
overflow
>3.775
<3.025
0
1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1
CODE
V
I(p-p)
IR
BINARY OUTPUTS
TWO'S COMPLEMENT
OUTPUTS
D9 TO D0
D9 TO D0
underflow
<3.0
0
0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
0
3.0
1
0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
1
-
1
0 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 1
-
511
3.7
1
0 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
-
1022
-
1
1 1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 1 0
1023
4.4
1
1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1
overflow
>4.4
0
1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1
OTC
CS
D0 TO D9 AND IR
1
1
binary; active
0
1
two's complement; active
X
(1)
0
high impedance
1996 Sep 12
15
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
Fig.3 Timing diagram.
CLK
MBD721
1.4 V
DATA
D0 to D7
t d
CPH
t
CPL
t
2.4 V
0.4 V
1.4 V
DATA
N + 1
DATA
N
DATA
N - 1
DATA
N - 2
dS
t
sample N + 1
sample N
sample N + 2
V
l
t HD
Fig.4 Timing diagram and test conditions of 3-state output delay time.
full pagewidth
MBD723
50 %
50 %
HIGH
LOW
dZH
t
dHZ
t
50 %
HIGH
LOW
dZL
t
dLZ
t
10 %
90 %
output
data
CS
VCCD
output
data
3.3 k
15 pF
S1
VCCD
TDA8760
CS
TEST
S1
t
dLZ
V
CCD
t
dZL
V
CCD
t
dHZ
GND
t
dZH
GND
CS = 100 kHz.
1996 Sep 12
16
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
Fig.5 Differential gain measurement conditions.
handbook, full pagewidth
MBD722
CODE 1023
CODE 0
digital output
DC offset voltage
(1)
f i = 4.43 MHz
(1)
f i = 4.43 MHz
(1)
f i = 4.43 MHz
(1)
f i = 4.43 MHz
(1)
f i = 4.43 MHz
V i
V4
V3
V2
V1
V0
(1) Full-scale divided-by-5.
G
diff
maximum of
V
n
1 to 4
(
)
V0
V0
------------------------------------------
100%
=
Fig.6
Typical effective bits under differential input
mode as a function of input signal
frequency.
20
9.0
8.0
0
4
12
MGA931 - 2
8
8.2
8.4
8.6
8.8
f (MHz)
i
effective
bits
16
f =
clk
20 MHz
40 MHz
Fig.7
Typical effective bits under single input
mode as a function of input signal
frequency.
10
9.0
8.0
0
2
6
MBD223 - 1
4
8.2
8.4
8.6
8.8
f (MHz)
i
effective
bits
8
f =
clk
20 MHz
40 MHz
1996 Sep 12
17
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
f (MHz)
0
20.2
40.4
60.6
80.8
101
121
amplitude
(dB)
MRC299
10.0
0
1.25
2.50
3.75
5.00
6.25
7.50
8.75
Fig.8 Fast Fourier Transformer (f
clk
= 20 MHz; f
i
= 4.43 MHz); for differential input mode.
Effective bits: 9.1; THD =
-
65.81 dB;
Harmonic levels (dB): 2nd =
-
75.54; 3rd =
-
76.29; 4th =
-
74.90; 5th =
-
67.50; 6th =
-
90.87.
Fig.9 Fast Fourier Transformer (f
clk
= 40 MHz; f
i
= 4.43 MHz); for differential input mode.
Effective bits: 8.92; THD =
-
65.86 dB;
Harmonic levels (dB): 2nd =
-
70.92; 3rd =
-
68.48; 4th =
-
75.32; 5th =
-
81.40; 6th =
-
72.69.
0
2.5
5
7.5
10
12.5
15
17.5
20
f (MHz)
0
20
40
60
80
100
120
amplitude
(dB)
MBD220
1996 Sep 12
18
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
INTERNAL PIN CONFIGURATION
Fig.10 Description of input and output circuitry.
handbook, full pagewidth
10 and 11
AGND
20
k
DGND
1.5 V
31 to 36,
40 and 41
30 and 37
25 and 43
30
k
DGND
1.5 V
30
k
1
2
V
CCA2
V
CCA1
V
CCA3
VCCD1 VCCD2
7
13
17
3
21
AGND1
8
AGND2
9
AGND3
12
AGND4
16
DGND1
4
DGND2
20
digital ground
analog ground
22 and 23
VCCD
CLK
CLK
OGND2 /
OGND3
CS
and
OTC
data output
bit 7 to 0
VI
V I
and
VCCO4
VCCO1 /
TDA8760
VCCO3
VCCA
MGA978
AGND
VCCA
15
14
VrefH
VrefL
1996 Sep 12
19
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
APPLICATION INFORMATION
handbook, full pagewidth
MGA979
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
TDA8760
6
5
4
3
2
1
44 43 42 41 40
39
38
37
36
35
34
32
31
30
29
33
D2
D3
D4
D5
D6
D7
D8
D9 (MSB)
D1
D0 (LSB)
100 nF
5 V
100 nF
output format select
chip select input
5 V
100 nF
5 V
100 nF
100 nF
100 nF
CLK
(1)
100 nF
100 nF
5 V
5 V
100 nF
IN
IN
4.7 F
R4
(2)
R3
(2)
100
nF
(3)
100
nF
(3)
R2
(2)
R1
(2)
3 V 4.5 V
IN
4.7 F
differential
analog inputs
IN
Fig.11 Application diagram for differential input mode.
The analog, digital and output supplies should be separated and decoupled.
(1) Differential clock signals can be applied if required.
(2) R1 and R2 must be determined in order to obtain a middle voltage of 3.4 V; see Table 1.
(3) V
refH
and V
refL
must be decoupled to AGND.
1996 Sep 12
20
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
handbook, full pagewidth
MGA980
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
TDA8760
6
5
4
3
2
1
44 43 42 41 40
39
38
37
36
35
34
32
31
30
29
33
D2
D3
D4
D5
D6
D7
D8
D9 (MSB)
D1
D0 (LSB)
100 nF
5 V
100 nF
output format select
chip select input
5 V
100 nF
5 V
100 nF
100 nF
100 nF
CLK
(1)
100 nF
100 nF
5 V
5 V
100 nF
IN
IN
R2
(2)
R1
(2)
100
nF
(3)
100
nF
(3)
3 V 4.5 V
IN
100
nF
single
analog
input
Fig.12 Application diagram for differential input mode using an input transformer.
The analog, digital and output supplies should be separated and decoupled.
(1) Differential clock signals can be applied if required.
(2) R1 and R2 must be determined in order to obtain 3.4 V at the transformer; see Table 1.
Adaptation with the single input signal impedance must be taken care of.
(3) V
refH
and V
refL
must be decoupled to AGND.
1996 Sep 12
21
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
handbook, full pagewidth
MGA981
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
TDA8760
6
5
4
3
2
1
44 43 42 41 40
39
38
37
36
35
34
32
31
30
29
33
D2
D3
D4
D5
D6
D7
D8
D9 (MSB)
D1
D0 (LSB)
100 nF
5 V
100 nF
output format select
chip select input
5 V
100 nF
5 V
100 nF
100 nF
100 nF
CLK
(1)
100 nF
100 nF
5 V
5 V
100 nF
IN
IN
4.7 F
R4
(2)
R3
(2)
100
nF
(3)
100
nF
(3)
R2
(2)
R1
(2)
3 V 4.5 V
single
analog
input
IN
4.7 F
Fig.13 Application diagram for single input mode.
The analog, digital and output supplies should be separated and decoupled.
(1) Differential clock signals can be applied if required.
(2) R1 = R3; R2 = R4. R1, R2, R3 and R4 must be determined in order to obtain a middle voltage of 3.7 V; see Table 2.
(3) V
refH
and V
refL
must be decoupled to AGND.
1996 Sep 12
22
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
PACKAGE OUTLINE
UNIT
A
A
min.
max.
max.
max. max.
1
A
4
b
p
E
(1)
(1)
(1)
e
H
E
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
4.57
4.19
0.51
3.05
0.53
0.33
0.021
0.013
16.66
16.51
1.27
17.65
17.40
0.51
2.16
45
o
0.18
0.10
0.18
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
SOT187-2
D
(1)
16.66
16.51
H
D
17.65
17.40
E
Z
2.16
D
b
1
0.81
0.66
k
1.22
1.07
k
1
0.180
0.165
0.020
0.12
A
3
0.25
0.01
0.656
0.650
0.05
0.695
0.685
0.020
0.085
0.007 0.004
0.007
L
p
1.44
1.02
0.057
0.040
0.656
0.650
0.695
0.685
e
E
e
D
16.00
14.99
0.630
0.590
16.00
14.99
0.630
0.590
0.085
0.032
0.026
0.048
0.042
29
39
44
1
6
7
17
28
18
40
detail X
(A )
3
b
p
w
M
A
1
A
A
4
L
p
b
1
k
1
k
X
y
e
E
B
D
H
E
e
E
H
v
M
B
D
Z D
A
Z E
e
v
M
A
pin 1 index
112E10
MO-047AC
0
5
10 mm
scale
95-02-25
97-12-16
inches
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
D
e
1996 Sep 12
23
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
"IC Package Databook" (order code 9398 652 90011).
Reflow soldering
Reflow soldering techniques are suitable for all PLCC
packages.
The choice of heating method may be influenced by larger
PLCC packages (44 leads, or more). If infrared or vapour
phase heating is used and the large packages are not
absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our
"Quality
Reference Handbook" (order code 9397 750 00192).
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250
C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45
C.
Wave soldering
Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:
A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
The longitudinal axis of the package footprint must be
parallel to the solder flow.
The package footprint must incorporate solder thieves at
the downstream corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260
C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150
C within
6 seconds. Typical dwell time is 4 seconds at 250
C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300
C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320
C.
1996 Sep 12
24
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
DEFINITIONS
LIFE SUPPORT APPLICATION
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
1996 Sep 12
25
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
NOTES
1996 Sep 12
26
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
NOTES
1996 Sep 12
27
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital
converter
TDA8760
NOTES
Internet: http://www.semiconductors.philips.com
Philips Semiconductors a worldwide company
Philips Electronics N.V. 1996
SCA51
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
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Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 825 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101, Fax. +43 1 60 101 1210
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 1949
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 615 800, Fax. +358 615 80920
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Germany: Hammerbrookstrae 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Greece: No. 15, 25th March Street, GR 17778 TAVROS,
Tel. +30 1 4894 339/911, Fax. +30 1 4814 240
Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.
Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722
Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,
Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Middle East: see Italy
Printed in The Netherlands
537021/1200/02/pp28
Date of release: 1996 Sep 12
Document order number:
9397 750 01092
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