1998 Aug 26

Philips Semiconductors

Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8768

FEATURES

12-bit resolution

Sampling rate up to 55 MHz

· -

3 dB bandwidth of 190 MHz

5 V power supplies

Binary or twos-complement CMOS outputs

In-range CMOS-compatible output

TLL-CMOS compatible static digital inputs

3 to 5 V CMOS-compatible digital outputs

Differential clock input; Positive Emitter Coupled Logic
(PECL)-compatible

Power dissipation 325 mW (typical)

Low analog input capacitance (typical 2 pF), no buffer
amplifier required

Integrated sample-and-hold amplifier

Differential analog input

External amplitude range control

Voltage controlled regulator included.

APPLICATIONS

High-speed analog-to-digital conversion for

Video signal digitizing

High Definition TV (HDTV)

Imaging (camera scanner)

Medical imaging

Telecommunication

Base-station receiver.

GENERAL DESCRIPTION

The TDA8768 is a bipolar 12-bit Analog-to-Digital
Converter (ADC) optimized for telecommunications and
professional imaging. It converts the analog input signal
into 12-bit binary coded digital words at a maximum
sampling rate of 55 MHz. All static digital inputs (SH, CE
and OTC) are TTL and CMOS compatible and all outputs
are CMOS compatible. A sine wave clock input signal can
also be used.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

CCA

analog supply voltage

4.75

5.0

5.25

CCD

digital supply voltage

4.75

5.0

5.25

CCO

output supply voltage

3.0

3.3

5.25

CCA

analog supply current

tbf

CCD

digital supply current

tbf

CCO

output supply current

CLK

= 4 MHz; f

= 400 kHz

3.2

tbf

INL

integral non-linearity

CLK

= 4 MHz; f

= 400 kHz

2.0

4.5

LSB

DNL

differential non-linearity

CLK

= 4 MHz; f

= 400 kHz

0.6

1.0

LSB

CLK(max)

maximum clock frequency

TDA8768H/4

MHz

TDA8768H/5

MHz

tot

total power dissipation

325

tbf

TYPE

NUMBER

PACKAGE

SAMPLING

FREQUENCY (MHz)

NAME

DESCRIPTION

VERSION

TDA8768H/4

QFP44

plastic quad flat package; 44 leads
(lead length 1.3 mm); body 10

1.75 mm

SOT307-2

TDA8768H/5

1998 Aug 26

Philips Semiconductors

Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8768

PINNING

SYMBOL

PIN

DESCRIPTION

n.c.

not connected

CCA1

analog supply voltage 1 (+5 V)

CCA3

analog supply voltage 3 (+5 V)

AGND3

analog ground 3

n.c.

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

CCA2

analog supply voltage 2 (+5 V)

AGND2

analog ground 2

ref

reference voltage input

n.c.

not connected

n.c.

not connected

n.c.

not connected

CCD2

digital supply voltage 2 (+5 V)

n.c.

not connected

DGND2

digital ground 2

OTC

control input twos complement
output; active HIGH

chip enable input
(CMOS level; active LOW)

in-range output

D11

data output; bit 11 (MSB)

D10

data output; bit 10

data output; bit 9

data output; bit 8

data output; bit 7

data output; bit 6

data output; bit 5

data output; bit 4

data output; bit 3

data output; bit 2

data output; bit 1

data output; bit 0 (LSB)

CCO

output supply voltage (3 to 5.25 V)

OGND

output ground

CLK

complementary clock input; active
LOW

CLK

clock input

CCD1

digital supply voltage 1 (+5 V)

DGND1

digital ground 1

sample-and-hold enable input
(CMOS level; active HIGH)

AGND4

analog ground 4

CCA4

analog supply voltage 4 (+5 V)

positive analog input voltage

negative analog input voltage

AGND1

analog ground 1

SYMBOL

PIN

DESCRIPTION

1998 Aug 26

Philips Semiconductors

Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8768

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. The supply voltages V

CCA

, V

CCD

and V

CCO

may have any value between

0.3 V and +7.0 V provided that the supply

voltage differences

are respected.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

CCA

analog supply voltage

note 1

0.3

+7.0

CCD

digital supply voltage

note 1

0.3

+7.0

CCO

output supply voltage

note 1

0.3

+7.0

supply voltage difference

CCA

CCD

1.0

+1.0

CCD

CCO

1.0

+4.0

CCA

CCO

1.0

+4.0

input voltage at pins 42 and 43

referenced to AGND

0.3

CCA

i(p-p)

input voltage at pins 35 and 36 for
differential clock drive (peak-to-peak
value)

CCD

output current

stg

storage temperature

+150

amb

operating ambient temperature

+85

junction temperature

150

SYMBOL

PARAMETER

CONDITION

VALUE

UNIT

th(j-a)

thermal resistance from junction to ambient

in free air

K/W

1998 Aug 26

Philips Semiconductors

Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8768

CHARACTERISTICS

CCA

= V

to V

, V

to V

, V

to V

and V

to V

= 4.75 to 5.25 V; V

CCD

= V

to V

and V

to V

= 4.75 to 5.25 V;

CCO

= V

to V

= 3.0 to 5.25 V; AGND and DGND shorted together; T

amb

= 0 to 70

C; typical values measured at

CCA

= V

CCD

= 5 V and V

CCO

= 3.3 V, T

amb

= 25

C, V

I(p-p)

= 2.0 V and C

= 10 pF; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

CCA

analog supply voltage

4.75

5.0

5.25

CCD

digital supply voltage

4.75

5.0

5.25

CCO

output supply voltage

3.0

3.3

5.25

CCA

analog supply current

CCD

digital supply current

CCO

output supply current

CLK

= 4 MHz; f

= 400 kHz

3.2

tbf

CLK

= 40 MHz; f

= 4.43 MHz

tbf

Inputs

CLK

AND

CLK (

REFERENCED TO

DGND)

LOW-level input voltage

CCD

= 5 V; note 1

3.19

3.52

HIGH-level input voltage

CCD

= 5 V; note 1

3.83

4.12

LOW-level input current

CLK

or V

CLK

= 3.19 V

HIGH-level input current

CLK

or V

CLK

= 3.83 V

input impedance

CLK

= 40 MHz

input capacitance

CLK

= 40 MHz

CLK(p-p)

differential AC input voltage
(peak-to-peak value) for
switching (V

CLK

)

DC voltage level = 2.5 V

0.5

2.0

OTC, SH

AND

CE (

REFERENCED TO

DGND); see Tables 1 and 2

LOW-level input voltage

0.8

HIGH-level input voltage

2.0

CCD

LOW-level input current

= 0.8 V

HIGH-level input current

= 2.0 V

+20

AND

(

REFERENCED TO

AGND); V

REF

= V

CCA

1.825 V; see Table 1

LOW-level input current

HIGH-level input current

input resistance

= 4.43 MHz

100

input capacitance

= 4.43 MHz

I(CM)

common mode input voltage

= V

; output code 2047

CCA

= 5 V

tbf

3.6

tbf

CCA

= 4.75 V

tbf

3.35

tbf

CCA

= 5.25 V

tbf

3.85

tbf

1998 Aug 26

Philips Semiconductors

Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8768

Voltage controlled regulator input V

ref

(referenced to AGND); note 2

ref(FS)

full-scale fixed voltage

CCA

= 5 V

3.175

ref

input current

0.5

I(p-p)

input voltage amplitude
(peak-to-peak value)

ref

= V

CCA

1.825 V

2.0

Outputs (referenced to OGND)

IGITAL OUTPUTS

D11

AND

IR (

REFERENCED TO

OGND)

LOW-level output voltage

= 2 mA

0.5

HIGH-level output voltage

0.4 mA

CCO

0.5

CCO

output current in 3-state

output level between 0.5 V
and V

CCO

+20

Switching characteristics

LOCK FREQUENCY

CLK

; see Fig.3

CLK(min)

minimum clock frequency

SH = HIGH

MHz

CLK(max)

maximum clock frequency

TDA8768H/4

MHz

TDA8768H/5

MHz

CLKH

clock pulse width HIGH

8.5

CLKL

clock pulse width LOW

8.5

Analog signal processing; 50% clock duty factor; V

= 2.0 V; V

ref

= V

CCA

1.825 V; see Table 1

INEARITY

INL

integral non-linearity

CLK

= 4 MHz; f

= 400 kHz

2.0

4.5

LSB

DNL

differential non-linearity

CLK

= 4 MHz; f

= 400 kHz;

no missing code

0.6

1.0

LSB

offset

offset error

CCA

= V

CCD

= V

CCO

= 5 V;

amb

= 25

C; V

= V

;

output code = 2047

tbf

G(FS)

gain error amplitude
(full scale); spread from
device to device

CCA

= V

CCD

= V

CCO

= 5 V;

amb

= 25

I(p-p)

= 2.0 V

ANDWIDTH

CLK

= 55 MHz); note 3

analog bandwidth

3 dB; full scale input

tbf

190

MHz

ARMONICS

CLK

= 40 MHz)

fund(FS)

fundamental harmonics
(full scale)

= 4.43 MHz

tot(FS)

harmonics (full scale);
all components

= 4.43 MHz

second harmonic

third harmonic

THD

total harmonic distortion

= 4.43 MHz; note 4

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1998 Aug 26

Philips Semiconductors

Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8768

HERMAL NOISE

th(rms)

thermal noise (RMS value)

grounded input;
f

CLK

= 40 MHz

0.25

tbf

LSB

PURIOUS FREE DYNAMIC RANGE

spurious free dynamic range

= 4.43 MHz

tbf

= 10 MHz

tbf

= 20 MHz

tbf

IGNAL

NOISE RATIO

; note 5

S/N

signal-to-noise ratio

without harmonics;
f

CLK

= 40 MHz; f

= 4.43 MHz

FFECTIVE NUMBER OF BITS

; note 5

bit

effective number of bits
TDA8768H/4 (f

CLK

= 40 MHz)

= 4.43 MHz

10.3

bits

= 10 MHz

tbf

bits

= 15 MHz

tbf

bits

effective number of bits
TDA8768H/5 (f

CLK

= 55 MHz)

= 4.43 MHz

9.9

bits

= 10 MHz

tbf

bits

= 15 MHz

tbf

bits

= 20 MHz

tbf

bits

NTERMODULATION

; note 6

TTIR

two-tone intermodulation
rejection

CLK

= 40 MHz

tbf

third order intermodulation
distortion

CLK

= 40 MHz

tbf

IT ERROR RATE

BER

bit error rate

CLK

= 40 MHz;

= 4.43 MHz;

16 LSB at code 2047

tbf

times/
sample

Timing (C

= 10 pF); see Fig.3 and note 7

d(s)

sampling delay time

output hold time

output delay time

CCO

= 5.25 V

CCO

= 3.0 V

3-state output delay times; see Fig.4

dZH

enable HIGH

dZL

enable LOW

dHZ

disable HIGH

dLZ

disable LOW

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1998 Aug 26

Philips Semiconductors

Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8768

Notes

1. The circuit has two clock inputs: CLK and CLK. There are four modes of operation:

a) PECL mode 1: (DC level varies 1 : 1 with V

CCD

) CLK and CLK inputs are at differential PECL levels.

b) PECL mode 2: (DC level varies 1 : 1 with V

CCD

) CLK input is at PECL level and sampling is taken on the falling

edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF
capacitor.

c) PECL mode 3: (DC level varies 1 : 1 with V

CCD

) CLK input is at PECL level and sampling is taken on the rising

edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF
capacitor.

d) AC driving mode 4: when driving the CLK input directly and with any AC signal of minimum 0.5 V (peak-to-peak

value) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal.
When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal. It is
recommended to decouple the CLK or CLK input to DGND via a 100 nF capacitor.

2. It is possible with an external reference connected to pin V

ref

to adjust the ADC input range. This voltage has to be

referenced to V

CCA

. For V

CCA

1.825 V, the differential input voltage amplitude is 2 V (peak-to-peak value).

3. The

3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a

full-scale sine wave.

4. THD (total harmonic distortion) is obtained with the addition of the first five harmonics:

where F is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.

5. Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all

harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to SNR:
SNR = N

bit

6.02 + 1.76 dB.

6. Intermodulation measured relative to either tone with analog input frequencies of 4.43 and 4.53 MHz. The two input

signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (

6 dB

below full-scale for each input signal).
d

is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation

product.

7. Output data acquisition: the output data is available after the maximum delay of t

THD

20 log

(2nd)

(3rd)

(4th)

(5th)

(6th)

---------------------------------------------------------------------------------------------------------------

1998 Aug 26

Philips Semiconductors

Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8768

Fig.6 Application diagram for differential clock input (PECL-compatible) using a TTL to PECL translator.

If the clock lines are more than 1 inch long they must be matched. In fact, the 27

resistor will be changed

by the series connection of R1 and R2, with R1 = Z

placed close to pins CLK and CLK.

(1) 50

matched line (Z

, L).

handbook, full pagewidth

MGL474

TDA8768

TRANSLATOR

PECL

CLK

(1)

270

100 nF

Z0 = 50

500

R1
500

R2
220

220

TTL

input

Fig.7

Application diagram for differential clock input (PECL-compatible) using a TTL to PECL translator
and Thevenin parallel terminations.

The value of R1 and R2 must be chosen in order to meet the following relations:

and

(1) 50

matched line (Z

, L).

3 V

CCD

-----------------------------

----------------------

handbook, full pagewidth

MGL473

TDA8768

TRANSLATOR

PECL

CLK

VCCD

(1)

120

R2
120

100 nF

R1
82

TTL

input

1998 Aug 26

Philips Semiconductors

Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8768

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For details,
refer to the Drypack information in the

"Data Handbook

IC26; Integrated Circuit Packages; Section: Packing
Methods".

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250

Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.

If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.

The footprint must be at an angle of 45

to the board

direction and must incorporate solder thieves
downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

1998 Aug 26

Philips Semiconductors

Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8768

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors a worldwide company

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Tel. +30 1 4894 339/239, Fax. +30 1 4814 240

Hungary: see Austria

India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381

Printed in The Netherlands

545104/750/02/pp20

Date of release: 1998 Aug 26

Document order number:

9397 750 03378

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