TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Rev. 02 -- 03 July 2002

Product data

Description

The TDA8768AH is a biCMOS 12-bit Analog-to-Digital Converter (ADC) optimized for
GSM and EDGE cellular infrastructures, professional telecommunications and
imaging, and advanced FM radio. It converts the analog input signal into 12-bit binary
coded digital words at a maximum sampling rate of 70 MHz. All static digital inputs
(SH, CE and OTC) are TTL and CMOS compatible and all outputs are CMOS
compatible. A sine wave clock input signal can also be used.

Features

12-bit resolution

Sampling rate up to 70 MHz

3 dB bandwidth of 245 MHz

5 V power supplies and 3.3 V output power supply

Binary or twos complement CMOS outputs

In-range CMOS compatible output

TTL and CMOS compatible static digital inputs

TTL and CMOS compatible digital outputs

Differential AC or PECL clock input; TTL compatible

Power dissipation 550 mW (typical)

Low analog input capacitance (typical 2 pF), no buffer amplifier required

Integrated sample-and-hold amplifier

Differential analog input

External amplitude range control

Voltage controlled regulator included

C to +85

C ambient temperature.

Applications

High-speed analog-to-digital conversion for:

Cellular infrastructure (GSM and EDGE)

Professional telecommunication

Advanced FM radio

Radar

Imaging (camera scanner)

Set Top Box (STB)

Medical imaging.

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

2 of 32

9397 750 09656

Quick reference data

Ordering information

Table 1:

Quick reference data

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

CCA

analog supply voltage

4.75

5.0

5.25

CCD

digital supply voltage

4.75

5.0

5.25

CCO

output supply voltage

3.0

3.3

3.6

CCA

analog supply current

CCD

digital supply current

CCO

output supply current

CLK

= 20 MHz

= 400 kHz

INL

integral non-linearity

CLK

= 20 MHz

= 400 kHz

2.6

4.5

LSB

DNL

differential non-linearity
(no missing code)

CLK

= 20 MHz

= 400 kHz

0.5

+1.1

0.95

LSB

CLK(max)

maximum clock frequency

TDA8768AH/4

MHz

TDA8768AH/5

MHz

TDA8768AH/7

MHz

tot

total power dissipation

CLK

= 55 MHz

= 20 MHz

550

660

Table 2:

Ordering information

Type number

Package

Sampling
frequency
(MHz)

Name

Description

Version

TDA8768AH/4

QFP44

plastic quad flat package; 44 leads
(lead length 1.3 mm); body 10

1.75 mm

SOT307-2

TDA8768AH/5

TDA8768AH/7

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

3 of 32

9397 750 09656

Block diagram

Fig 1.

Block diagram.

005aaa024

D11

MSB

data outputs

D10

6 to 10, 13, 14, 16

Vref

n.c.

LSB

VCCO

CMOS

OUTPUTS

LATCHES

ANALOG-TO-DIGITAL

CONVERTER

CLOCK DRIVER

VCCD2

VCCD1

VCCA4

VCCA3

VCCA1

CLK

CMOS

OUTPUT

OGND

OVERFLOW/

UNDERFLOW

LATCH

OTC

AMP

sample-

and-hold

TDA8768A

DGND2

DGND1

AGND4

AGND3

AGND1

VREF

REFERENCE

FSref

CMADC

REFERENCE

CMADC

DEC

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

4 of 32

9397 750 09656

Pinning information

7.1 Pinning

7.2 Pin description

Fig 2.

Pin configuration.

TDA8768AH

FCE002

CMADC

DEC

n.c.

VCCA1

VCCA3

Vref

AGND3

ref

n.c.

D11

D10

DGND2

CCD2

OGND

DGND1

GND4

GND1

CCD1

CCA4

CLK

VCCO

CLK

Table 3:

Pin description

Symbol

Pin

Description

CMADC

regulator output common mode ADC input

CCA1

analog supply voltage 1 (+5 V)

CCA3

analog supply voltage 3 (+5 V)

AGND3

analog ground 3

DEC

decoupling node

n.c.

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

VREF

reference voltage input

FSREF

full-scale reference output

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

5 of 32

9397 750 09656

Limiting values

n.c.

not connected

n.c.

not connected

CCD2

digital supply voltage 2 (+5 V)

n.c.

not connected

DGND2

digital ground 2

OTC

control input twos complement output; active HIGH

chip enable input (CMOS level; active LOW)

in-range output

D11

data output; bit 11 (MSB)

D10

data output; bit 10

data output; bit 9

data output; bit 8

data output; bit 7

data output; bit 6

data output; bit 5

data output; bit 4

data output; bit 3

data output; bit 2

data output; bit 1

data output; bit 0 (LSB)

CCO

output supply voltage (+3.3 V)

OGND

output ground

CLK

complementary clock input

CLK

clock input

CCD1

digital supply voltage 1 (+5 V)

DGND1

digital ground 1

sample-and-hold enable input (CMOS level; active HIGH)

AGND4

analog ground 4

CCA4

analog supply voltage 4 (+5 V)

analog input voltage

complementary analog input voltage

AGND1

analog ground 1

Table 3:

Pin description

...continued

Symbol

Pin

Description

Table 4:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

CCA

analog supply voltage

[1]

0.3

+7.0

CCD

digital supply voltage

[1]

0.3

+7.0

CCO

output supply voltage

[1]

0.3

+7.0

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

6 of 32

9397 750 09656

[1]

The supply voltages V

CCA

, V

CCD

and V

CCO

may have any value between

0.3 V and +7.0 V provided

that the supply voltage differences

are respected.

Thermal characteristics

10. Characteristics

supply voltage difference

CCA

CCD

1.0

+1.0

CCD

CCO

1.0

+4.0

CCA

CCO

1.0

+4.0

, V

input voltage at
pins 42 and 43

referenced to
AGND

0.3

CCA

CLK(p-p)

input voltage at pins
35 and 36 for differential
clock drive (peak-to-peak
value)

CCD

output current

stg

storage temperature

+150

amb

ambient temperature

+85

junction temperature

150

Table 4:

Limiting values

...continued

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

Table 5:

Thermal characteristics

Symbol

Parameter

Condition

Value

Unit

th(j-a)

thermal resistance from junction to
ambient

in free air

K/W

Table 6:

Characteristics

CCA

= V

to V

, V

to V

and V

to V

= 4.75 to 5.25 V; V

CCD

= V

to V

and V

to V

= 4.75 to 5.25 V;

CCO

= V

to V

= 3.0 to 3.6 V; AGND and DGND shorted together; T

amb

40 to 85

C; V

I(p-p)

= 1.9 V;

ref

= V

CCA3

1.75 V; V

I(CM)

= V

CCA3

1.6V; typical values measured at V

CCA

= V

CCD

= 5 V and V

CCO

= 3.3 V, T

amb

= 25

and C

= 10 pF; unless otherwise specified.

Symbol

Parameter

Conditions

Test

[1]

Min

Typ

Max

Unit

Supplies

CCA

analog supply voltage

4.75

5.0

5.25

CCD

digital supply voltage

4.75

5.0

5.25

CCO

output supply voltage

3.0

3.3

3.6

CCA

analog supply current

CCD

digital supply current

CCO

output supply current

CLK

= 20 MHz; f

= 400 kHz

CLK

= 40 MHz; f

= 4.43 MHz C

6.2

CLK

= 55 MHz; f

= 20 MHz

9.5

Inputs

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

7 of 32

9397 750 09656

CLK and CLK (referenced to DGND)

[2]

LOW-level input voltage

PECL mode; V

CCD

= 5 V

3.19

3.52

TTL mode

0.8

HIGH-level input voltage

PECL mode; V

CCD

= 5 V

3.83

4.12

TTL mode

2.0

CCD

LOW-level input current

CLK

or V

CLK

= 3.19 V

HIGH-level input current

CLK

or V

CLK

= 3.83 V

CLK(p-p)

differential AC input voltage
for switching
(V

CLK(p-p)

)

AC driving mode; DC voltage
level = 2.5 V

1.5

2.0

input resistance

CLK

= 55 MHz

input capacitance

CLK

= 55 MHz

OTC, SH and CE (referenced to DGND); see Tables

and

LOW-level input voltage

0.8

HIGH-level input voltage

2.0

CCD

LOW-level input current

= 0.8 V

HIGH-level input current

= 2.0 V

and V

(referenced to AGND); see

Table 7

, V

ref

= V

CCA3

1.75 V

LOW-level input current

SH = HIGH

HIGH-level input current

SH = HIGH

input resistance

= 20 MHz

input capacitance

= 20 MHz

450

I(CM)

common mode input voltage

= V

; output code 2047

CCA3

1.7

CCA3

1.6 V

CCA3

1.2

Voltage controlled regulator output CMADC

o(CM)

common mode output voltage

CCA3

1.6 -

load current

Voltage input V

ref

[3]

ref

full-scale fixed voltage

= 20 MHz; f

CLK

= 55 Msps

CCA3

1.75

ref

input current at V

ref

0.3

I(p-p)

input voltage amplitude
(peak-to-peak value)

ref

= V

CCA3

1.75 V

I(CM)

= V

CCA3

1.6 V

1.9

Voltage controlled regulator output FS

ref

o(ref)

1.9 V full-scale output voltage

CCA3

1.75

Outputs (referenced to OGND)

Digital outputs D11 to D0 and IR (referenced to OGND)

LOW-level output voltage

= 2 mA

0.5

Table 6:

Characteristics

...continued

CCA

= V

to V

, V

to V

and V

to V

= 4.75 to 5.25 V; V

CCD

= V

to V

and V

to V

= 4.75 to 5.25 V;

CCO

= V

to V

= 3.0 to 3.6 V; AGND and DGND shorted together; T

amb

40 to 85

C; V

I(p-p)

= 1.9 V;

ref

= V

CCA3

1.75 V; V

I(CM)

= V

CCA3

1.6V; typical values measured at V

CCA

= V

CCD

= 5 V and V

CCO

= 3.3 V, T

amb

= 25

and C

= 10 pF; unless otherwise specified.

Symbol

Parameter

Conditions

Test

[1]

Min

Typ

Max

Unit

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

8 of 32

9397 750 09656

HIGH-level output voltage

0.4 mA

CCO

0.5

CCO

output current in 3-state

output level between 0.5 V
and V

CCO

+20

Switching characteristics

Clock frequency f

CLK

; see

Figure 3

CLK(min)

minimum clock frequency

SH = HIGH

MHz

CLK(max)

maximum clock frequency

TDA8768AH/4

MHz

TDA8768AH/5

MHz

TDA8768AH/7

MHz

CLKH

clock pulse width HIGH

= 20 MHz

6.8

CLKL

clock pulse width LOW

= 20 MHz

6.8

Analog signal processing; 50% clock duty factor; V

= 1.9 V; V

ref

= V

CCA3

1.75 V; see

Table 7

Linearity

INL

integral non-linearity

CLK

= 20 MHz; f

= 400 kHz

2.6

4.5

LSB

DNL

differential non-linearity

CLK

= 20 MHz; f

= 400 kHz

(no missing code
guaranteed)

0.5

+1.1

0.95

LSB

err

offset error

CCA

= V

CCD

= 5 V;

CCO

= 3.3 V; T

amb

= 25

output code = 2047

gain error amplitude; spread
from device to device

CCA

= V

CCD

= 5 V;

CCO

= 3.3 V; T

amb

= 25

%FS

Bandwidth (f

CLK

= 55 MHz)

[4]

analog bandwidth

3 dB; full-scale input

220

245

MHz

Harmonics

second harmonic
TDA8768AH/4
(f

CLK

= 40 MHz)

= 4.43 MHz

dBFS

= 10 MHz

dBFS

= 15 MHz

dBFS

= 20 MHz

dBFS

second harmonic
TDA8768AH/5
(f

CLK

= 55 MHz)

= 4.43 MHz

dBFS

= 10 MHz

dBFS

= 15 MHz

dBFS

= 20 MHz

dBFS

second harmonic
TDA8768AH/7
(f

CLK

= 70 MHz)

= 4.43 MHz

dBFS

= 10 MHz

dBFS

= 15 MHz

dBFS

Table 6:

Characteristics

...continued

CCA

= V

to V

, V

to V

and V

to V

= 4.75 to 5.25 V; V

CCD

= V

to V

and V

to V

= 4.75 to 5.25 V;

CCO

= V

to V

= 3.0 to 3.6 V; AGND and DGND shorted together; T

amb

40 to 85

C; V

I(p-p)

= 1.9 V;

ref

= V

CCA3

1.75 V; V

I(CM)

= V

CCA3

1.6V; typical values measured at V

CCA

= V

CCD

= 5 V and V

CCO

= 3.3 V, T

amb

= 25

and C

= 10 pF; unless otherwise specified.

Symbol

Parameter

Conditions

Test

[1]

Min

Typ

Max

Unit

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

9 of 32

9397 750 09656

third harmonic
TDA8768AH/4
(f

CLK

= 40 MHz)

= 4.43 MHz

dBFS

= 10 MHz

dBFS

= 15 MHz

dBFS

= 20 MHz

dBFS

third harmonic
TDA8768AH/5
(f

CLK

= 55 MHz)

= 4.43 MHz

dBFS

= 10 MHz

dBFS

= 15 MHz

dBFS

= 20 MHz

dBFS

third harmonic
TDA8768AH/7
(f

CLK

= 70 MHz)

= 4.43 MHz

dBFS

= 10 MHz

dBFS

= 15 MHz

dBFS

Total harmonic distortion

[5]

THD

total harmonic distortion
TDA8768AH/4
(f

CLK

= 40 MHz)

= 4.43 MHz

dBFS

= 10 MHz

dBFS

= 15 MHz

dBFS

= 20 MHz

dBFS

total harmonic distortion
TDA8768AH/5
(f

CLK

= 55 MHz)

= 4.43 MHz

dBFS

= 10 MHz

dBFS

= 15 MHz

dBFS

= 20 MHz

dBFS

total harmonic distortion
TDA8768AH/7
(f

CLK

= 70 MHz)

= 4.43 MHz

dBFS

= 10 MHz

dBFS

= 15 MHz

dBFS

Thermal noise (f

CLK

= 55 MHz)

th(rms)

thermal noise (RMS value)

shorted input; SH = HIGH;
f

CLK

= 55 MHz

0.45

LSB

Signal-to-noise ratio

[6]

SNR

signal-to-noise ratio
TDA8768AH/4
(f

CLK

= 40 MHz)

= 4.43 MHz

dBFS

= 10 MHz

dBFS

= 15 MHz

dBFS

= 20 MHz

dBFS

signal-to-noise ratio
TDA8768AH/5
(f

CLK

= 55 MHz)

= 4.43 MHz

dBFS

= 10 MHz

dBFS

= 15 MHz

dBFS

= 20 MHz

dBFS

signal-to-noise ratio
TDA8768AH/7
(f

CLK

= 70 MHz)

= 4.43 MHz

dBFS

= 10 MHz

dBFS

= 15 MHz

dBFS

Table 6:

Characteristics

...continued

CCA

= V

to V

, V

to V

and V

to V

= 4.75 to 5.25 V; V

CCD

= V

to V

and V

to V

= 4.75 to 5.25 V;

CCO

= V

to V

= 3.0 to 3.6 V; AGND and DGND shorted together; T

amb

40 to 85

C; V

I(p-p)

= 1.9 V;

ref

= V

CCA3

1.75 V; V

I(CM)

= V

CCA3

1.6V; typical values measured at V

CCA

= V

CCD

= 5 V and V

CCO

= 3.3 V, T

amb

= 25

and C

= 10 pF; unless otherwise specified.

Symbol

Parameter

Conditions

Test

[1]

Min

Typ

Max

Unit

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

10 of 32

9397 750 09656

Spurious free dynamic range; see

Figure 7

and

SFDR

spurious free dynamic range
TDA8768AH/4
(f

CLK

= 40 MHz)

= 4.43 MHz

dBFS

= 10 MHz

dBFS

= 15 MHz

dBFS

= 20 MHz

dBFS

spurious free dynamic range
TDA8768AH/5
(f

CLK

= 55 MHz)

= 4.43 MHz

dBFS

= 10 MHz

dBFS

= 15 MHz

dBFS

= 20 MHz

dBFS

spurious free dynamic range
TDA8768AH/7
(f

CLK

= 70 MHz)

= 4.43 MHz

dBFS

= 10 MHz

dBFS

= 15 MHz

dBFS

Effective number of bits

[7]

ENOB

effective number of bits
TDA8768AH/4
(f

CLK

= 40 MHz)

= 4.43 MHz

10.1

bits

= 10 MHz

10.1

bits

= 15 MHz

10.1

bits

= 20 MHz

bits

effective number of bits
TDA8768AH/5
(f

CLK

= 55 MHz)

= 4.43 MHz

10.1

bits

= 10 MHz

10.1

bits

= 15 MHz

bits

= 20 MHz

bits

effective number of bits
TDA8768AH/7
(f

CLK

= 70 MHz)

= 4.43 MHz

bits

= 10 MHz

bits

= 15 MHz

bits

Intermodulation; (f

CLK

= 55 MHz; f

= 20 MHz)

[8]

TTIR

two-tone intermodulation
rejection

third-order intermodulation
distortion

Bit error rate (f

CLK

= 55 MHz)

BER

bit error rate

= 20 MHz; V

16 LSB at

code 2047

times/
sample

Timing (C

= 10 pF)

[9]

d(s)

sampling delay time

0.25

h(o)

output hold time

6.4

d(o)

output delay time

9.0

Table 6:

Characteristics

...continued

CCA

= V

to V

, V

to V

and V

to V

= 4.75 to 5.25 V; V

CCD

= V

to V

and V

to V

= 4.75 to 5.25 V;

CCO

= V

to V

= 3.0 to 3.6 V; AGND and DGND shorted together; T

amb

40 to 85

C; V

I(p-p)

= 1.9 V;

ref

= V

CCA3

1.75 V; V

I(CM)

= V

CCA3

1.6V; typical values measured at V

CCA

= V

CCD

= 5 V and V

CCO

= 3.3 V, T

amb

= 25

and C

= 10 pF; unless otherwise specified.

Symbol

Parameter

Conditions

Test

[1]

Min

Typ

Max

Unit

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

11 of 32

9397 750 09656

[1]

D = guaranteed by design; C = guaranteed by characterization; I = 100% industrially tested.

[2]

The circuit has two clock inputs: CLK and CLK. There are 5 modes of operation:

a) PECL mode 1: (DC level vary 1:1 with V

CCD

) CLK and CLK inputs are at differential PECL levels.

b) PECL mode 2: (DC level vary 1:1 with V

CCD

) CLK input is at PECL level and sampling is taken on the falling edge of the clock input

signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.

c) PECL mode 3: (DC level vary 1:1 with V

CCD

) CLK input is at PECL level and sampling is taken on the rising edge of the clock input

signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.

d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level

of 2.5 V, the sampling takes place at the falling edge of the clock signal.
When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to
decouple the CLK or CLK input to DGND via a 100 nF capacitor.

e) TTL mode 1: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal.

In that case CLK pin has to be connected to the ground.

[3]

The ADC input range can be adjusted with an external reference connected to V

ref

pin. This voltage has to be referenced to V

CCA

;

see

Figure 12

[4]

The

3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.

[5]

Total Harmonic Distortion (THD) is obtained with the addition of the first five harmonics:

where F is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input; see

Figure 6

[6]

Signal-to-noise ratio (SNR) takes into account all harmonics above five and noise up to nyquist frequency; see

Figure 8

[7]

Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all harmonics and noise up
to half of the clock frequency (Nyquist frequency). Conversion to SINAD is given by SINAD = ENOB

6.02 + 1.76 dB; see

Figure 5

[8]

Intermodulation measured relative to either tone with analog input frequencies of 20 and 20.1 MHz. The two input signals have the
same amplitude and the total amplitude of both signals provides full-scale to the converter (

6 dB below full scale for each input signal).

(IM3)

is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product.

[9]

Output data acquisition: the output data is available after the maximum delay of t

; see

Figure 3

3-state output delay times; see

Figure 4

dZH

enable HIGH

5.1

9.0

dZL

enable LOW

7.0

dHZ

disable HIGH

9.7

dLZ

disable LOW

9.5

Table 6:

Characteristics

...continued

CCA

= V

to V

, V

to V

and V

to V

= 4.75 to 5.25 V; V

CCD

= V

to V

and V

to V

= 4.75 to 5.25 V;

CCO

= V

to V

= 3.0 to 3.6 V; AGND and DGND shorted together; T

amb

40 to 85

C; V

I(p-p)

= 1.9 V;

ref

= V

CCA3

1.75 V; V

I(CM)

= V

CCA3

1.6V; typical values measured at V

CCA

= V

CCD

= 5 V and V

CCO

= 3.3 V, T

amb

= 25

and C

= 10 pF; unless otherwise specified.

Symbol

Parameter

Conditions

Test

[1]

Min

Typ

Max

Unit

THD

20 log

2nd

(

)

3rd

(

)

4th

(

)

5th

(

)

6th

(

)

--------------------------------------------------------------------------------------------------------------------------------------

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

12 of 32

9397 750 09656

[1]

Twos complement reference is inverted MSB.

[1]

X = don't care.

Table 7:

Output coding with differential inputs (typical values to AGND);
V

i(p-p)

= 1.9 V, V

ref

= V

CCA3

1.75 V

Code

i(p-p)

Binary outputs

Twos complement
outputs

[1]

D11 to D0

Underflow

<3.125

>4.075

0 0 0 0 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 0

3.125

4.075

0 0 0 0 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0 0 0 0 1

2047

3.6

0 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1

4094

1 1 1 1 1 1 1 1 1 1 1 0

0 1 1 1 1 1 1 1 1 1 1 0

4095

4.075

3.125

1 1 1 1 1 1 1 1 1 1 1 1

0 1 1 1 1 1 1 1 1 1 1 1

Overflow

>4.075

<3.125

1 1 1 1 1 1 1 1 1 1 1 1

0 1 1 1 1 1 1 1 1 1 1 1

Table 8:

Mode selection

OTC

D0 to D11 and IR

binary; active

twos complement; active

[1]

high-impedance

Table 9:

Sample-and-hold selection

Sample-and-hold

active

inactive; tracking mode

Fig 3.

Timing diagram.

sample N + 1

sample N

CLK

MBG855

sample N + 2

DATA
D0 to D11

t d

t h

tCLKL

tCLKH

HIGH

LOW

50 %

HIGH

LOW

50 %

DATA

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

13 of 32

9397 750 09656

= 100 kHz.

Fig 4.

Timing diagram and test conditions of 3-state output delay time.

MBG856

50 %

HIGH

LOW

tdZH

tdHZ

50 %

HIGH

LOW

tdZL

tdLZ

10 %

90 %

output
data

0 V

VCCD

output
data

3.3 k

15 pF

VCCO

TDA8768A

TEST

dLZ

dZL

dHZ

dZH

CCO

OGND

(1) 40 Msps

(2) 55 Msps

(3) 70 Msps

(1) 40 Msps

(2) 55 Msps

(3) 70 Msps

Fig 5.

Effective number of bits (ENOB) as a function
of input frequency (sample device).

Fig 6.

Total harmonic distortion (THD) as a function of
input frequency (sample device).

005aaa011

10.4

10.2

9.8

9.4

9.6

9.2

ENOB

(bits)

100

fi (MHz)

(1)

(2)

(3)

005aaa012

100

(1)

(2)

(3)

fi (MHz)

THD

(dBFS)

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

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9397 750 09656

(1) 40 Msps

(2) 55 Msps

(3) 70 Msps

(1) 40 Msps

(2) 55 Msps

(3) 70 Msps

Fig 7.

Spurious free dynamic range (SFDR) as a
function of input frequency (sample device).

Fig 8.

Signal-to-noise ratio (SNR) as a function of
input frequency (sample device).

SFDR

(dBFS)

100

fi (MHz)

(1)

(2)

005aaa013

(3)

62.5

63.5

64.5

65.5

005aaa014

SNR

(dBFS)

100

fi (MHz)

(1)

(2)

(3)

Fig 9.

Single-tone; f

= 20 MHz; f

CLK

= 55 Msps.

-160

-140

-120

-100

-80

-60

-40

-20

005aaa015

17.5

27.5

2.5

7.5

12.5

22.5

measured output range (MHz)

power

spectrum

(dB)

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

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9397 750 09656

(1) f

= 4.43 MHz

(2) f

= 20 MHz

(3) SFDR = 80 dB

Fig 14. Spurious free dynamic range (SFDR) as a function of input amplitude; FSREF = 1.9 V; f

CLK

= 55 MHz.

-60

-50

-40

-30

-20

-10

005aaa020

Vi (dBFS)

SFDR

(dBFS)

(1)

(2)

(3)

(1) = SNR

(2) = ENOB

(3) = SFDR

Fig 15. ENOB, SFDR and SNR as a function of V

ref

;

CLK

= 55 MHz; f

= 4.43 MHz.

Fig 16. ADC full-scale; V

I(p-p)

as a function of

CCA

ref

1.3 1.4

1.5

1.6

1.7

1.8

1.9

2.1

2.2

8.5

9.5

10.5

005aaa021

(1)

(2)

(3)

Vref (V)

(dB)

bits

1.2

1.4

1.6

1.8

2.2

2.4

2.6

1.3

1.4 1.5

1.6

1.7

1.8

1.9

2.1

2.2

VCCA - Vref (V)

(Vi - Vi)(p-p)

(V)

005aaa022

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

18 of 32

9397 750 09656

11. Application information

11.1 Application diagrams

The analog, digital and output supplies should be separated and decoupled.

Fig 17. Application diagram.

FCE003

n.c.

13 14 15 16 17 18 19 20 21 22

D11

(MSB)

D10

TDA8768A

44 43 42 41 40 39 38 37 36 35 34

D0 (LSB)

5 V

100 nF

5 V

100

output format select

chip select input

5 V

n.c.

CLK

100 nF

5 V

mode

10 nF

220 nF

100

1:1

Vref

100 nF

Fig 18. Application diagram for differential clock input PECL compatible using a TTL to PECL translator.

PECL

270

TTL

input

FCE168

CLK

TDA8768A

MC100
ELT20

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

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9397 750 09656

11.2 Demonstration board

C8 = close to TR1 pin.

Fig 20. Demonstration board schematic.

FCE733

CMADC

CCO

FL2

VCC

VCCO

VCC

VCCA

CCA1

CCA3

AGDN3

DEC

n.c.

ref

OGND

CLK

VCCD1
DGND1

AGND4

VCCA4
Vi
Vi
AGND1

C15 10 nF

330 nF

C13

100 nF

C16
10
nF

C10
100
nF

C11

100 nF

R6
2.4 k

1 k

5 k

1.2 k

C18
10 nF

C5
330 nF

100

C17

10 nF

220 nF

330 nF

D10

D11

OTC

DGND2

n.c

VCCD2

n.c

FSref

IC2

TDA8768A

CLK

TR1

CMADC

CLK1

MCLT1_6T_KK81

FL4

VCC

100

330 nF

FL3

4.7

GND

BYD17G

IC1

MC78MO5CDT

OUT

12 V

4.7

(16 V)

BZV55C3V6

VCCO

TP2

VCC

TM3

PMBT

2222A

VCC

C1
22

(20 V)

GND

LGT679

750

VCCA

B11

CLK2

10 nF

C19

VCCA

VCCD

C14
100 nF

C12
100 nF

FL1

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

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9397 750 09656

12. Support information

12.1 Definitions

12.1.1

Non-linearities

Integral Non-Linearity (INL).:

It is defined as the deviation of the transfer function

from a best fit straight line (linear regression computation). The INL of the code i is
obtained from the equation:

where

and

S = slope of the ideal straight line = code width; i = code value.

Differential Non-Linearity (DNL).:

It is the deviation in code width from the value of

1LSB.

where

Fig 25. PCB layout (power plane).

FCE727

INL i

( )

ideal

(

)

-----------------------------------------------

(

)

DNL i

( )

(

)

( )

---------------------------------------------

(

)

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

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12.1.2

Dynamic parameters (single tone)

Figure 26

shows the spectrum of a full-scale input sine wave with frequency f

conforming to coherent sampling (f

= M/N, where M is the number of cycles and N

is number of samples, M and N being relatively prime), and digitized by the ADC
under test.

Remark: in the following equations, P

noise

is the power of the terms which include the

effects of random noise, non-linearities, sampling time errors, and "quantization
noise".

Signal-to-noise and distortion (SINAD):

The ratio of the output signal power to the

noise plus distortion power for a given sample rate and input frequency, excluding the
DC component:

Effective Number of Bits (ENOB):

It is derived from SINAD and gives the

theoretical resolution an ideal ADC would require to obtain the same SINAD
measured on the real ADC. A good approximation gives:

Total Harmonic Distortion (THD):

The ratio of the power of the harmonics to the

power of the fundamental. For k-1 harmonics the THD is:

where

The value of k is usually 6 (i.e. calculation of THD is done on the first 5 harmonics).

Fig 26. Spectrum of full-scale input sine wave with frequency f

magnitude

fs/2

SFDR

FCE710

measured output range

SINAD db

[ ]

signal

noise

distortion

------------------------------------------

log

ENOB

SINAD dB

[

]

1 76

(

)

(

)

6 02

(

)

THD dB

[

]

harmonics

signal

---------------------------

log

harmonics

signal

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

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9397 750 09656

Signal-to-Noise Ratio (SNR):

The ratio of the output signal power to the noise

power, excluding the harmonics and the DC component.

Spurious Free Dynamic Range (SFDR):

The number SFDR specifies available

signal range as the spectral distance between the amplitude of the fundamental and
the amplitude of the largest spurious (harmonic and non-harmonic, excluding DC
component.

12.1.3

Intermodulation distortion

Spectral analysis (dual-tone)

From a dual-tone input sinusoid (f

and f

, these frequencies being chosen

according to the coherence criterion), the intermodulation distortion products IMD2
and IMD3 (respectively, 2nd and 3rd-order components) are defined, as follows.

IMD2 (IMD3):

The ratio of the RMS value of either tone to the RMS value of the worst

second (third) order intermodulation product.

SNR dB

[

]

signal

noise

-----------------

log

SFDR dB

[

]

max s

( )

------------------

log

Fig 27. Spectral analysis (dual-tone)

-160

-140

-120

-100

-80

-60

-40

-20

17.5

27.5

2.5

7.5

12.5

22.5

measured output range (MHz)

(dB)

005aaa023

IMD3

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

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9397 750 09656

The total intermodulation distortion IMD is given by

where,

and

is the power in the intermodulation component at frequency f

12.1.4

Noise Power Ratio (NPR)

When using a notch-filtered broadband white-noise generator as the input to the ADC
under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch
to the in-notch power spectral density magnitudes for the FFT spectrum of the ADC
output sample set.

IMD dB

[

]

intermod

signal

-----------------------

log

intermod

t 1

t 2

(

)

t 1

t 2

(

)

t 1

2 f

t 2

(

)

t 1

2 f

t 2

(

)

2 f

t 1

t 2

(

)

2 f

t 1

t 2

(

)

signal

t 1

(

)

t 2

(

)

( )

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

27 of 32

9397 750 09656

13. Package outline

Fig 28. SOT307-2.

UNIT

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

0.25
0.05

1.85
1.65

0.25

0.40
0.20

0.25
0.14

10.1

9.9

0.8

1.3

12.9
12.3

1.2
0.8

0.15

0.1

0.15

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.95
0.55

SOT307-2

95-02-04
97-08-01

(1)

10.1

9.9

12.9
12.3

1.2
0.8

Z E

detail X

(A )

pin 1 index

2.5

5 mm

scale

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

SOT307-2

max.

2.10

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

28 of 32

9397 750 09656

14. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.
However, to be completely safe, it is desirable to take normal precautions appropriate
to handling integrated circuits.

15. Soldering

15.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our

Data Handbook IC26; Integrated Circuit

Packages (document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine
pitch SMDs. In these situations reflow soldering is recommended.

15.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215 to 250

C. The top-surface

temperature of the packages should preferable be kept below 220

C for thick/large

packages, and below 235

C small/thin packages.

15.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically
developed.

If wave soldering is used the following conditions must be observed for optimal
results:

Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

29 of 32

9397 750 09656

The footprint must incorporate solder thieves at the downstream end.

For packages with leads on four sides, the footprint must be placed at a 45

angle

to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time is 4 seconds at 250

C. A mildly-activated flux will eliminate the

need for removal of corrosive residues in most applications.

15.4 Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300

When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320

15.5 Package related soldering information

[1]

For more detailed information on the BGA packages refer to the

(LF)BGA Application Note

(AN01026); order a copy from your Philips Semiconductors sales office.

[2]

All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the

Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods.

[3]

These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with
the heatsink on the top side, the solder might be deposited on the heatsink surface.

[4]

If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[5]

Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[6]

Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

Table 10:

Suitability of surface mount IC packages for wave and reflow soldering
methods

Package

[1]

Soldering method

Wave

Reflow

[2]

BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA

not suitable

suitable

HBCC, HBGA, HLQFP, HSQFP, HSOP,
HTQFP, HTSSOP, HVQFN, HVSON, SMS

not suitable

[3]

suitable

PLCC

[4]

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

[4][5]

suitable

SSOP, TSSOP, VSO

not recommended

[6]

suitable

9397 750 09656

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 -- 03 July 2002

31 of 32

Contact information

For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

17. Data sheet status

[1]

Please consult the most recently issued data sheet before initiating or completing a design.

[2]

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.

18. Definitions

Short-form specification -- The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.

Application information -- Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.

19. Disclaimers

Life support -- These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.

Data sheet status

[1]

Product status

[2]

Definition

Objective data

Development

This data sheet contains data from the objective specification for product development. Philips Semiconductors
reserves the right to change the specification in any manner without notice.

Preliminary data

Qualification

This data sheet contains data from the preliminary specification. Supplementary data will be published at a
later date. Philips Semiconductors reserves the right to change the specification without notice, in order to
improve the design and supply the best possible product.

Product data

Production

This data sheet contains data from the product specification. Philips Semiconductors reserves the right to
make changes at any time in order to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change Notification (CPCN) procedure
SNW-SQ-650A.

All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.

The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.

Date of release: 03 July 2002

Document order number: 9397 750 09656

Contents

Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pinning information . . . . . . . . . . . . . . . . . . . . . . 4

7.1

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

7.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Thermal characteristics. . . . . . . . . . . . . . . . . . . 6

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Application information. . . . . . . . . . . . . . . . . . 18

11.1

Application diagrams . . . . . . . . . . . . . . . . . . . 18

11.2

Demonstration board . . . . . . . . . . . . . . . . . . . 20

Support information . . . . . . . . . . . . . . . . . . . . 23

12.1

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

12.1.1

Non-linearities. . . . . . . . . . . . . . . . . . . . . . . . . 23

12.1.2

Dynamic parameters (single tone) . . . . . . . . . 24

12.1.3

Intermodulation distortion . . . . . . . . . . . . . . . . 25

12.1.4

Noise Power Ratio (NPR) . . . . . . . . . . . . . . . . 26

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 27

Handling information. . . . . . . . . . . . . . . . . . . . 28

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

15.1

Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

15.2

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 28

15.3

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 28

15.4

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 29

15.5

Package related soldering information . . . . . . 29

Revision history . . . . . . . . . . . . . . . . . . . . . . . . 30

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 31

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA8768AH/7

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA8768AH/7