1997 Dec 18

Philips Semiconductors

Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

FEATURES

8-bit analog-to-digital converter (ADC)

8-bit digital-to-analog converter (DAC)

Sampling rate up to 30 Msps for both ADC and DAC

Binary or two's complement 3-state TTL outputs

TTL compatible inputs and outputs

100 MHz variable gain amplifier (0 to 20 dB) externally
controlled

All analog inputs and outputs are differential (can also
be used in single-ended format)

Analog input signal from 0.1 to 1.0 V (p-p) differential

Offset amplifier with:

Slow offset control (

250 mV)

Fast offset control (

500 mV) eventually driven by

internal DAC.

ADC output code of 8 (typ.) when analog input signal
and offset correction inputs are 0 V

Gain, slow offset control inputs and DAC output swing
of 1.5 V (p-p) range (2.75

0.75 V)

2.75 V reference voltage

Internal references for ADC and DAC.

APPLICATIONS

CCD type of systems

Scanner

Copier

Video acquisition.

GENERAL DESCRIPTION

The TDA8785 is an 8-bit analog-to-digital converter with
gain and offset controls for the input signal. An internal
8-bit DAC provides fast offsets control.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

CCA1

analog supply voltage 1

4.75

5.0

5.25

CCA2

analog supply voltage 2

4.75

5.0

5.25

CCD

digital supply voltage

4.75

5.0

5.25

CCO

TTL output supply voltage

4.75

5.0

5.25

CCA

analog supply current

CCD

digital supply current

CCO

TTL output supply current

INL

integral non-linearity

0 to 20 dB gain; ramp input

0.7

1.8

LSB

DNL

differential non-linearity

0 to 20 dB gain; ramp input

0.2

0.7

LSB

clk(max)

maximum clock frequency

ADC and DAC

MHz

controlled gain amplifier
bandwidth

100

MHz

tot

total power dissipation

600

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA8785H

QFP44

plastic quad flat package; 44 leads (lead length 1.3 mm); body 10

1.75 mm SOT307-2

1997 Dec 18

Philips Semiconductors

Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

PINNING

SYMBOL

PIN

DESCRIPTION

CCA1

analog supply voltage 1 (+5 V)

CCA2

analog supply voltage 2 (+5 V)

AGND1

analog ground 1

AGND2

analog ground 2

DEC2

decoupling input 2

bandwidth adjustment node input

ADC reference voltage output
bottom (decoupling)

DACO(n)

DAC negative voltage output

DACO(p)

DAC positive voltage output

FSDAC(p)

DAC full-scale positive control
voltage input

FSDAC(n)

DAC full-scale negative control
voltage input

DA7

DAC TTL input; bit 7 (MSB)

DA6

DAC TTL input; bit 6

DA5

DAC TTL input; bit 5

DA4

DAC TTL input; bit 4

DA3

DAC TTL input; bit 3

DA2

DAC TTL input; bit 2

DA1

DAC TTL input; bit 1

DA0

DAC TTL input; bit 0 (LSB)

CLKDAC

DAC clock input

DGND

digital ground

CLKADC

ADC clock input

CCD

digital supply voltage (+5 V)

OGND

output ground

CCO

output supply voltage (+5 V)

AD0

output data; bit 0 (LSB)

AD1

output data; bit 1

AD2

output data; bit 2

AD3

output data; bit 3

AD4

output data; bit 4

AD5

output data; bit 5

AD6

output data; bit 6

AD7

output data; bit 7 (MSB)

output format input

DEC1

decoupling input 1

ref

reference voltage output (2.75 V)

SOFF(p)

slow offset amplifier positive
voltage input

SOFF(n)

slow offset amplifier negative
voltage input

FSAD(p)

gain control positive voltage input

FSAD(n)

gain control negative voltage input

FOFF(n)

fast offset amplifier negative
voltage input

FOFF(p)

fast offset amplifier positive voltage
input

i(p)

analog positive voltage input

i(n)

analog negative voltage input

SYMBOL

PIN

DESCRIPTION

1997 Dec 18

Philips Semiconductors

Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

FUNCTIONAL DESCRIPTION

The TDA8785 is composed of an 8-bit ADC (30 Msps),
a wide-band gain amplifier, an input offset amplifier and an
8-bit dynamic adjustment DAC.

Input signal

Two input pins are provided to apply a differential input
signal with a wide range (100 to 1000 mV differential).
It is also possible to apply a single signal by setting a DC
voltage on one of the differential pins and supplying the
signal to the other.

Controlled gain amplifier

The gain amplifier is used to adjust the wide input signal
range to the fixed ADC input range of 1 V (p-p).

A large gain of 20 dB can be achieved with low-noise
behaviour and a large bandwidth of 100 MHz to correctly
amplify square type signals with step edges. Using pin 6,
it is possible to reduce the internal bandwidth of the gain
amplifier via an external capacitor and thus improve its
noise behaviour. The gain amplifier is controlled via an
external differential voltage (single input can also be
applied).

Input offset amplifier and adjustment DAC

The Input offset amplifier contains two different control
inputs (which can also be single):

Slow offset control, for slow variation characteristics
(e.g. temperature, supply voltage, etc.)

Fast offset control, for correction related to the clock
rate.

Slow offset control is carried out by an external voltage
while fast offset control is digitally carried out via the
internal 8-bit DAC with external connections of the
respective pins V

DACO(n)

, V

DACO(p)

, V

FOFF(n)

and V

FOFF(p)

The internal 8-bit DAC operates at the ADC clock rate to
allow dynamic corrections on the input signal chain based
on the signal processing information carried out after the
digital conversion. The output voltage amplitude of the
DAC can be controlled via a different input voltage (which
can also be single) in a range of

25% with a 150

DAC

output load.

The DAC can also be used for the gain or the slow offset
control with some external DC voltage adaptations and
can be considered as a separate function of the ADC
chain. The DAC can be used independently, for example
as a video DAC.

8-bit ADC

The 8-bit ADC converts a signal of 1 V (p-p) from the
controlled gain amplifier into an 8-bit coded digital word at
a maximum rate of 30 Msps. Its reference voltage is
supplied by the general voltage regulator. The output data
format can either be binary, two's complement or 3-state
by selecting pin OF.

When all the differential inputs on the offset amplifier
(V

SOFF(p)

, V

SOFF(n)

, V

FOFF(n)

, V

FOFF(p)

, V

i(p)

and V

i(n)

) are at

0 V (equivalent to both inputs short-circuited), the output
code of the ADC is code 8.

Internal voltage regulator

An internal voltage regulator provides all the references for
the different blocks. A stable 2.75 V voltage reference
output is provided for use in the application environment.
One application is to connect all the slow control inputs
(V

FSDAC(p)

, V

FSDAC(n)

, V

SOFF(p)

, V

SOFF(n)

, V

FSAD(p)

and

FSAD(n)

) to this reference, either to their two differential

inputs to get the nominal settings or to one of the
differential inputs to have easy single-input control.

All these control inputs have the same control range.

1997 Dec 18

Philips Semiconductors

Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

CHARACTERISTICS
V

CCA1

= V

CCA2

= V

CCD

= V

CCO

= 4.75 to 5.25 V; AGND, DGND and OGND short-circuited together;

CCA

to V

CCD

= V

CCD

to V

CCO

= V

CCA

to V

CCO

0.25 to +0.25 V; T

amb

= 0 to 70

typical values measured at V

CCA

= V

CCD

= V

CCO

= 5 V and T

amb

= 25

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX. UNIT

Supplies

CCA1

analog supply voltage 1

4.75

5.0

5.25

CCA2

analog supply voltage 2

4.75

5.0

5.25

CCD

digital supply voltage

4.75

5.0

5.25

CCO

TTL output supply voltage

4.75

5.0

5.25

CCA

analog supply current

CCD

digital supply current

CCO

TTL output supply current

Reference voltages (pins V

ref

and V

)

o(ref)

output reference voltage

2.60

2.75

2.90

line

line regulation voltage

CCA

= 4.75 to 5.25 V

o(L)

output load current

0.5

+0.5

reference voltage output bottom
(decoupling)

CCA

2.5

offset(B)

offset voltage bottom

code 0

250

ADC

ADC reference voltage difference

between
code 0 and 255

Analog inputs (pins V

i(p)

and V

i(n)

); see Table 1

i(diff)(p-p)

differential input voltage V

i(p)

i(n)

(peak-to-peak value)

0 dB gain

1000

20 dB gain

100

DC input voltage

2.5

3.0

3.5

input current

input impedance

input capacitance

Fast offset amplifier inputs (pins V

FOFF(p)

and V

FOFF(n)

); DC parameters

FOFF(p)

positive input voltage

0 dB gain

500

20 dB gain

FOFF(n)

negative input voltage

0 dB gain

500

20 dB gain

DC input voltage

CCA

0.75 V

CCA

0.25 V

CCA

input current

input impedance

input capacitance

1997 Dec 18

Philips Semiconductors

Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

Slow offset amplifier inputs (pins V

SOFF(p)

and V

SOFF(n)

) gain amplifier at 0 dB; note 1

offset(ADC)

offset voltage at ADC input

SOFF(p)

= 2 V;

SOFF(n)

= 2.75 V

0.25

SOFF(p)

= 2.75 V;

SOFF(n)

= 2.75 V

SOFF(p)

= 3.5 V;

SOFF(n)

= 2.75 V

0.25

input current

Offset reference code; T

amb

= 25

OFSRE

offset reference (ADC output code)

i(p)

= V

i(n)

;

FOFF(p)

= V

FOFF(n)

;

SOFF(p)

= V

SOFF(n)

;

amplifier gain set at
0 dB

code

OFSER

offset reference error on code 8

+15

code

Gain control inputs (pins V

FSAD(p)

and V

FSAD(n)

); see Fig.7

v(min)

minimum voltage gain

FSAD(p)

= 2 V;

FSAD(n)

= 2.75 V

v(max)

maximum voltage gain

FSAD(p)

= 3.5 V;

FSAD(n)

= 2.75 V

input current

DAC full-scale control inputs (pins V

FSDAC(p)

and V

FSDAC(n)

) 150

output load on pins V

DACO(p)

and V

DACO(n)

;

see Table 3

DACO(n)

DAC negative output voltage (pin 8)

code 0 at DAC inputs

CCA

code 255 at DAC inputs;
V

FSDAC(p)

= 2 V;

FSDAC(n)

= 2.75 V

CCA

0.4

code 255 at DAC inputs;
V

FSDAC(p)

= 2.75 V;

FSDAC(n)

= 2.75 V

CCA

0.5

code 255 at DAC inputs;
V

FSDAC(p)

= 3.5 V;

FSDAC(n)

= 2.75 V

CCA

0.6

input current

Bandwidth adjustment node input (pin B); see Fig.6

input impedance

500

8-bit DAC; f

clk

= 30 MHz, ramp input; T

amb

= 25

output impedance

150

INL

integral non-linearity

0.4

0.8

LSB

DNL

differential non-linearity

0.4

1.0

LSB

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX. UNIT

1997 Dec 18

Philips Semiconductors

Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

Digital inputs (pins CLKDAC, CLKADC and DA7 to DA0)

LOW-level input voltage

0.8

HIGH-level input voltage

2.0

CCD

LOW-level input current

= 0.4 V

400

HIGH-level input current

= 2.7 V

100

input impedance

clk

= 10 MHz

input capacitance

clk

= 10 MHz

4.5

ADC output format (pin OF); see Table 2

LOW-level input voltage

0.2

HIGH-level input voltage

2.6

CCD

i(Z)

input voltage in high impedance
state

1.20

LOW-level input current

= 0.4 V

370

130

HIGH-level input current

clk

= 2.7 V

300

450

ADC digital outputs

LOW-level output voltage

= 2 mA

0.6

HIGH-level output voltage

0.4 mA

2.4

CCO

ADC and DAC switching; see Fig.4

clk(max)

maximum clock frequency

note 2

MHz

CPH

clock pulse width HIGH

CPL

clock pulse width LOW

Analog processing; note 3

INL

integral non-linearity

ramp input (full-scale);
0 to 20 dB gain

0.7

1.8

LSB

DNL

differential non-linearity

ramp input (full-scale);
0 to 20 dB gain

0.2

0.7

LSB

S/N

signal-to-noise ratio
(without harmonics)

= 2 MHz

0 dB gain

10 dB gain

20 dB gain

bandwidth

3 dB

100

MHz

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX. UNIT

1997 Dec 18

Philips Semiconductors

Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

Notes

1. V

is proportional to the amplifier gain. For instance, V

at 20 dB is the one indicated at 0 dB multiplied by 10.

2. It is recommended that the rise and fall times of the clock are >1 ns. In addition a good layout for the digital and

analog grounds is recommended.

3. Analog processing from signal inputs or fast offset amplifier inputs to ADC digital output; f

clk

= 30 MHz; no external

filtering on pin 6 (B).

4. The data set-up time (t

SU; DAT

) is the minimum period preceding the rising edge of the clock, that the input data must

be stable in order to be correctly registered. A negative set-up time indicates that the data may be initiated after the
rising edge and still be recognized. The data set hold time (t

HD; DAT

) is the minimum period following the rising edge

of the clock, that the input data must be stable in order to be correctly registered. A negative hold time indicates that
the data may be released prior to the rising edge and still be recognized.

5. The residual settling accuracy is defined as follows. When a full-scale step is applied to the DAC, the initial settling

shows a fast settling behaviour. For the final part, the DAC analog output shows a slow settling behaviour.
The Residual Settling Accuracy (RSA) is defined as the full-scale error at the cross-over point at time t

Timing

ADC

DIGITAL OUTPUTS

= 15 pF)

sampling delay time

1.5

output hold time

output delay time

DAC

OUTPUTS

(

PINS

DACO(p)

AND

DACO(n)

)

SU; DAT

data set-up time

note 4

0.3

HD; DAT

data hold time

note 4

DAC setting time (10 to 90%)

= 150

; C

= 15 pF

RSA

residual setting accuracy

note 5; see Fig.8

0.1

2.5

STATE OUTPUT DELAY TIMES

(see Fig.5)

dZH

enable HIGH

dZL

enable LOW

dHZ

disable HIGH

dLZ

disable LOW

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX. UNIT

1997 Dec 18

Philips Semiconductors

Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

Table 1

Output coding and input voltage (typical values; referenced to AGND, V

i(p)

i(n)

= 1 V (p-p), 0 dB gain, no

offset correction

Table 2

OF input coding

Note

1. Use C

10 pF to DGND.

Table 3

Input coding and DAC output voltages (typical values; referenced to V

CCA

regardless of the offset voltage);

FSDAC(p)

= V

FSDAC(n)

STEP

i(p)

i(n)

BINARY OUTPUT BITS

TWO'S COMPLEMENT OUTPUT BITS

Underflo

0.032

254

255

0.968

Overflow

>0.968

AD0 to AD7

active, two's complement

high impedance

open circuit; note 1

active, binary

CODE

BINARY INPUT DATA

DAC OUTPUT VOLTAGES (V)

DA7

DA6

DA5

DA4

DA3

DA2

DA1

DA0

= 10 k

= 150

DACO(p)

DACO(n)

DACO(p)

DACO(n)

1.0

0.5

128

0.5

0.25

254

255

1.0

0.5

1997 Dec 18

Philips Semiconductors

Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

"Quality

Reference Handbook" (order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250

Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.

If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

The footprint must be at an angle of 45

to the board

direction and must incorporate solder thieves
downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

1997 Dec 18

Philips Semiconductors

Product specification

8-bit high-speed analog-to-digital converter
with gain and offset controls

TDA8785

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors a worldwide company

SCA56

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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 0044

Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580920

France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300

Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240

Hungary: see Austria

India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966

Indonesia: see Singapore

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381

Middle East: see Italy

Printed in The Netherlands

547047/1200/02/pp24

Date of release: 1997 Dec 18

Document order number:

9397 750 03005

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