1997 Nov 17

Philips Semiconductors

Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

FEATURES

Correlated Double Sampling (CDS), AGC, soft clipper,
pre-blanking, 10-bit ADC and reference regulator
included

Fully programmable via a 3-wire serial interface

Sampling frequency up to 18 MHz

AGC gain from 3.5 to 33.5 dB (in 0.1 dB steps)

Programmable soft clipper for white compression
(starting at 40% of the input signal)

Standby mode available for each block for power saving
applications (19 mW)

6 dB fixed gain analog output for analog iris control

8-bit and 10-bit DAC included for analog settings

Low power consumption of only 475 mW (typ.)

5 V operation and 2.5 to 5 V operation for the digital
outputs

CDS control pulse: TDA8786 = HIGH;
TDA8786A = LOW

TTL compatible inputs, TTL and CMOS compatible
outputs.

GENERAL DESCRIPTION

The TDA8786; TDA8786A is a 10-bit analog-to-digital
interface for CCD cameras. The device includes a
correlated double sampling circuit, AGC, a soft clipper
circuit and a low power 10-bit Analog-to-Digital Converter
(ADC) together with its reference voltage regulator.

The AGC and soft clipper circuits are controlled by on-chip
DACs via a serial interface.

A 10-bit DAC controls the ADC input clamp level.

A pre-blanking function is also included.

An additional DAC is provided for additional system
controls; its output voltage range is 1.4 V (p-p) which is
available at pin OFDOUT.

APPLICATIONS

CCD camera systems.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

CCA

analog supply voltage

4.5

4.75

5.5

CCD

digital supply voltage

4.5

4.75

5.5

CCO

digital outputs supply voltage

2.5

2.6

5.5

CCA

analog supply current

CCD

digital supply current

CCO

digital outputs supply current

CLK

= 18 MHz;

= 20 pF; ramp input

ADC

res

ADC resolution

bits

i(CDS)(p-p)

CDS input voltage (peak-to-peak value)

400

1200

CDS

CDS output amplifier gain

CLK(max)

maximum clock frequency

MHz

AGC

dyn

AGC dynamic range

tot(rms)

total noise from CDS input to ADC
output (RMS value)

gain = 3.5 dB

0.5

LSB

tot

total power consumption

475

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA8786G

LQFP48

plastic low profile quad flat package; 48 leads; body 7

1.4 mm

SOT313-2

TDA8786AG

1997 Nov 17

Philips Semiconductors

Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

PINNING

SYMBOL

PIN

DESCRIPTION

CLPOPB

optical black clamp control pulse input (active HIGH for TDA8786, active LOW for TDA8786A)

PBK

pre-blanking control pulse input; if PBK is HIGH (LOW) the signal is replaced by the optical
black level for TDA8786 (TDA8786A)

OFDOUT

analog output of the additional 8-bit control DAC (controlled via the serial interface)

AMPOUT

CDS amplifier output (fixed gain = +6 dB)

AGND1

analog ground 1

CCA1

analog supply voltage 1

AGCOUT

AGC and soft clipper amplifier signal output

PBIN

optical black clamp and pre-blanking block signal input (from AGCOUT via a capacitor)

PBOUT

optical black clamp and pre-blanking block signal output

ADCIN

ADC analog signal input (from PBOUT or AGCOUT via a capacitor)

CLPADC

clamp control input for ADC analog input signal clamp (active HIGH for TDA8786 and active
LOW for TDA8786A)

ref

ADC input clamp reference voltage (normally connected to pin VRB or DACOUT)

DACOUT

DAC output for ADC clamp level

AGND2

analog ground 2

CCA2

analog supply voltage 2

ADC reference voltage (BOTTOM) code 0

ADC reference voltage (TOP) code 1023

DEC1

decoupling 1 (decoupled to ground via a capacitor)

STGE

CDS offset storage

SDATA

serial data input for the 4 control DACs (9-bit DAC for AGC gain, 4-bit DAC for soft clipper;
additional 8-bit DAC for OFD output voltage; 10-bit DAC for ADC clamp level and the stand-by
mode per block; see Table 1)

SCLK

serial clock input for the control DACs and their serial interface; see Table 1

SEN

enable input for the serial interface shift register (active when SEN = logic 0); see Table 1

STDBY

stand-by control pin (active HIGH); all the output bits are logic 0 when stand-by is enabled

CCD1

digital supply voltage 1

DGND1

digital ground 1

ADC digital output 0 (LSB)

ADC digital output 1

ADC digital output 2

ADC digital output 3

ADC digital output 4

ADC digital output 5

ADC digital output 6

ADC digital output 7

ADC digital output 8

ADC digital output 9 (MSB)

OGND

digital output ground

1997 Nov 17

Philips Semiconductors

Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

CCO

digital output supply voltage

output enable (LOW: digital outputs active; HIGH: digital outputs high impedance)

CCD2

digital supply voltage 2

DGND2

digital ground 2

CLK

ADC clock input

CLPCDS

CDS clamp control input (active HIGH for TDA8786; active LOW for TDA8786A)

CDSP1

CDS control pulse input 1 (active HIGH for TDA8786; active LOW for TDA8786A)

CDSP2

CDS control pulse input 2 (active HIGH for TDA8786; active LOW for TDA8786A)

CCA3

analog supply voltage 3

IN1

input signal 1 from CCD (usually black channel)

IN2

input signal 2 from CCD (usually video channel)

AGND3

analog ground 3

SYMBOL

PIN

DESCRIPTION

Fig.2 Pin configuration.

TDA8786

TDA8786A

MGE360

OGND

DGND1

CLPOPB

PBK

OFDOUT

AMPOUT

AGND1

VCCA1

PBIN

PBOUT

CLPADC

Vref

IN2

IN1

CCA3

CDSP2

CDSP1

CLPCDS

DGND2

CCD2

CCO

AGND3

CLK

AGCOUT

ADCIN

AGND2

CCA2

DEC1

STGE

SDATA

SEN

STDBY

CCD1

DACOUT

SCLK

1997 Nov 17

Philips Semiconductors

Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. The supply voltages V

CCA

, V

CCD

and V

CCO

may have any value between

0.3 and +7.0 V provided that the supply

voltage difference

remains as indicated.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

CCA

analog supply voltage

note 1

0.3

+7.0

CCD

digital supply voltage

note 1

0.3

+7.0

CCO

output stages supply voltage

note 1

0.3

+7.0

supply voltage difference

between V

CCA

and V

CCD

1.0

+1.0

between V

CCA

and V

CCO

1.0

+4.0

between V

CCD

and V

CCO

1.0

+4.0

input voltage

referenced to V

SSA

0.3

+7.0

CLK(p-p)

AC input voltage for switching
(peak-to peak-value)

referenced to V

SSD

CCD

output current

stg

storage temperature

+150

amb

operating ambient temperature

+75

junction temperature

150

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th(j-a)

thermal resistance from junction to ambient

in free air

K/W

1997 Nov 17

Philips Semiconductors

Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

CHARACTERISTICS

CCA

= V

CCD

= 4.75 V; V

CCO

= 2.6 V; f

CLK

= 18 MHz; T

amb

= 25

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

CCA

analog supply voltage

4.5

4.75

5.5

CCD

digital supply voltage

4.5

4.75

5.5

CCO

digital outputs supply
voltage

2.5

2.6

5.5

CCA

analog supply current

CCD

digital supply current

CCO

digital outputs supply
current

= 20 pF on all data

outputs; ramp input

Digital inputs

LOCK INPUT

: CLK (

REFERENCED TO

DGND)

LOW-level input voltage

0.8

HIGH-level input voltage

2.0

CCD

LOW-level input current

CLK

= 0.8 V

HIGH-level input current

CLK

= 2.0 V

input impedance

CLK

= 18 MHz

input capacitance

CLK

= 18 MHz

NPUTS

: CDSP1

AND

CDSP2

LOW-level input voltage

0.6

HIGH-level input voltage

2.2

CCD

LOW-level input current

= 0.6 V

100

HIGH-level input current

= 2.2 V

NPUTS

: SEN, STDBY, CLPCDS, CLPOPB, PBK

AND

CLPADC

LOW-level input voltage

0.6

HIGH-level input voltage

2.2

CCD

input current

NPUTS

: SEN, SDATA

AND

SCLK (see Fig.14)

su1

SEN set-up time compared
to SCLK rising edge

su2

SDATA set-up time
compared to SCLK rising
edge

su3

SEN set-up time compared
to SCLK falling edge

hd3

SEN hold time compared
to SCLK rising edge

hd4

SDATA hold time
compared to SCLK rising
edge

1997 Nov 17

Philips Semiconductors

Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

Correlated Double Sampling; CDS

i(CDS)(p-p)

CDS input amplitude
(peak-to-peak value)

400

1200

STGE,IN1,IN2

input current pins 19, 46
and 47

CDS(min)

CDS control pulses
minimum active time
(HIGH for TDA8786,
LOW for TDA8786A)

i(CDS1,2)

= f

CLK(pix)

i(CDS)(p-p)

= 1200 mV

black-to-white transition in
one pixel (

1 LSB typ.)

hd1

hold time IN1 compared to
control pulse CDSP1

see Fig.15

hd2

hold time of IN2 compared
to control pulse CDSP2

see Fig.15

0.5

Amplifier outputs

AMPOUT

output amplifier gain

AMPOUT

output amplifier
impedance

300

AMPOUT(p-p)

output amplifier dynamic
voltage level
(peak-to-peak value)

2.4

AMPOUT(bl)

output amplifier black
level voltage

1.1

AGCOUT(p-p)

AGC output amplifier
dynamic voltage level
(peak-to-peak value)

1800

AGCOUT

AGC output amplifier black
level voltage

1.1

AGCOUT

AGC output amplifier
output impedance

at 10 kHz

AGCOUT

AGC output static drive
current

static

OPB(p-p)

optical black clamp and
blanking block output
dynamic voltage
(peak-to-peak value)

1.8

OPB

optical black clamp and
blanking block output black
level voltage

1.4

OPB

optical black clamp and
blanking block output
impedance

at 10 kHz

OPB

OPB output current drive

static

PBIN

input current pin 8

AGC(min)

minimum gain of AGC
circuit

AGC DAC input code = 00
(9-bit control)

3.5

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1997 Nov 17

Philips Semiconductors

Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

AGC(max)

maximum gain of AGC
circuit

AGC DAC input
code =

319 (9-bit control)

33.5

AGCOUT

AGC output amplifier black
level voltage

1.1

inflex(p-p)

voltage at soft clipper
inflexion point
(peak-to-peak value)

soft clipper 4-bit control
DAC input code = 00

40%
V

AGCOUT(p-p)

soft clipper 4-bit control
DAC input code = 15

100%
V

AGCOUT(p-p)

soft clipper compression
ratio

i(sc)

< V

inflex

1.0

i(sc)

> V

inflex

0.66

CLAMPS

mADC

ADC clamps
transconductance

at clamp level

mPBK

PBK clamp
transconductance

at clamp level

mCDS

CDS clamps
transconductance

at clamp level

5.5

PBIN(clamp)

clamp voltage
at PBIN input

1.4

Analog-to-Digital Converter; ADC

CLK(max)

maximum clock frequency

MHz

CPH

clock pulse width HIGH

CPL

clock pulse width LOW

CLK

clock input slew rate
(rising and falling edge)

10 to 90%

0.5

V/ns

i(ADC)(p-p)

ADC input voltage level
(peak-to-peak value)

1.8

ADC reference voltage
output code 0

1.4

ADC reference voltage
output code 1023

3.2

ADCIN

input current pin 10

ILE

integral linearity error

CLK

= 18 MHz; ramp input

1.0

2.0

LSB

DLE

differential linearity error

CLK

= 18 MHz; ramp input

0.4

0.75

LSB

d(s)

sampling delay time

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1997 Nov 17

Philips Semiconductors

Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

Total chain timing (CDS + ADC + SOFT CLIPPER + PRE BLANKING + ADC)

time delay between
CDSP1 and CLK

50% at rising edges of
CLK and CDSP1:
transition full-scale code 0
to code 1023;
V

i(CDS)(p-p)

= 1200 mV

(rms)

noise (RMS value)

gain = 3.5 dB

0.5

LSB

Digital-to-Analog Converters (OFDOUT DAC)

OFDOUT(p-p)

additional 8-bit control
DAC (OFD) output voltage
(peak-to-peak value)

1.4

OFDOUT(0)

DC output voltage for
code 0

2.0

OFDOUT(255)

DC output voltage for
code 255

3.4

OFDOUT

additional 8-bit control
DAC (OFD) output
impedance

2000

OFDOUT

OFD output current drive

static

ADC clamp control DAC (see Fig.5)

DACOUT(p-p)

ADC clamp 10-bit control
DAC output voltage
(peak-to-peak value)

0.9

DACOUT

DC output voltage

code 0

1.4

code 1023

2.3

DACOUT

ADC clamp control DAC
output impedance

250

DACOUT

DAC output current drive

static

OFE

LOOP

maximum offset error of
DAC + ADC clamp loop

code 0

LSB

code 1023

LSB

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1997 Nov 17

Philips Semiconductors

Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

Table 1

Serial interface programming (see note 1)

Note

1. At the end of each programming sequence (usually during the video vertical blanking), the soft clipper register must

be reloaded (for example if the soft clipper is not used, code 15 must be entered in the soft clipper register at the end
of each TDA8786(A) programming sequence).

Table 2

Standby selection

ADDRESS BITS

DATA BITS D9 to D0

OFDOUT output control (D7 to D0).

Soft clipper control. Only the 4 LSBs (D3 to D0) are used. Bits D9 to D4 should be set to
logic 0.

AGC gain control (D8 to D0).

Partial standby controls for power consumption optimization. Only the 4 LSBs (D3 to D0)
are used. Bits D9 to D4 should be set to logic 0:

D0 = 1: CDS + AGC + soft clipper block in standby; I

CCA

+ I

CCD

= 48 mA

D1 = 1: optical black clamp + blanking block in standby; I

CCA

+ I

CCD

= 92 mA

D2 = 1: OFD DAC in standby; I

CCA

+ I

CCD

= 98 mA

D3 = 1: 6 dB amplifier (output on AMPOUT pin) in standby; I

CCA

+ I

CCD

= 98.5 mA.

Clamp reference DAC (D9 to D0).

STDBY

D9 to D0

CCA

+ I

CCD

LOW

4 mA (typ.)

active

99 mA (typ.)

1997 Nov 17

Philips Semiconductors

Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

APPLICATION INFORMATION

TDA8786 and SAA8110 can be used with Sharp CCDs. TDA8786A and SAA8110 can be used with Sony CCDs. Table 3
gives as an example some references of ICs which may be used with Philips TDA8786(A)/SAA8110. This overview is
not restrictive, both devices are compatible with other CCD/V-driver/PPG combinations including the more recent ones.

Table 3

Possible components for the application of Figs 17 and 18

Notes to the application diagram

1. In the configuration of Figs 17 and 18, the microcontroller reads and writes data from/to the DSP using the

SNERT-bus (UART mode 0). Optional external control is available via the I

C-bus.

2. Free I/O pins of the microcontroller can be used to control PGG, or for other purposes.

3. 83Cxxx processing is synchronized by VD interruption. Depending on VD polarity, it can be necessary to invert VD.

4. A customized 83Cxxx is available for this application. Please contact your nearest Philips sales office.

CCD TYPE

COMPONENT

TYPE

NTSC

PAL

MEDIUM

RESOLUTION

HIGH

RESOLUTION

MEDIUM

RESOLUTION

HIGH

RESOLUTION

Sony CCDs

CCD

LZ2313H5

LZ2353A

LZ2323H5

LZ2363

V-driver

LR36683N

timing generator

LZ95G55

LZ95G71

LZ95G55

LZ95G71

Sharp CCDs

CCD

ICX056AK

ICX068AK

ICX057AK

ICXo69AK

V-driver

CXD1250MN, CXD1267N

timing generator

CXD1257AR

CXD1265R

CXD1257AR

CXD1265R

1997 Nov 17

Philips Semiconductors

Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

Fig.17 SAA8110G system configuration for camera application (continued in Fig.18).

handbook, full pagewidth

P0 (optional, PPG setting)

P1 (optional, PPG settings)

CDAC

OUT

(optional, can be used for frequency tuning)

CLK1 (to ADC and DSP)

CLK2 (to DSP, CLK2 = 2

CLK1)

CDSPULSE1

CDSPULSE2

CLAMPCDS (CLAMP CDS, OPB, ADC can be the same)

CLAMPOPB

CLAMPADC

PreBlank (optional)

HD (to DSP and

VD (to DSP and

FI (to DSP and

CDAC

OUT

CLK1

CLK2

CDSPULSE1

CDSPULSE2

CLAMPCDS

CLAMPOPB

CLAMPADC

PreBlank

Horizontal Drive

Vertical Drive

Field Id

VERTICAL DRIVER

(PPG)

V4 V3 V2 V1

Electrical

Shutter

Reset
Pulse

OGND

100

1 nF

2.2

200

DGND1

CLPOPB

CLK1

100 nF

OEN (optional)
(from microcontroller)

100 nF

VDDD

CLAMPCDS

CDSPULSE1

CDSPULSE2

PBK

CLAMPOPB

PreBlank

OFDOUT

AMPOUT

AGND1

VCCA1

AGCOUT

PBIN

PBOUT

ADCIN

CLPADC

Vref

TDA8786G

TDA8786AG

ANALOG-TO-DIGITAL INTERFACE

AGND3

IN2

IN1

CCA3

CCD2

CDSP2

CDSP1

CLPCDS

DGND2

CCO

CLK

DACOUT

AGND2

CCA2

SEN

DEC1

STGE

SCLK

CCD1

STBY

ATA

13 14 15 16

17 18 19

48 47

220 nF

CLAMPADC

(from PPG)

46 45

44 43 42

VERTICAL

DRIVER BUFFER

CCD

SMP_CLK
(from DSP)

VDDD

VDDA1

xxV

SWITCH MODE

POWER SUPPLIES

(optional)

CCDout

OFD level

(optional)

VD (from PPG)

SDA

SCL

PTC

VDD

100 nF

VSS

4.7

12 MHz

A0/SN

SCL/SN

HD (opt.)

A1/SN

RES

83C54/

83C654

(OM-XXX)

MICRO-

CONTROLLER

EPROM

PCF8598
PCF8594
PCF8582

18 pF

VDD

VDDD

P0.0/AD0

P0.1/AD1

P0.2/AD2

P0.3/AD3

P0.4/AD4

P0.5/AD5

RESET_DSP
(to DSP)

P0.6/AD6

P0.7/AD7

ALE

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P2.0/A8

OEN (optional)

(to ADC)

BC848C

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6/SCL

P1.7/SDA

RST

P3.0/RxD

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

XTAL1

VSS

5 V

VDDA1

5 V

VDDA2

5 V

VDDA3

VDDD

5 V

GND

SCL

SDA

10 k

4.7
k

10 k

MGK393

digital ground

analog ground

Shutter

Reset

1997 Nov 17

Philips Semiconductors

Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

Fig.18 SAA8110G system configuration for camera application (continued from Fig.17).

(1) Values depend on DSP output configuration.

handbook, full pagewidth

MGK394

SAA8110G

DIGITAL SIGNAL PROCESSOR

10 nF

100 nF

100

100 nF

SMP_CLK (to power supply)

digital ground

analog ground

RESET_DSP

(from

VDDA2

VDDA3

22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

47 k

150 k

38 39 40

80 79

100 nF

A1/SN

RES

A0/SN

SDA

optional

SCL/SN

78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

CVBS-RCA

CVBS

V, Red

U, Blue

Green

SVHS

VDDD(C1)

VSYNCIN

FIIN

CCD9

CCD7

CCD5

CCD3

CCD1

VSSD(C2)

VDDD

VSSA(CD)

CLK1

HSYNCIN

VSSD(C1)

VDDD

CCD8

CCD6

CCD4

CCD2

CCD0

SCLK

CDAC

RBIAS

DDA(CD)

ATA

STROBE

SMP

SIS

DDD(C2)

RESET

SSA(OB)

OUT3

DDA(O3)

OUT2

DDA(O2)

OUT1

DDA(O1)

CDACOUT

CDAC

OUT

UV1

100 nF

100

UV7

LLC

HREF

FIOUT

VDDD(P1)

RBIAS

VSSA(BG)

UV2

UV3

UV4

UV5

UV6

VSSD(P1)

DDD(P2)

VDDD

CREF/PXQ

VSYNCOUT

CLK2

CLK2 (from PPG)

VDDA(BG)

DECOUPL

100 nF

VDDA(DC)

OUT

A0/SN

DDD(C3)

SSD(C4)

SCL/SN

SSD(C3)

SDA

A1/SN

RES

SSD(P2)

UV0

VDDD

DIGIT

AL OUTPUT CONNECT

(1)

1997 Nov 17

Philips Semiconductors

Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all LQFP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250

Wave soldering

Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all LQFP
packages with a pitch (e) equal or less than 0.5 mm.

If wave soldering cannot be avoided, for LQFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.

The footprint must be at an angle of 45

to the board

direction and must incorporate solder thieves
downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

1997 Nov 17

Philips Semiconductors

Product specification

10-bit analog-to-digital interface for
CCD cameras

TDA8786; TDA8786A

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors a worldwide company

SCA56

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

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Printed in The Netherlands

547047/1200/03/pp28

Date of release: 1997 Nov 17

Document order number:

9397 750 02926

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