1996 Feb 21

Philips Semiconductors

Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter

TDA8790

FEATURES

8-bit resolution

Operation between 2.7 and 5.5 V

Sampling rate up to 40 MHz

DC sampling allowed

High signal-to-noise ratio over a large analog input
frequency range (7.3 effective bits at 4.43 MHz
full-scale input at f

clk

= 40 MHz)

CMOS/TTL compatible digital inputs and outputs

External reference voltage regulator

Power dissipation only 30 mW (typical)

Low analog input capacitance, no buffer amplifier
required

Sleep mode (4 mW)

No sample-and-hold circuit required.

APPLICATIONS

High-speed analog-to-digital conversion for:

Video data digitizing

Camera

Camcorder

Radio communication.

GENERAL DESCRIPTION

The TDA8790 is an 8-bit universal analog-to-digital
converter (ADC) for video and general purpose
applications. It converts the analog input signal from
2.7 to 5.5 V into 8-bit binary-coded digital words at a
maximum sampling rate of 40 MHz. All digital inputs and
outputs are CMOS/TTL compatible. A sleep mode allows
reduction of the device power consumption down to 4 mW.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

DDA

analog supply voltage

2.7

3.3

5.5

DDD

digital supply voltage

2.7

3.3

5.5

DDO

output stages supply voltage

2.5

3.3

5.5

supply voltage difference

DDA

DDD

0.2

+0.2

DDD

DDO

0.2

+2.25

DDA

analog supply current

DDD

digital supply current

DDO

output stages supply current

clk

= 40 MHz; C

= 20 pF;

ramp input

INL

integral non-linearity

clk

= 40 MHz; ramp input

0.5

0.75

LSB

DNL

differential non-linearity

clk

= 40 MHz; ramp input

0.25

0.5

LSB

clk(max)

maximum clock frequency

MHz

tot

total power dissipation

DDA

= V

DDD

= V

DDO

= 3.3 V

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA8790M

SSOP20

plastic shrink small outline package; 20 leads; body width 4.4 mm

SOT266-1

1996 Feb 21

Philips Semiconductors

Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter

TDA8790

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. The supply voltages V

DDA

, V

DDD

and V

DDO

may have any value between

0.3 V and +7.0 V provided that the supply

voltage

remains as indicated.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

DDA

analog supply voltage

note 1

0.3

+7.0

DDD

digital supply voltage

note 1

0.3

+7.0

DDO

output stages supply voltage

note 1

0.3

+7.0

supply voltage difference

DDA

DDD

1.0

+4.0

DDA

DDO

1.0

+4.0

DDD

DDO

1.0

+4.0

input voltage

referenced to V

SSA

0.3

+7.0

clk(p-p)

AC input voltage for switching
(peak-to-peak value)

referenced to V

SSD

DDD

output current

stg

storage temperature

+150

amb

operating ambient temperature

+75

junction temperature

+150

SYMBOL

PARAMETER

VALUE

UNIT

th j-a

thermal resistance from junction to ambient in free air

120

K/W

1996 Feb 21

Philips Semiconductors

Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter

TDA8790

CHARACTERISTICS
V

DDA

= V

to V

= 3.3 V; V

DDD

= V

to V

= 3.3 V; V

DDO

= V

to V

= 3.3 V; V

SSA

, V

SSD

and V

SSO

shorted together;

i(p-p)

= 1.84 V; C

= 20 pF; T

amb

= 0 to +70

C; typical values measured at T

amb

= 25

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

DDA

analog supply voltage

2.7

3.3

5.5

DDD

digital supply voltage

2.7

3.3

5.5

DDO

output stages supply voltage

2.5

3.3

5.5

supply voltage difference

DDA

DDD

0.2

+0.2

DDD

DDO

0.2

+2.25

DDA

analog supply current

DDD

digital supply current

DDO

output stages supply current

clk

= 40 MHz; ramp input;

= 20 pF

Inputs

LOCK INPUT

CLK (

REFERENCED TO

SSD

); see note 1

LOW level input voltage

0.3V

DDD

HIGH level input voltage

0.7V

DDD

3.6 V

0.6V

DDD

LOW level input current

clk

= 0.3V

DDD

HIGH level input current

clk

= 0.7V

DDD

input impedance

clk

= 40 MHz

input capacitance

clk

= 40 MHz

NPUT SLEEP

(

REFERENCED TO

SSD

); see Table 2

LOW level input voltage

0.3V

DDD

HIGH level input voltage

0.7V

DDD

3.6 V

0.6V

DDD

LOW level input current

= 0.3V

DDD

HIGH level input current

= 0.7V

DDD

(

ANALOG INPUT VOLTAGE REFERENCED TO

SSA

)

LOW level input current

= V

HIGH level input current

= V

input impedance

= 1 MHz

input capacitance

= 1 MHz

Reference voltages for the resistor ladder; see Table 1

reference voltage BOTTOM

1.1

1.2

reference voltage TOP

TOP

DDA

2.7

3.3

DDA

diff

differential reference voltage
V

1.5

2.1

2.7

ref

reference current

0.95

1996 Feb 21

Philips Semiconductors

Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter

TDA8790

LAD

resistor ladder

2.2

RLAD

temperature coefficient of the
resistor ladder

1860

ppm

4092

osB

offset voltage BOTTOM

note 2

170

osT

offset voltage TOP

note 2

170

i(p-p)

analog input voltage (peak-to-peak
value)

note 3

1.4

1.76

2.4

Outputs

IGITAL OUTPUTS

D0 (

REFERENCED TO

SSD

)

LOW level output voltage

= 1 mA

0.5

HIGH level output voltage

1 mA

DDO

0.5

DDO

output current in 3-state mode

0.4 V < V

< V

DDO

+20

Switching characteristics

LOCK INPUT

CLK; see Fig.4; note 1

clk(max)

maximum clock frequency

MHz

CPH

clock pulse width HIGH

CPL

clock pulse width LOW

Analog signal processing

INEARITY

INL

integral non-linearity

clk

= 40 MHz; ramp input;

see Fig.6

0.5

0.75

LSB

DNL

differential non-linearity

clk

= 40 MHz; ramp input;

see Fig.7

0.25

0.5

LSB

ANDWIDTH

clk

= 40 MHz)

analog bandwidth

full-scale sine wave;
note 4

MHz

75% full-scale sine wave;
note 4

MHz

50% full-scale sine wave;
note 4

MHz

small signal at mid scale;
V

10 LSB at

code 128; note 4

350

MHz

NPUT SET RESPONSE

clk

= 40 MHz; see Fig.8; note 5)

STLH

analog input settling time
LOW-to-HIGH

full-scale square wave

STHL

analog input settling time
HIGH-to-LOW

full-scale square wave

ARMONICS

; (f

clk

= 40 MH

; see Fig.9; note 6)

THD

total harmonic distortion

= 4.43 MHz

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Feb 21

Philips Semiconductors

Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter

TDA8790

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock

must not be less than 1 ns.

2. Analog input voltages producing code 0 up to and including 256:

a) V

osB

(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and

the reference voltage BOTTOM (V

) at T

amb

= 25

b) V

osT

(voltage offset TOP) is the difference between V

(reference voltage TOP) and the analog input which

produces data outputs equal to 256 at T

amb

= 25

IGNAL

NOISE RATIO

; see Fig.9; note 6

S/N

signal-to-noise ratio (full scale)

without harmonics;
f

clk

= 40 MHz;

= 4.43 MHz

FFECTIVE BITS

; see Fig.9; note 6

effective bits

clk

= 40 MHz

= 300 kHz

7.8

bits

= 4.43 MHz

7.3

bits

IFFERENTIAL GAIN

; see note 7

diff

differential gain

clk

= 40 MHz;

PAL modulated ramp

1.5

IFFERENTIAL PHASE

; see note 7

diff

differential phase

clk

= 40 MHz;

PAL modulated ramp

0.25

deg

Timing (f

clk

= 40 MHz; C

= 20 pF); see Fig.4; note 8

sampling delay time

output hold time

output delay time

DDO

= 4.75 V

DDO

= 3.15 V

DDO

= 2.7 V

3-state sleep mode delay times; see Fig.5

dZH

enable HIGH

dZL

enable LOW

dHZ

disable HIGH

dLZ

disable LOW

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Feb 21

Philips Semiconductors

Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter

TDA8790

3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities

of the converter reference resistor ladder (corresponding to output codes 0 and 255 respectively) are connected to
pins V

and V

via offset resistors R

and R

as shown in Fig.3.

a) The current flowing into the resistor ladder is

and the full-scale input range at the converter,

to cover code 0 to code 255, is

b) Since R

, R

and R

have similar behaviour with respect to process and temperature variation, the ratio

will be kept reasonably constant from part to part. Consequently variation of the output codes

at a given input voltage depends mainly on the difference V

and its variation with temperature and supply

voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching
between each of them is then optimized.

4. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.

No glitches greater than 2 LSBs, nor any significant attenuation is observed in the reconstructed signal.

5. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale

input (square-wave signal) in order to sample the signal and obtain correct output data.

6. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent

fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB

6.02 + 1.76 dB.

7. Measurement carried out using video analyser VM700A, where video analog signal is reconstructed through a DAC.

8. Output data acquisition: the output data is available after the maximum delay time of t

------------------------------------------

)

0.838

(

)

------------------------------------------

Fig.3 Explanation of note 3.

handbook, halfpage

RLAD

ROT

VRT

VRM

VRB

ROB

code 255

code 0

MGD284

1996 Feb 21

Philips Semiconductors

Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter

TDA8790

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
cases reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

Reflow soldering SSOP

Reflow soldering techniques are suitable for all SSOP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration:
45 minutes at 45

Wave soldering SSOP

Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.

The longitudinal axis of the package footprint must
be parallel to the solder flow and must incorporate
solder thieves at the downstream end.

Even with these conditions, only consider wave
soldering SSOP packages that have a body width of
4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds at between 270 and
320

1996 Feb 21

Philips Semiconductors

Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter

TDA8790

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

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SCDS47

All rights are reserved. Reproduction in whole or in part is prohibited without the
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other industrial or intellectual property rights.

Printed in The Netherlands

537021/1100/03/pp20

Date of release: 1996 Feb 21

Document order number:

9397 750 00677

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA8790

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA8790