1995 Dec 19

Philips Semiconductors

Preliminary specification

Sound fader control circuit

TEA6322T

FEATURES

Source selector for three stereo and one differential
stereo input for remote sources

The differential stereo input works optional as a fourth
stereo input and the common mode pin can be used as
well as an additional mono input

Interface for noise reduction circuits

Interface for external equalizer

Volume, balance and fader control

Output at volume I for external booster

Special loudness characteristic automatically controlled
in combination with volume setting

Bass and treble control

Mute control at audio signal zero crossing

Logic output to read mute status

Fast mute control via I

C-bus

Fast mute control via pin

C-bus control for all functions

Power supply with internal power-on reset

Power-down indication.

GENERAL DESCRIPTION

The sound fader control circuit TEA6322T is an I

C-bus

controlled stereo preamplifier for car radio hi-fi sound
applications.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

supply voltage

7.5

8.5

9.5

supply current

= 8.5 V

o(rms)

maximum output voltage level

= 8.5 V; THD

0.1%

2000

voltage gain

+20

step(vol)

step resolution (volume)

bass

bass control

+15

treble

treble control

+12

step(treble)

step resolution (bass, treble)

1.5

(S+N)/N

signal-plus-noise to noise ratio

= 2.0 V; G

= 0 dB;

unweighted

105

100

ripple rejection

r(rms)

200 mV;

f = 100 Hz; G

= 0 dB

CMRR

common mode rejection ratio
differential stereo input

TYPE NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TEA6322T

VSO40

plastic very small outline package; 40 leads

SOT158-1

1995 Dec 19

Philips Semiconductors

Preliminary specification

Sound fader control circuit

TEA6322T

PINNING

SYMBOL

PIN

DESCRIPTION

SDA

serial data input/output

MUTE

mute control input and output

DGND

digital ground

AGND

analog ground

OUTLR

output left rear

OUTLF

output left front

treble control capacitor left channel or input from external equalizer

B2L

bass control capacitor left channel or output to an external equalizer

B1L

bass control capacitor, left channel

OVL

output volume I, left channel

IVL

input volume I, left control part

ILL

input loudness, left control part

QSL

output source selector, left channel

IDL

input D left source

i.c.

COMM, common mode rejection adjust, centre position

ICL

input C left source

COM

common mode input / mono source input

IBL

input B left source

i.c.

COML, common mode rejection adjust, left position

IAL

input A differential source left

IAR

input A differential source right

i.c.

COMR, common mode rejection adjust, right position

IBR

input B right source

CAP

electronic filtering for supply

ICR

input C right source

ref

reference voltage (0.5 V

)

IDR

input D right source

QSR

output source selector right channel

ILR

input loudness right channel

IVR

input volume I, right control part

OVR

output volume I, right channel

B1R

bass control capacitor right channel

B2R

bass control capacitor right channel or output to an external equalizer

treble control capacitor right channel or input from an external equalizer

OUTRF

output right front

OUTRR

output right rear

n.c.

not connected

supply voltage

n.c.

not connected

SCL

serial clock input

1995 Dec 19

Philips Semiconductors

Preliminary specification

Sound fader control circuit

TEA6322T

FUNCTIONAL DESCRIPTION

The source selector allows either the source selection
between the differential stereo input (IAL, IAR and COM)
and three stereo inputs, or selection of four stereo inputs
and the mono input (COM). The maximum input signal
voltage is V

i(rms)

= 2 V. The outputs of the source selector

and the inputs of the following volume control parts are
available at pins 13 and 11 for the left channel and pins 28
and 30 for the right channel. This offers the possibility of
interfacing a noise reduction system.

The volume control part is following the source selector.
The signal phase from input volume control part to all
outputs is 180

Fig.2 Pin configuration.

handbook, halfpage

TEA6322T

MHA085

OUTLF

OUTLR

AGND

DGND

ICL

i.c.

IDL

IAL

i.c.

IBL

COM

QSL

IVL

ILL

OVL

B1L

B2L

MUTE

SDA

ICR

IDR

Vref

IAR

IBR

CAP

QSR

ILR

IVR

B1R

OVR

i.c.

B2R

OUTRF

OUTRR

VCC

SCL

n.c.

The volume control function is split into two sections:
volume I control block and volume II control block.

The control range of volume I is between +20 dB and

31 dB in steps of 1 dB. The volume II control range is

between 0 dB and

55 dB in steps of 1 dB. Although the

theoretical possible control range is 106 dB
(+20 to

86 dB), in practice a range of 86 dB

(+20 to

66 dB) is recommended. The gain/attenuation

setting of the volume I control block is common for both
channels.

The volume I control block operates in combination with
the loudness control. The filter is linear when the maximum
gain for the volume I control (+20 dB) is selected. The filter
characteristic increases automatically over a range of
32 dB down to a setting of

12 dB. That means the

maximum filter characteristic is obtained at

12 dB setting

of volume I. Further reduction of the volume does not
further influence the filter characteristic (see Fig.5). The
maximum selected filter characteristic is determined by
external components. The proposed application gives a
maximum boost of 17 dB for bass and 4.5 dB for treble.
The loudness may be switched on or off via I

C-bus control

(see Table 7).

The volume I control block has an output pin and is
followed by the bass control block. A single external
capacitor of 33 nF for each channel in combination with
internal resistors, provides the frequency response of the
bass control (see Fig.3). The adjustable range is between

15 and +15 dB at 40 Hz.

Both loudness and bass control result in a maximum bass
boost of 32 dB for low volume settings.

The treble control block offers a control range between

12 and +12 dB in steps of 1.5 dB at 15 kHz. The filter

characteristic is determined by a single capacitor of 5.6 nF
for each channel in combination with internal resistors
(see Fig.4).

The basic step width of bass and treble control is 3 dB. The
intermediate steps are obtained by switching 1.5 dB boost
and 1.5 dB attenuation steps.

The bass and treble control functions can be switched off
via I

C-bus. In this event the internal signal flow is

disconnected. The connections B2L and B2R are outputs
and TL and TR are inputs for inserting an external
equalizer.

1995 Dec 19

Philips Semiconductors

Preliminary specification

Sound fader control circuit

TEA6322T

The last section of the circuit is the volume II block. The
balance and fader functions are performed using the same
control blocks. This is realized by 4 independently
controllable attenuators, one for each output. The control
range of these attenuators is 55 dB in steps of 1 dB with an
additional mute step.

The circuit provides 3 mute modes:

1. Zero crossing mode mute via I

C-bus using

2 independent zero crossing detectors
(ZCM, see Tables 2 and 9).

2. Fast mute via MUTE pin.

3. Fast mute via I

C-bus either by general mute (GMU,

see Tables 2 and 9) or volume II block setting
(see Table 4).

The mute function is performed immediately if ZCM is
cleared (ZCM = 0). If the bit is set (ZCM = 1) the mute is
activated after changing the GMU bit. The actual mute
switching is delayed until the next zero crossing of the
audio frequency signal. As the two audio channels (left and
right) are independent, two comparators are built-in to
control independent mute switches.

To avoid a large delay of mute switching when very low
frequencies are processed or the output signal amplitude
is lower than the DC offset voltage a second I

C-bus

transmission is needed. Both transmissions have the
same data and the second transmission a delay time of
e.g. 100 ms. The first transmission starts the zero cross
circuit, but second transmission moves the mute switch
immediately if the circuit has no zero cross detected.

The mute function can also be controlled externally. If the
mute pin is switched to ground all outputs are muted
immediately (except the outputs volume left and right (OVL
and OVR) and hardware mute). This mute request
overwrites all mute controls via the I

C-bus for the time the

pin is held LOW. The hardware mute position is not stored
in the TEA6322T.

The MUTE pin can also be used as output. The mute pin
voltage is LOW when all outputs are in mute position.

For the turn on/off behaviour the following explanation is
generally valid. To avoid AF output caused by the input
signal coming from preceding stages, which produces
output during drop of V

, the mute has to be set, before

the V

will drop. This can be achieved by I

C-bus control

or by grounding the MUTE pin.

For use where is no mute in the application before turn off,
a supply voltage drop of more than 1

will result in a

mute during the voltage drop.

The power supply should include a V

buffer capacitor,

which provides a discharging time constant. If the input
signal does not disappear after turn off the input will
become audible after certain time. A 4.7 k

resistor

discharges the V

buffer capacitor, because the internal

current of the IC does not discharge it completely.

The hardware mute function is favourable for use in Radio
Data System (RDS) applications. The zero crossing mute
avoids modulation plops. This feature is an advantage for
mute during changing presets and/or sources (e.g. traffic
announcement during cassette playback).

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. Human body model: C = 100 pF; R = 1.5 k

; V

2 kV. Charge device model: C = 200 pF; R = 0

; V

500 V.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

supply voltage

voltage at pins 1, 2 and 5 to 40
to pins 3 and 4

amb

operating ambient temperature

+85

stg

storage temperature

+150

electrostatic handling

note 1

1995 Dec 19

Philips Semiconductors

Preliminary specification

Sound fader control circuit

TEA6322T

CHARACTERISTICS
V

= 8.5 V; R

= 600

; R

= 10 k

; C

= 2.5 nF; AC coupled; f = 1 kHz; T

amb

= 25

C; gain control G

= 0 dB; bass

linear; treble linear; fader off; balance in mid position; loudness off; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

supply voltage

7.5

8.5

9.5

supply current

internal DC voltage at inputs and
outputs

3.83

4.25

4.68

ref

internal reference voltage at pin 26

4.25

v(max)

maximum voltage gain

= 0

; R

o(rms)

output voltage level for

max

at the power output stage

THD

0.5%; see Fig.10

2000

start of clipping

THD = 1%; G

= 3 dB

2300

= 2 k

; C

= 10 nF;

THD = 1%

2000

i(rms)

input sensitivity

= 2000 mV; G

= 20 dB

200

roll-off frequency

KIN

= 220 nF;

KVL

= 220 nF; Z

= Z

i(min)

low frequency (

1 dB)

low frequency (

3 dB)

high frequency (

1 dB)

20000

KIN

= 470 nF;

KVL

= 100 nF; Z

= Z

i(typ)

low frequency (

3 dB)

channel separation

= 2 V; frequency range

250 Hz to 10 kHz

THD

total harmonic distortion

frequency range
20 Hz to 12.5 kHz

= 100 mV; G

= 20 dB

0.1

= 1 V; G

= 0 dB

0.05

0.1

= 2 V; G

= 0 dB

0.1

= 2 V; G

10 dB

0.1

ripple rejection

r(rms)

200 mV

f = 100 Hz

f = 40 Hz to 12.5 kHz

1995 Dec 19

Philips Semiconductors

Preliminary specification

Sound fader control circuit

TEA6322T

(S+N)/N

signal-plus-noise to noise ratio

unweighted;
20 Hz to 20 kHz (RMS);
V

= 2.0 V;

see Figs 6 and 7

105

CCIR468-2 weighted;
quasi peak; V

= 2.0 V

= 0 dB

= 12 dB

= 20 dB

differential input

= 0 dB

= 20 dB

CMRR

common mode rejection ratio
differential stereo input

no(rms)

noise output power (RMS value)
only contribution of TEA6322T;
power amplifier for 6 W

mute position; note 1

crosstalk

between bus

inputs and signal outputs

note 2

110

Source selector

input impedance

input isolation of one selected
source to any other input

f = 1 kHz

105

f = 12.5 kHz

i(rms)

maximum input voltage
(RMS value)

THD

0.5%; V

= 8.5 V

2.15

THD

0.5%; V

= 7.5 V

1.8

offset

DC offset voltage at source selector
output

by selection of any stereo inputs

by selection of differential input or
mono input

output impedance

120

output load resistance

output load capacity

2500

voltage gain, source selector

Control part (source selector disconnected; source resistance 600

)

input impedance volume input

100

150

200

input impedance loudness input

output impedance

120

output load resistance

output load capacity

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

bus p

(

)

o rms

(

)

---------------------------

log

1995 Dec 19

Philips Semiconductors

Preliminary specification

Sound fader control circuit

TEA6322T

i(rms)

maximum input voltage
(RMS value)

THD

0.5%

2.15

noise output voltage

CCIR468-2 weighted;
quasi peak

= 20 dB

110

220

= 0 dB

66 dB

mute position

tot

total continuous control range

106

recommended control range

step

step resolution

step error between any adjoining
step

0.5

attenuator set error

= +20 to

50 dB

51 to

66 dB

gain tracking error

= +20 to

50 dB

MUTE

att

mute attenuation

see Fig.9

100

110

offset

DC step offset between any
adjoining step

= 0 to

66 dB

0.2

= 20 to 0 dB

DC step offset between any step to
mute

= 0 to

66 dB

= 20 to 0 dB

= 0 to

31 dB;

loudness on

Volume I control and loudness

vol

continuous volume control range

voltage gain

+20

step

step resolution

Bmax

maximum loudness boost

loudness on; referred to
loudness off; boost is
determined by external
components

f = 40 Hz

f = 10 kHz

4.5

Bass control

bass

bass control, maximum boost

f = 40 Hz

maximum attenuation

f = 40 Hz

step

step resolution (toggle switching)

f = 40 Hz

1.5

step error between any adjoining
step

f = 40 Hz

0.5

offset

DC step offset in any bass position

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1995 Dec 19

Philips Semiconductors

Preliminary specification

Sound fader control circuit

TEA6322T

Notes to the characteristics

1. The indicated values for output power assume a 6 W power amplifier at 4

with 20 dB gain and a fixed attenuator

of 12 dB in front of it. Signal-to-noise ratios exclude noise contribution of the power amplifier.

2. The transmission contains: total initialization with MAD and subaddress for volume and 8 data words, see also

definition of characteristics, clock frequency = 50 kHz, repetition burst rate = 400 Hz, maximum bus signal
amplitude = 5 V (p-p).

3. The AC characteristics are in accordance with the I

C-bus specification. This specification, "

The I

C-bus and how to

use it", can be ordered using the code 9398 393 40011.

Treble control

treble

treble control, maximum boost

f = 15 kHz

maximum attenuation

f = 15 kHz

maximum boost

15 kHz

step

step resolution (toggle switching)

f = 15 kHz

1.5

step error between any adjoining
step

f = 15 kHz

0.5

offset

DC step offset in any treble position

Volume II, balance and fader control

continuous attenuation fader and
volume control range

53.5

56.5

step

step resolution

attenuation set error

1.5

Mute function

muteLOWI

input level for fast mute detection

1.0

input level for no mute detection

2.2

muteLOWO

output level for mute

1 mA; C

100 pF

0.4

muteHIGH

pull-up voltage

open collector

CCdrop

supply drop to V

CAP

for mute active

0.7

Power-on reset (when reset is active the GMU-bit (general mute) is set and the I

C-bus receiver is in

reset position)

increasing supply voltage start of
reset

2.5

end of reset

5.2

6.5

7.2

decreasing supply voltage start of
reset

4.2

5.5

6.2

Digital part (I

C-bus pins); note 3

HIGH level input voltage

9.5

LOW level input voltage

0.3

+1.5

HIGH level input current

= 0 to 9.5 V

+10

LOW level input current

+10

LOW level output voltage

= 3 mA

0.4

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1995 Dec 19

Philips Semiconductors

Preliminary specification

Sound fader control circuit

TEA6322T

Table 2

Definition of third byte after MAD and SAD

Notes

1. Zero crossing mode.

2. Switch loudness on/off.

3. Volume control.

4. Don't care bits (logic 1 during testing).

5. Fader control front right.

6. Fader control front left.

7. Fader control rear right.

8. Fader control rear left.

9. Bass control.

10. Treble control.

11. Mute control for all outputs except OVL and OVR (general mute).

12. Source selector control.

FUNCTION

BIT

MSB

LSB

Volume/loudness

ZCM

(1)

LOFF

(2)

(3)

Fader front right

FFR

FFR5

(5)

FFR4

(5)

FFR3

(5)

FFR2

(5)

FFR1

(5)

FFR0

(5)

Fader front left

FFL

FFL5

(6)

FFL4

(6)

FFL3

(6)

FFL2

(6)

FFL1

(6)

FFL0

(6)

Fader rear right

FRR

FRR5

(7)

FRR4

(7)

FRR3

(7)

FRR2

(7)

FRR1

(7)

FRR0

(7)

Fader rear left

FRL

FRL5

(8)

FRL4

(8)

FRL3

(8)

FRL2

(8)

FRL1

(8)

FRL0

(8)

Bass

BA4

(9)

BA3

(9)

BA2

(9)

BA1

(9)

BA0

(9)

Treble

TR4

(10)

TR3

(10)

TR2

(10)

TR1

(10)

TR0

(10)

Switch

GMU

(11)

SC2

(12)

SC1

(12)

SC0

(12)

1995 Dec 19

Philips Semiconductors

Preliminary specification

Sound fader control circuit

TEA6322T

Table 4

Volume II setting (fader and balance)

(dB)

DATA

FRR5

FRR4

FRR3

FRR2

FRR1

FRR0

FRL5

FRL4

FRL3

FRL2

FRL1

FRL0

FFL5

FFL4

FFL3

FFL2

FFL1

FFL0

FFR5

FFR4

FFR3

FFR2

FFR1

FFR0

1995 Dec 19

Philips Semiconductors

Preliminary specification

Sound fader control circuit

TEA6322T

Table 5

Bass setting

Notes

1. Recommended data word for step 0 dB.

2. Result of 1.5 dB boost and 1.5 dB attenuation.

3. The last four bass control data words mute the bass response.

4. The last bass control and treble control data words (00000) enable the external equalizer connection.

bass

(dB)

DATA

BA4

BA3

BA2

BA1

BA0

+15.0

+13.5

+15.0

+13.5

+15.0

+13.5

+12.0

+10.5

+9.0

+7.5

+6.0

+4.5

+3.0

+1.5

(1)

(2)

1.5

3.0

4.5

6.0

7.5

9.0

10.5

12.0

13.5

15.0

13.5

15.0

note 3

notes 3 and 4

1995 Dec 19

Philips Semiconductors

Preliminary specification

Sound fader control circuit

TEA6322T

Table 6

Treble setting

Notes

1. Recommended data word for step 0 dB.

2. Result of 1.5 dB boost and 1.5 dB attenuation.

3. The last eight treble control data words select treble output.

4. The last treble control and bass control data words (00000) enable the external equalizer connection.

treble

(dB)

DATA

TR4

TR3

TR2

TR1

TR0

+12.0

+10.5

+12.0

+10.5

+12.0

+10.5

+12.0

+10.5

+9.0

+7.5

+6.0

+4.5

+3.0

+1.5

(1)

(2)

1.5

3.0

4.5

6.0

7.5

9.0

10.5

12.0

note 3

notes 3 and 4

1995 Dec 19

Philips Semiconductors

Preliminary specification

Sound fader control circuit

TEA6322T

Loudness filter calculation example

Figure 15 shows the basic loudness circuit with an
external low-pass filter application. R1 allows an
attenuation range of 21 dB while the boost is determined
by the gain stage V

. Both result in a loudness control

range of +20 to

12 dB.

Defining f

ref

as the frequency where the level does not

change while switching loudness on/off. The external
resistor R3 for f

ref

can be calculated as:

. With G

21 dB and R1 = 33 k

R3 = 3.2 k

is generated.

For the low-pass filter characteristic the value of the
external capacitor C1 can be determined by setting a
specific boost for a defined frequency and referring the
gain to G

at f

ref

as indicated above.

For example: 3 dB boost at f = 1 kHz
G

= G

v(ref)

+ 3 dB =

18 dB; f = 1 kHz and C1 = 100 nF.

If a loudness characteristic with additional high frequency
boost is desired, an additional high-pass section has to be
included in the external filter circuit as indicated in the
block diagram. A filter configuration that provides
AC coupling avoids offset voltage problems.

-------

---------------------

-------------

(

)

-------

--------------------------------------------------------------

Fig.15 Basic loudness circuit.

handbook, halfpage

MHA092

CKVL

0 dB

33 k

1995 Dec 19

Philips Semiconductors

Preliminary specification

Sound fader control circuit

TEA6322T

PACKAGE OUTLINE

UNIT

(1)

(2)

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

inches

0.3
0.1

2.45
2.25

0.25

0.42
0.30

0.22
0.14

15.6
15.2

7.6
7.5

0.762

2.25

12.3
11.8

1.15
1.05

0.6
0.3

7
0

0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes

1. Plastic or metal protrusions of 0.4 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

1.7
1.5

SOT158-1

92-11-17
95-01-24

detail X

(A )

pin 1 index

0.012
0.004

0.096
0.089

0.017
0.012

0.0087
0.0055

0.61
0.60

0.30
0.29

0.03

0.089

0.48
0.46

0.045
0.041

0.024
0.012

0.004

0.2

0.008

0.004

0.067
0.059

0.010

10 mm

scale

VSO40: plastic very small outline package; 40 leads

SOT158-1

max.

2.70

0.11

1995 Dec 19

Philips Semiconductors

Preliminary specification

Sound fader control circuit

TEA6322T

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all VSO
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45

Wave soldering

Wave soldering techniques can be used for all VSO
packages if the following conditions are observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

The longitudinal axis of the package footprint must be
parallel to the solder flow.

The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

1995 Dec 19

Philips Semiconductors

Preliminary specification

Sound fader control circuit

TEA6322T

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

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For all other countries apply to: Philips Semiconductors,
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SCD47

All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.

Printed in The Netherlands

513061/1100/01/pp36

Date of release: 1995 Dec 19

Document order number:

9397 750 00535

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