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Электронный компонент: PJ339CD

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PJ339
Quad Voltage Compartor
1-6
2003/10.ver.A

DIP-14 SOP-14

he comparator is designed for use in level detection,
low level sensingand memory application in
Consumer Automotive and industria electronic applications.


Single or Spit Supply Operation
Low input bnias current - 25 nA(T
YP
)
Low input offset current - 5.0 nA(T
YP
)
Low input offset voltage - 1.0 mV (T
YP
)
Input common-made voltage range to gnd
Low output saturation voltage - 130mV(T
YP
) @4.0mA
TTL and CMOS compatible




















T
Device Operating
Temperature Package
PJ339CS SOP-14
PJ339CD
-20+85
DIP-14
Rating Symbol Value
Unit
Power Supply Voltage
V
CC
+36
or
18 Vdc
Input Differential Voltage Range
V
IDR
36
Vdc
Input Common Mode Voltage Range
V
ICR
-0.3 to V
CC
Vdc
Output Short-Circuit to Gnd
(Note1)
I
SC
Continuous
mA
Input Current(Vin -0.3 Vdc)
(Note2)
I
in
50
mA
Power Dissipation@T
A
=25
Ceramic Package
Derate above 25
Plastic Package
Derate above 25
P
D
1.0
8.0
1.0
8.0
Watts
mW/
C
Watts
mW/
C
Storage Temperature Range
T
stg
-65
to+150
FEATURES
ORDERING INFORMATION
Pin : 1. Output 2 8. Input 3
2. Output 1 9. +Input 3
3. Vcc 10. Input 4
4. Input 1 11. +Input 4
5. +Input 1 12. Gnd
6. Input 2 13. Output 4
7. +Input 2 14. Output 3
MAXIMUM RATINGS
PJ339
Quad Voltage Compartor
2-6
2003/10.ver.A



Note :1. The maximum output current may be as high as 20mA, independent of the magnitude of V
CC
Output short circuits to V
CC
can cause excessive heating and eventual destruction.
2. This magnitude of input current will only occur if the leads are driven more negative than ground or the negative
supply voltage. This is due to the input PNP collector base junction becoming forward biased, acting as an input clamp
diode. There is also a lateral PNP parasitic transistor action which can cause the output voltage of the comparators to go
to the V
CC
voltage level (or ground if overdrive is large)during the time that an input is driven negative. This will not
destroy the device when limited to the max rating and normal output states will recover when the inputs become
ground or negative supply.
3. At the output switch point, V
O
= 1.4 Vdc, R
S
100, 5.0 Vdc V
CC
30 Vdc, with the inputs over the full common-
mode range (o Vdc to V
CC
-1.5 Vdc).
4. The bias current flows out of the inputs due to the PNP input stage. This current is virtually constant, independent of
the output state.
5. The response time specified is for a 100 mV input step with 5.0 mV overdrive For larger signals, 300 ns is typical.
6. Positive excursions of input voltage may exceed the power supply level. As long as one of the inputs remain within the
common-mode range, the comparator will provide the proper output state.
Characteristics Symbol Min Typ Max Unit
Input offset voltage (Note 3)
V
IO
--
+2.0
+5.0
mVdc
Input Bias Current (Note 3,4)
(Output in Linear Range)
I
IB
--
25
250
nA
Input Offset Current (Note 3)
I
IO
--
5.0
50
nA
Input Common-Mode Voltage Range (Note 6)
V
ICR
0 --
V
CC
-1.5 V
Supply Current
R
L
=
(For All Comparators)
R
L
=
, V
CC
=30Vdc
I
CC
--
--
0.8
--
2.0
--
mA
Voltage Gain R
L
15K , V
CC
= 15Vdc
A
V
--
200
--
V/mV
Large Signal Response Time
V1 = TTL logic Swing,
V
ref
= 1.4 Vdc, V
RL
= 5.0Vdc, RL = 5.1 K
-- --
300 -- ns
Response Time (Note 6) V
RL
= 5.0 Vdc, R
L
=5.1 K
--
--
1.3
--
s
Output Sink Current V
I
(-)
+1.0 Vdc, V
I
(+) = 0, V
O
15Vdc I
sink
6.0
16
-- mA
Saturation Voltage
V
I
(-)
+1.0 Vdc, V
I
(+) = 0, I
sink
4.0 mA
V
sat
--
130
400 mV
Output Leakage Current
V
I
(+)
+1.0 Vdc, V
I
(-) = 0, V
O
=+5.0Vdc
I
OL
--
0.1
-- nA
Input Offset Voltage (Note 3)
T
A
=
-20 to +85
V
IO
-- --
+9.0
mVdc
Input Bias Current (Note 3 4) (Output in Linear Range)
T
A
=
-20
to +85
I
IB
--
--
400
nA
Input Offset Current (Note 3)
T
A
=
-20
to +85
I
IO
--
--
150
nA
Input Common-Mode Voltage Range
T
A
=
-20
to +85
V
ICR
0 --
V
CC
-2.0 V
Saturation Voltage V
I
(-)
+ 1.0 Vdc, V
I
(+) = 0, I
sink
4.0mA
T
A
=
-20
to +85
V
sat
-- --
700
mV
Output Lezkage Current
V
I
(+)
+1.0 Vdc, V
I
(-) = 0, V
O
= 30 Vdc
T
A
=
-20 to +85
I
OL
--
--
1.0
A
Differential Input Voltage ALLV
I
0 Vdc (Note 6)
T
A
=-20
to +85
V
ID
-- --
V
CC
Vdc
ELECTRICAL CHARACTERISTICS (V
CC
= 5.0Vdc,T
A
= 25
unless otherwise noted.)
PJ339
Quad Voltage Compartor
3-6
2003/10.ver.A


FIGURE 1- CIRCUIT SCHEMATIC
(Diagram shown is for 1 comparator)













FIGURE 2 - INVERTING COMPARATOR WITH FIGURE 3 - NON-INVERTING COMPARATOR
HYSTERESIS WITH HYSTERESIS


















PJ339
Quad Voltage Compartor
4-6
2003/10.ver.A

FIGURE 4 - NORMALIZED INPUT OFFSET FIGURE 5 - INPUT BIAS CURRENT

VOLTAGE
















FIGURE 6 - OUTPUT SINK CURRENT versus
OUTPUT SATURATION VOLTAGE
















FIGURE 7- FRIVING LOGIC FIGURE 8 - SQUAREWAVE OSCILLATOR


















PJ339
Quad Voltage Compartor
5-6
2003/10.ver.A
APPLICATIONS INFORMATION
This quad comparator feature high gain, wide bandwidth characteristics. This gives the device oscillation tendencies if the
outputs are capacitively coupled to the inputs via stray capacitance. This oscillation manifests itself during output transitions
(V
OL
to V
OH
). To alleviate this situation input resistors
10
K
should be used. The addition of positive feedback (
10
mV) is also recommended.
It is good design practice to ground all unused input pins.
Differential input voltages may be larger than supply voltage without damaging the comparator inputs.
Voltages more negative than -300mV should not be used.

FIGURE 9 - ZERO CROSSING DETECTOR
( Single Supply )













FIGURE 10 - ZERO CROSSING DETECTOR
( Split Supplies)
VINmin=0.4V peak for 1.phase dissfortion((-))
















D1 prevents input from going negative by more than 06V
R1R2R3
10
5
3
R
R
for small error in zero crossing