N
et
C
hip
Technology, Inc.
335 Pioneer Way
Mt View, California 94041
(650) 526-1490 Fax (650) 526-1494
e-mail: sales@netchip.com
Internet: www.netchip.com
NET2270 USB 2.0 Interface Controller
Doc #: 605-0139-0350
Revision: 3.6
Date: April 17, 2003
Specification
NET2270 USB Interface Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
http://www.netchip.com
Rev 3.6, April 17, 2003
2
This document contains material that is confidential to NetChip. Reproduction without the express written consent
of NetChip is prohibited. All reasonable attempts were made to ensure the contents of this document are accurate,
however no liability, expressed or implied is guaranteed. NetChip reserves the right to modify this document,
without notification, at any time.
Revision History
Revision
Issue Date
Comments
1.0
February 6, 2001
Revision 1 silicon initial release
1.1
March 21, 2001
Update sample schematic, register, and functional descriptions
2.0
April 30, 2001
Revision 2 silicon initial release
3.0
June 12, 2001
Revision 3 silicon initial release
3.1
September 7, 2001
Update some descriptions and bus timing
3.2
December 17, 2001
Minor changes
3.3
March 27, 2002
Modifications to sample schematic
3.4
April 5, 2002
Modifications to Ambient Operating Temperature
3.5
January 31, 2003
Re-arrange chapters, update electrical specifications
3.6
April 17, 2003
Update physical pin assignment diagram
Specification
NET2270 USB Interface Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
http://www.netchip.com
Rev 3.6, April 17, 2003
3
NET2270 USB Interface Controller
1
INTRODUCTION .................................................................................................................................7
1.1
F
EATURES
.........................................................................................................................................7
1.2
O
VERVIEW
........................................................................................................................................7
1.3
NET2270 B
LOCK
D
IAGRAM
.............................................................................................................9
1.4
NET2270 T
YPICAL
S
YSTEM
B
LOCK
D
IAGRAMS
..............................................................................9
1.4.1
Example connections to NET2270.........................................................................................11
1.4.2
Example Part Numbers..........................................................................................................12
1.4.3
General PCB Layout Guidelines ...........................................................................................12
1.4.3.1
USB Differential Signals ..................................................................................................................12
1.4.3.2
Analog VDD (power)........................................................................................................................12
1.4.3.3
Analog VSS (ground)........................................................................................................................13
1.4.3.4
Decoupling Capacitors......................................................................................................................13
1.4.3.5
EMI Noise Suppression ....................................................................................................................13
1.5
T
ERMINOLOGY
...............................................................................................................................14
2
PIN DESCRIPTION............................................................................................................................15
2.1
D
IGITAL
P
OWER
& G
ROUND
(9
PINS
) .............................................................................................15
2.2
USB T
RANSCEIVER
(15
PINS
).........................................................................................................16
2.3
C
LOCKS
, R
ESET
, M
ISC
. (9
PINS
).....................................................................................................17
2.4
L
OCAL
B
US
P
IN
D
ESCRIPTIONS
(31
PINS
) .......................................................................................18
2.5
P
HYSICAL
P
IN
A
SSIGNMENT
...........................................................................................................19
3
RESET AND INITIALIZATION ......................................................................................................20
3.1
O
VERVIEW
......................................................................................................................................20
3.2
RESET# P
IN
..................................................................................................................................20
3.3
R
OOT
P
ORT
R
ESET
..........................................................................................................................20
3.4
R
ESET
S
UMMARY
...........................................................................................................................20
4
LOCAL BUS INTERFACE................................................................................................................21
4.1
I
NTRODUCTION
...............................................................................................................................21
4.2
R
EGISTER
A
DDRESSING
M
ODES
.....................................................................................................21
4.2.1
Direct Address Mode .............................................................................................................21
4.2.2
Indirect Address Mode...........................................................................................................21
4.2.3
Multiplexed Address Mode ....................................................................................................21
4.3
C
ONTROL
S
IGNAL
D
EFINITIONS
......................................................................................................21
4.4
B
US
W
IDTH
/ B
YTE
A
LIGNMENT
....................................................................................................21
4.5
I/O T
RANSACTIONS
........................................................................................................................22
4.5.1
Non-Multiplexed I/O Read.....................................................................................................22
4.5.2
Multiplexed I/O Read.............................................................................................................22
4.5.3
Non-Multiplexed I/O Write ....................................................................................................23
4.5.4
Multiplexed I/O Write ............................................................................................................23
4.5.5
I/O Performance ....................................................................................................................24
4.5.5.1
Non-Multiplexed Read Transaction ..................................................................................................24
4.5.5.2
Multiplexed Read Transaction ..........................................................................................................24
4.5.5.3
Non-Multiplexed Write Transaction .................................................................................................24
4.5.5.4
Multiplexed Write Transaction .........................................................................................................24
4.6
DMA T
RANSACTIONS
....................................................................................................................25
4.6.1
DMA Read .............................................................................................................................25
4.6.2
DMA Write.............................................................................................................................26
4.6.3
DMA Split Bus Mode .............................................................................................................28
4.6.4
Terminating DMA Transfers..................................................................................................28
Specification
NET2270 USB Interface Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
http://www.netchip.com
Rev 3.6, April 17, 2003
4
4.6.5
DMA Performance.................................................................................................................28
4.6.5.1
DMA Read........................................................................................................................................28
4.6.5.2
DMA Write .......................................................................................................................................28
5
USB FUNCTIONAL DESCRIPTION...............................................................................................29
5.1
USB I
NTERFACE
.............................................................................................................................29
5.2
USB P
ROTOCOL
.............................................................................................................................29
5.2.1
Tokens....................................................................................................................................29
5.2.2
Packets...................................................................................................................................29
5.2.3
Transaction............................................................................................................................30
5.2.4
Transfer .................................................................................................................................30
5.3
A
UTOMATIC
R
ETRIES
.....................................................................................................................30
5.3.1
Out Transactions ...................................................................................................................30
5.3.2
In Transactions ......................................................................................................................30
5.4
P
ING
F
LOW
C
ONTROL
.....................................................................................................................30
5.5
P
ACKET
S
IZES
.................................................................................................................................30
5.6
USB E
NDPOINTS
............................................................................................................................31
5.6.1
Control Endpoint - Endpoint 0 ..............................................................................................31
5.6.1.1
Control Write Transfer......................................................................................................................31
5.6.2
Control Write Transfer Details..............................................................................................32
5.6.2.1
Control Read Transfer.......................................................................................................................33
5.6.2.2
Control Read Transfer Details ..........................................................................................................33
5.6.3
Isochronous Endpoints ..........................................................................................................34
5.6.3.1
Isochronous Out Transactions...........................................................................................................35
5.6.3.2
Isochronous In Transactions .............................................................................................................36
5.6.4
Bulk Endpoints.......................................................................................................................37
5.6.4.1
Bulk Out Transactions ......................................................................................................................37
5.6.4.2
Bulk In Endpoints .............................................................................................................................38
5.6.5
Interrupt Endpoints................................................................................................................39
5.6.5.1
Interrupt Out Transactions ................................................................................................................39
5.6.5.2
Interrupt In Endpoints .......................................................................................................................39
5.7
P
ACKET
B
UFFERS
...........................................................................................................................40
5.7.1
IN Endpoint Buffers ...............................................................................................................40
5.7.2
OUT Endpoint Buffers ...........................................................................................................41
5.8
USB T
EST
M
ODES
..........................................................................................................................42
6
INTERRUPT AND STATUS REGISTER OPERATION...............................................................43
6.1
I
NTERRUPT
S
TATUS
R
EGISTERS
(IRQSTAT0, IRQSTAT1)...........................................................43
6.2
E
NDPOINT
R
ESPONSE
R
EGISTERS
(EPRSP_CLR, EPRSP_SET)....................................................43
6.3
E
NDPOINT
S
TATUS
R
EGISTER
(EP_STAT0, EP_STAT1) ..............................................................43
7
POWER MANAGEMENT.................................................................................................................44
7.1
S
USPEND
M
ODE
..............................................................................................................................44
7.1.1
The Suspend Sequence...........................................................................................................44
7.1.2
Host-Initiated Wake-Up.........................................................................................................45
7.1.3
Device-Remote Wake-Up.......................................................................................................45
7.1.4
Resume Interrupt ...................................................................................................................45
7.2
NET2270 P
OWER
C
ONFIGURATION
...............................................................................................45
7.2.1
Self-Powered Device..............................................................................................................45
7.2.2
Low-Power Modes.................................................................................................................45
7.2.2.1
USB Suspend (Unplugged from USB)..............................................................................................45
7.2.2.2
Power-On Standby ............................................................................................................................46
8
CONFIGURATION REGISTERS.....................................................................................................47
8.1
R
EGISTER
D
ESCRIPTION
.................................................................................................................47
Specification
NET2270 USB Interface Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
http://www.netchip.com
Rev 3.6, April 17, 2003
5
8.2
R
EGISTER
S
UMMARY
......................................................................................................................47
8.2.1
Main Control Registers..........................................................................................................47
8.2.2
USB Control Registers...........................................................................................................48
8.2.3
Endpoint Registers.................................................................................................................48
8.3
N
UMERIC
R
EGISTER
L
ISTING
..........................................................................................................49
8.4
M
AIN
C
ONTROL
R
EGISTERS
...........................................................................................................50
8.4.1
(Address 00h; REGADDRPTR) Indirect Register Address Pointer ......................................50
8.4.2
(Address 01h; REGDATA) Indirect Register Data................................................................50
8.4.3
(Address 02h; IRQSTAT0) Interrupt Status Register (low byte)............................................50
8.4.4
(Address 03h; IRQSTAT1) Interrupt Status Register (high byte) ..........................................51
8.4.5
(Address 04h; PAGESEL) Endpoint Page Select Register ....................................................51
8.4.6
(Address 1Ch; DMAREQ) DMA Request Control Register...................................................52
8.4.7
(Address 1Dh; SCRATCH) Scratchpad Register...................................................................52
8.4.8
(Address 20h; IRQENB0) Interrupt Enable Register (low byte) ...........................................53
8.4.9
(Address 21h; IRQENB1) Interrupt Enable Register (high byte) ..........................................53
8.4.10
(Address 22h; LOCCTL) Local Bus Control Register...........................................................54
8.4.11
(Address 23h; CHIPREV) Silicon Revision Register.............................................................54
8.5
USB C
ONTROL
R
EGISTERS
.............................................................................................................55
8.5.1
(Address 18h; USBCTL0) USB Control Register (low byte) .................................................55
8.5.2
(Address 19h; USBCTL1) USB Control Register (high byte)................................................55
8.5.3
(Address 1Ah; FRAME0) Frame Counter (low byte) ............................................................55
8.5.4
(Address 1Bh; FRAME1) Frame Counter (high byte)...........................................................55
8.5.5
(Address 30h; OURADDR) Our Current USB Address ........................................................56
8.5.6
(Address 31h; USBDIAG) USB Diagnostic Register.............................................................56
8.5.7
(Address 32h; USBTEST) USB Test Modes...........................................................................56
8.5.8
(Address 33h; XCVRDIAG) Transceiver Diagnostic Register ..............................................57
8.5.9
(Address 40h; SETUP0) Setup Byte 0....................................................................................57
8.5.10
(Address 41h; SETUP1) Setup Byte 1....................................................................................58
8.5.11
(Address 42h; SETUP2) Setup Byte 2....................................................................................58
8.5.12
(Address 43h; SETUP3) Setup Byte 3....................................................................................58
8.5.13
(Address 44h; SETUP4) Setup Byte 4....................................................................................58
8.5.14
(Address 45h; SETUP5) Setup Byte 5....................................................................................58
8.5.15
(Address 46h; SETUP6) Setup Byte 6....................................................................................59
8.5.16
(Address 47h; SETUP7) Setup Byte 7....................................................................................59
8.6
E
NDPOINT
R
EGISTERS
.....................................................................................................................60
8.6.1
(Address 05h; EP_DATA) Endpoint Data .............................................................................60
8.6.2
(Address 06h; EP_STAT0) Endpoint Status Register (low byte) ...........................................60
8.6.3
(Address 07h; EP_STAT1) -- Endpoint Status Register (high byte) ......................................61
8.6.4
(Address 08h; EP_TRANSFER0) Transfer Count Register (Byte 0) .....................................62
8.6.5
(Address 09h; EP_TRANSFER1) Transfer Count Register (Byte 1) .....................................62
8.6.6
(Address 0Ah; EP_TRANSFER2) Transfer Count Register (Byte 2).....................................62
8.6.7
(Address 0Bh; EP_IRQENB) Endpoint Interrupt Enable Register .......................................63
8.6.8
(Address 0Ch: EP_AVAIL0) Endpoint Available Count (low byte) ......................................63
8.6.9
(Address 0Dh: EP_AVAIL1) Endpoint Available Count (high byte).....................................63
8.6.10
(Address 0Eh; EP_RSPCLR) Endpoint Response Register Clear .........................................64
8.6.11
(Address 0Fh; EP_RSPSET) Endpoint Response Register Set..............................................65
8.6.12
(Address 28h; EP_MAXPKT0) Max Packet Size (low byte)..................................................65
8.6.13
(Address 29h; EP_MAXPKT1) Max Packet Size (high byte) ................................................65
8.6.14
(Address 2Ah; EP_CFG) Endpoint Configuration Register..................................................66
9
USB STANDARD DEVICE REQUESTS .........................................................................................67
9.1
C
ONTROL
`R
EAD
' T
RANSFERS
........................................................................................................68
9.1.1
Get Device Status...................................................................................................................68
9.1.2
Get Interface Status ...............................................................................................................68
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