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FAS366U
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QLogic Corporation
Data Sheet
FAS366U
Fast Architecture SCSI Processor
Features
H
Compliance with ANSI draft Fast20 standard
H
Compliance with ANSI X3T10/855D SCSI3
parallel interface (SPI) standard
H
Compliance with ANSI SCSI configured
automatically (SCAM) protocol levels 1 and 2
H
Sustained SCSI data transfer rates of up to:
h
40 Mbytes/sec synchronous (ultra and wide
SCSI)
h
14 Mbytes/sec asynchronous (wide SCSI)
H
Synchronous DMA timing; DMA speed of
50 Mbytes/sec
H
REQ and ACK programmable assertion and
deassertion control
H
Support for hot plugging
H
Target and initiator block transfer sequences
H
Bus idle timer
H
Splitbus architecture
H
Pipelined command structure
H
Onchip, singleended SCSI transceivers
(48mA drivers)
H
Initiator and target roles
H
Active negation
H
16bit recommand counter
H
Differential mode
H
SCSI bus reset watchdog timer
Figure 1. FAS366U Block Diagram
SEQUENCERS
FIFO
SCSI
CONTROL
SCSI
DATA
CLOCK
CONVERSION
DB BUS
CONFIGURATION
SYNC OFFSET/
SYNC ASSERT/
SYNC DEASSERT
SYNC PERIOD
SEQUENCE
STEP
STATUS
INTERRUPT
COMMAND
PARITY (2)
DATA (16)
RECOMMAND
COUNTER
BLOCK
REGISTERS
TRANSFER
COUNTER
PAD BUS
SEL/RESEL
BUS ID
SEL/RESEL
TIMEOUT
TRANSFER
COUNT
TEST (SCAM)
QLogic Corporation
2
FAS366U
5336658001 B
Product Description
The FAS366U is a new addition to the QLogic fast
architecture SCSI processor (FAS) chip family. The
FAS366U supports advanced SCSI3 options including
ultra SCSI synchronous transfers. Also included is the
advanced SCAM level 2 SCSI controller core.
The FAS366U is a singlechip controller for use in
host and peripheral applications. It is firmware and
pinout compatible with the QLogic FAS366 chip. The
FAS366U block diagram is shown in figure 1.
The FAS366U implements QLogic's new SCSI
target and initiator block transfer sequences. The block
sequences reduce firmware overhead and are composed
of the following new commands: Target Block
Sequence (including the bus idle timer), Initiator Block
Sequence, Load/Unload Block Registers sequences,
Abort Block Sequence, and Disconnect Abort Block
Sequence.
The FAS366U supports both singleended and
differential mode SCSI operations and operates in
initiator and target roles. The FAS366U has been
optimized for interaction with a DMA controller and
the controlling microprocessor.
The versatile splitbus architecture supports various
microprocessor and DMA bus configurations. A
separate 8bit microprocessor bus (PAD) provides
access to all internal registers, and a 16bit DMA bus
(DB) provides a path for DMA transfers through the
FIFO. Each bus is protected by a parity bit (bytewide
parity) to improve data integrity. During data transfer,
the microprocessor has instant access to status and has
the ability to execute commands.
SCAM Implementation
The FAS366U supports levels 1 and 2 of the SCAM
protocol. Refer to the latest revision of X3T10/855D,
Annex B. The SCAM protocol requires direct access
and control over the SCSI data bus and several of the
SCSI phase and control signals. The majority of the
SCAM protocol can be implemented in firmware at
microprocessor speeds. The following SCAM features
are supported in the hardware:
H
Arbitration without an ID
H
Slow response to selection with an unconfirmed ID
H
Detection of and response to SCAM selection
Fast DMA Protocol
The fast DMA protocol is required for supporting
the full bandwidth of ultra, wide SCSI.
The DREQ signal initiates DMA transfers and runs
asynchronous to the user's clock. For read operations,
DACK acts as a chip select to enable the FAS366U
drivers onto the DMA bus. The chip select role of
DACK helps support the burst timing of fast DMA
mode. DACK selects the FAS366U after DREQ is
asserted and is removed either after DREQ is deasserted
or when the DMA transfer is paused.
DBRD requests data from the FAS366U and DBWR
validates data sent to the FAS366U. Data is valid
around the rising (trailing) edge of DBRD or DBWR.
DMA transfers are terminated by deasserting
DREQ. Deassertion of DREQ is triggered by the
leading edge of DBRD or DBWR (see timing
parameter t1 in figures 2 and 3) under any of the
following conditions:
H
To prevent FIFO overrun conditions
H
To prevent FIFO underrun conditions
H
When the required amount of data has been
transferred
When DREQ is deasserted, the FAS366U ignores
DBRD and DBWR. Data transfers do not take place
unless DREQ is asserted.
The FAS366U does not generate parity on the
incoming DMA bus. Correct parity must always be
supplied with the data.
The DMA interface signals are given in table 1.
DMA timing is given in table 2 and figures 2 and 3.
Table 1. DMA Interface Signals
Pin
Type
Active
Level
Description
DREQ
O
High
The FAS366U DMA
request line begins and
ends DMA cycles.
DACK
I
Low
The acknowledge is used
as a chip select to activate
FAS366U drivers and to
acknowledge acceptance of
DREQ.
DBRD
I
Rising edge
The trailing edge accepts
data from the FAS366U for
DMA read operations.
DBWR
I
Rising edge
The trailing edge strobes
data into the FAS366U
FIFO on DMA write
operations.
DB150
I/O
N/A
This is the DMA data bus.
QLogic Corporation
5336658001 B
FAS366U
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Table 2. DMA Timing
Symbol
Description
Minimum (ns)
Maximum (ns)
Note
t1
DBRD/DBWR low to DREQ low
12
a
t2
DACK high to DREQ high
TBD
t3
DACK high to DACK low
40
tR1
DACK low to DBRD low
tR5
tR2
DBRD assertion pulse width
15
tR3
DBRD deassertion pulse width
15
tR4
DBRD high to DACK high
tR3
b
tR5
DBRD low to DBRD low cycle
40
tR6
DACK low to DB150 read on
2
c
tR7
DACK high to DB150 read off
15
c
tR8
DBRD low to DB150 read valid
15
c
tR9
DBRD low to DB150 read invalid
0
c
tW1
DACK low to DBWR low
tW5
tW2
DBWR assertion pulse width
15
tW3
DBWR deassertion pulse width
15
tW4
DBWR high to DACK high
tW3
d
tW5
DBWR low to DBWR low cycle
40
tW6
DB150 write setup to DBWR high
10
tW7
DB150 write hold from DBWR high
5
Table Notes
a
DREQ loading is 30 pf.
b
DBRD low to DACK high
wtR5
c
Data loading is 50 pf.
d
DBWR low to DACK high
wtW5
QLogic Corporation
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FAS366U
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Interfaces
The FAS366U interfaces consist of the microprocessor bus and the SCSI bus. Pins that support these interfaces
and other chip operations are shown in figure 4.
Figure 4. FAS366U Functional Signal Grouping
RD
MICROPROCESSOR
INTERFACE
RESETO
RESETI
RESET
VDD
VSS
POWER
AND GROUND
CLK
CLOCK
RST
SEL
BSY
ATN
MSG
CD
IO
REQ
ACK
SCSI
INTERFACE
FAS366U
INT
CS
DIFFERENTIAL
MODE SUPPORT
DIFFM
DIFFSENS
ESDP10
ERST
ESEL
EBSY
ETGS
EIGS
DREQ
DMA AND
MICROPROCESSOR
INTERFACE
A30
WR
ESD150
PAD70
PADP
MODE10
BUS CONFIGURATION
DBWR
DBRD
DACK
DBP10
SDP10
SD150
DB150
PAUSE
4245
75, 63
14
SEE NOTE
15
57
13
55
3
61
91
62
9297, 99, 100
56
10
33
8
9
5
4
127, 117
SEE NOTE
1
2
88
SEE NOTE
SEE NOTE
31
32
58
86, 48
SEE NOTE
38
36
39
19
20
11
47
41, 40
NOTE:
DB150
=
126122, 120118, 116, 115, 113108
ESD150
=
101104, 2124, 4952, 8285
NO CONNECT
=
16, 37, 53, 60, 67, 90, 105
SD150
=
76, 7880, 2628, 30, 64, 65, 6870, 7274
VDD
=
7, 12, 17, 35, 87, 106
VSS
=
6, 18, 25, 29, 34, 46, 54, 59, 66, 71, 77, 81, 89, 98, 107, 114, 121, 128
NO CONNECT
SEE NOTE
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