53368-580-00 A
FAS368M
1
Features
s
Compliance with ANSI X3T10/1142D SCSI
Parallel Interconnect-2 (SPI-2) standard
s
Compliance with ANSI SCSI configured
automatically (SCAM) protocol levels 1 and 2
s
Sustained SCSI data transfer rates of up to:
40 Mbytes/sec synchronous (Ultra and wide
SCSI)
14 Mbytes/sec asynchronous (wide SCSI)
s
Synchronous DMA timing; DMA speed of
50 Mbytes/sec
s
REQ and ACK programmable assertion and
deassertion control
s
Support for hot plugging
s
Target and initiator block transfer sequences
s
Bus idle timer
s
Split-bus architecture
s
Pipelined command structure
s
On-chip, single-ended SCSI transceivers
(48-mA drivers)
s
On-chip, multimode, low voltage differential
(LVD) drivers
s
On-chip differential sense decoder
s
Initiator and target roles
s
Active negation
s
16-bit recommand counter
s
Differential mode
s
SCSI bus reset watchdog timer
Product Description
The FAS368M is a new addition to the QLogic fast
architecture SCSI processor (FAS) chip family. The
FAS368M supports internal multimode LVD and
single-ended (SE) transceivers, which allow the chip to
support LVD and SE operations in initiator and target roles.
The FAS368M is a single-chip controller for use in host
and peripheral applications. To ensure firmware
compatibility and provide FAS366U customers a seamless
upgrade path, the FAS368M uses the same SCSI core,
foundry, and process as the FAS366U. Note that the
FAS368M package size, pin out, and transceivers differ
from the FAS366U. The FAS368M block diagram is shown
in figure 1.
The FAS368M implements QLogic's new SCSI target
and initiator block transfer sequences. The block sequences
reduce firmware overhead and are composed of the
following new commands: Target Block Sequence
(including the bus idle timer), Initiator Block Sequence,
Load/Unload Block Registers sequences, Abort Block
Sequence, and Disconnect Abort Block Sequence.
The FAS368M supports both single-ended and
differential mode SCSI operations and operates in initiator
and target roles. The FAS368M has been optimized for
interaction with a DMA controller and the controlling
microprocessor.
The versatile split-bus architecture supports various
microprocessor and DMA bus configurations. A separate
8-bit microprocessor bus (PAD) provides access to all
internal registers, and a 16-bit DMA bus (DB) provides a
path for DMA transfers through the FIFO. Each bus is
protected by a parity bit (byte-wide parity) to improve data
integrity. During data transfer, the microprocessor has
instant access to status and has the ability to execute
commands.
SCAM Implementation
The FAS368M supports levels 1 and 2 of the SCAM
protocol. Refer to the latest revision of X3T10/855D,
Annex B. The SCAM protocol requires direct access and
control over the SCSI data bus and several of the SCSI
phase and control signals. The majority of the SCAM
protocol can be implemented in firmware at
microprocessor speeds. The following SCAM features are
supported in the hardware:
s
Arbitration without an ID
s
Slow response to selection with an unconfirmed ID
s
Detection of and response to SCAM selection
QLogic Corporation
FAS368M Fast Architecture SCSI Processor
Data Sheet
2
FAS368M
53368-580-00 A
QLogic Corporation
Fast DMA Protocol
Fast DMA protocol is required for supporting the full
bandwidth of Ultra, wide SCSI.
The DREQ signal initiates DMA transfers and runs
asynchronous to the user's clock. For read operations,
DACK acts as a chip select to enable the FAS368M drivers onto
the DMA bus. The chip select role of DACK helps support the
burst timing of fast DMA mode. DACK selects the FAS368M
after DREQ is asserted and is removed either after DREQ is
deasserted or when the DMA transfer is paused.
DBRD requests data from the FAS368M and DBWR
validates data sent to the FAS368M. Data is valid around the
rising (trailing) edge of DBRD or DBWR.
DMA transfers are terminated by deasserting DREQ.
Deassertion of DREQ is triggered by the leading edge of
DBRD or DBWR (see timing parameter t1 in figures 2 and 3)
under any of the following conditions:
s
To prevent FIFO overrun conditions
s
To prevent FIFO underrun conditions
s
When the required amount of data has been
transferred
When DREQ is deasserted, the FAS368M ignores
DBRD and DBWR. Data transfers do not take place unless
DREQ is asserted.
The FAS368M does not generate parity on the incoming
DMA bus. Correct parity must always be supplied with the
data.
The DMA interface signals are listed in table 1. DMA
timing is listed in table 2 and illustrated in figures 2 and 3.
Figure 1. FAS368MBlock Diagram
SEQUENCERS
FIFO
18 SCSI
CONTROL PINS
SCSI DATA BUS
CLOCK
CONVERSION
CONFIGURATION
SYNC OFFSET/
SYNC ASSERT/
SYNC DEASSERT
SYNC PERIOD
SEQUENCE
STEP
STATUS
INTERRUPT
COMMAND
32 DATA PINS
4 PARITY PINS
RECOMMAND
COUNTER
BLOCK
REGISTERS
TRANSFER
COUNTER
PAD BUS
SEL/RESEL
BUS ID
SEL/RESEL
TIMEOUT
TRANSFER
COUNT
DB BUS
16 DATA PINS
2 PARITY PINS
8 DATA PINS
1 PARITY PIN
Table 1. DMA Interface Signals
Pin
Type Active Level
Description
DREQ
O
High
The FAS368M DMA request
line begins and ends DMA
cycles.
DACK
I
Low
The acknowledge is used as
a chip select to activate
FAS368M drivers and to
acknowledge acceptance of
DREQ.
DBRD
I
Rising edge
The trailing edge accepts
data from the FAS368M for
DMA read operations.
53368-580-00 A
FAS368M
3
QLogic Corporation
DBWR
I
Rising edge
The trailing edge strobes
data into the FAS368M FIFO
on DMA write operations.
DB15-0
I/O
N/A
This is the DMA data bus.
Table 2. DMA Timing
Symbol
Description
Min.
(ns)
Max.
(ns)
t1
DBRD/DBWR low to DREQ low
a
12
t2
DACK high to DREQ high
2
t3
DACK high to DACK low
40
tR1
DACK low to DBRD low
tR5
tR2
DBRD assertion pulse width
15
tR3
DBRD deassertion pulse width
15
tR4
DBRD high to DACK high
b
tR3
tR5
DBRD low to DBRD low cycle
40
tR6
DACK low to DB15-0 read on
c
2
Table 1. DMA Interface Signals (Continued)
Pin
Type Active Level
Description
tR7
DACK high to DB15-0 read off
c
15
tR8
DBRD low to DB15-0 read valid
c
15
tR9
DBRD low to DB15-0 read invalid
c
0
tW1
DACK low to DBWR low
tW5
tW2
DBWR assertion pulse width
15
tW3
DBWR deassertion pulse width
15
tW4
DBWR high to DACK high
d
tW3
tW5
DBWR low to DBWR low cycle
40
tW6
DB15-0 write setup to DBWR high
10
tW7
DB15-0 write hold from DBWR high
5
Table Notes
a
DREQ loading is 30 pf.
b
DBRD low to DACK high
tR5
c
Data loading is 50 pf.
d
DBWR low to DACK high
tW5
Table 2. DMA Timing (Continued)
Symbol
Description
Min.
(ns)
Max.
(ns)
tR6
tR8
DREQ
DBRD
DB15-0
Figure 2. DMA Read Cycle
DACK
tR3
tR2
t2
t3
t1
tR5
tR1
tR9
tR4
tR7
DREQ
DBRD
DB15-0
Figure 3. DMA Write Cycle
DACK
tW3
tW2
t2
t3
t1
tW5
tW1
tW4
tW6
tW7
4
FAS368M
53368-580-00 A
QLogic Corporation
Interfaces
The FAS368M interfaces consist of the microprocessor bus and the SCSI bus. Pins that support these interfaces and
other chip operations are shown in figure 4.
Figure 4. FAS368M Functional Signal Grouping
RD
MICROPROCESSOR
INTERFACE
RESETO
RESETI
RESET
VDD
VSS
POWER
AND GROUND
CLK
CLOCK
RST/RST
SEL/SEL
BSY/BSY
ATN/ATN
MSG/MSG
CD/CD
IO/IO
REQ/REQ
ACK/ACK
SCSI
INTERFACE
INT
CS
DREQ
DMA AND
MICROPROCESSOR
INTERFACE
A3-0
WR
PAD7-0
PADP
MODE1-0
BUS CONFIGURATION
DBWR
DBRD
DACK
DBP1-0
SDP1-0/SDP1-0
SD15-0/SD15-0
DB15-0
PAUSE
FAS368M
16
4
8
2
2
2
2
2
2
2
2
2
32
4
2
DIFFERENTIAL
MODE SUPPORT
DIFFM
DIFFSENS
53368-580-00 A
FAS368M
5
QLogic Corporation
Packaging
The FAS368M is available in a 144-pin thin quad flat pack (TQFP). The mechanical drawings are illustrated in figure 3.
Electrical Characteristics
Table 4. Operating Conditions
Symbol
Description
Minimum
Maximum
Unit
VDD
Supply voltage (5 volt)
4.75
5.25
V
VDD
Supply voltage (3 volt)
3.3 V - 5%
3.3 V + 5%
V
IDD
a
Supply current (static IDD)
1
mA
IDD
b
Supply current (dynamic IDD)
TBD
mA
TA
Ambient temperature
0
70
o
C
Table Notes
Conditions that not within the operating conditions but within the absolute maximum stress ratings may
cause the chip to malfunction.
Capacitance in and out (CIN, COUT) is 15 pF maximum for all pins.
a
Static IDD is measured with no clocks running and all inputs forced to VDD, all outputs unloaded, all
bidirectional pins configured as inputs, and LVD mode disabled.
b
Dynamic IDD is dependent on the application.
Figure 3. FAS368M Mechanical Drawings
INDEX MARK
20.0
0.2
22.0
0.4
0.5
0.2
DETAIL A
0.5
PIN 1
PIN 37
PIN72
PIN 36
PIN 144
PIN 73
PIN 108
PIN 109
0.2
0.1
1.0
0.2
22.0
0.4
0.10 + 0.05
0.1
0.1
1.6 MAX
NOTE:
ALL DIMENSIONS ARE IN MILLIMETERS.
ALL DIMENSIONS ARE NOMINAL UNLESS SPECIFIED OTHERWISE.
20.0
0.2
4
TYPICAL
SEE DETAIL A
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