53660-580-00 A
FAS660
page 1 of 4
Features Summary
s
Compliance with Information Technology--Small
Computer System Interface, X3.131-1994 (SCSI-2)
s
Compliance with SCSI Parallel Interface (SCSI-3),
X3T10-855D (SCAM)
s
Compliance with Information Technology--Small
Computer System Interface, X3T10/1071D
(Fast-20)
s
Compliance with Information Technology--SCSI
Parallel Interface-2 (SPI-2), X3T10/1142D
(Fast-40)
s
Compliance with Information Technology--SCSI
Parallel Interface-3 (SPI-3), X3T10/1302D
(Fast-80)
s
Compliance with Information Technology--SCSI
Parallel Interface-4 (SPI-4), X3T10/1365D
(Fast-160)
s
SCSI synchronous data transfer rates up to:
320 MBps (wide, 16-bit Fast-160)
160 MBps (wide, 16-bit Fast-80)
80 MBps (wide, 16-bit Fast-40)
40 MBps (narrow, eight-bit Fast-40)
s
On-chip low voltage differential (LVD) drivers
s
Versatile 40 million instructions per second (MIPS)
microcontroller
s
Programmable microcontroller to automate SCSI
protocol handling
s
Programmable filtering on select SCSI signals
s
Programmable slew-rate control
s
Supports initiator and target modes
s
DMA interface with late transfer tolerant design
that provides 160 MBps sustained transfers
s
Buffer controller for external SRAM
s
Two 256-byte DMA FIFOs
s
On-chip phase lock loop (PLL) for high frequency
clock synthesis
Product Description
The FAS660 device incorporates an enhanced
high-performance SCSI engine derived from the triple
embedded controller (TEC) family
(see figure 1)
.
Figure 1. FAS660 Block Diagram
BUFFER
CONTROLLER
DATA FLOW
CONTROL
DATA
ADDRESS
BUS TIMING
ADDRESS AND TIMING DATA
DATA BUS
MICROPROCESSOR BUS
DMA
SCSI
CONTROLLER
DATA
AND
CONTROL
MICROCONTROLLER
DMA PORT
SDRAM PORT
SCSI PORT
MICROPROCESSOR
MICROPROCESSOR
INTERFACE LOGIC
QLogic Corporation
FAS660 Fast Architecture SCSI Processor
Data Sheet
page 2 of 4
FAS660
53660-580-00 A
QLogic Corporation
The FAS660 provides Fast-160 SCSI synchronous
transfer rates. The highly integrated SCSI core provides
advanced SCAM level 1 and level 2 support. The core
includes a microcontroller to provide the user with a
flexible, programmable means to coordinate SCSI
sequences.
SCSI Controller
The following list highlights the FAS660 SCSI
controller features.
s
Asynchronous data transfers greater than
5 megatransfers per second
s
Synchronous data transfers (5 megatransfers per
second)
s
Fast synchronous data transfers (10 megatransfers
per second)
s
Fast-20 synchronous data transfers
(20 megatransfers per second)
s
Fast-40 synchronous data transfers
(40 megatransfers per second)
s
Fast-80 synchronous data transfers
(80 megatransfers per second)
s
Fast-160 synchronous data transfers
(160 megatransfers per second)
s
8-bit (narrow) and 16-bit (wide) SCSI bus widths
s
SCAM levels 1 and 2
The SCSI controller provides powerful and flexible
low-level hardware assistance for SCSI protocol handling.
The FAS660 microcontroller, SCSI FIFO, and SCSI
controller perform frequently used SCSI operations with
low firmware overhead at performance levels ranging from
asynchronous SCSI to Fast-160.
The core of the FAS660 SCSI processor, with enhanced
initiator support, is derived from the proven TEC485 SCSI
disk controller.
Microcontroller
The following list highlights the FAS660 SCSI
microcontroller features.
s
Maximum 40 MIPS with a 25-ns instruction cycle
(except for branch)
s
64 single-word instructions
s
16-bit wide instructions
s
Eight-bit wide data path
s
1024x 16 SRAM program memory
s
16 x 8 dual-port, general purpose registers;
32 mailbox registers
s
Five-level deep hardware stack
s
Direct, indirect, and absolute addressing modes
s
Two firmware interrupt sources
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Two hardware interrupts; one with four-bit,
automatic interrupt vector and status
s
Full chip access through the microprocessor bus
The FAS660 provides a microcontroller with separate
program and data memory. The result is improved
bandwidth over traditional Von Neuman architecture where
program and data share the same memory. Separating
program and data memory allows independent widths for
instruction and data. All instructions are 16-bit wide, single
word.
The four operations for each instruction cycle are fetch,
decode, execute, and write back. A three-stage pipeline
allows overlaps between fetch and write-back cycles with
decode and execute cycles. Consequently, all instructions
execute in one instruction cycle or two clock periods (25 ns
at 80 MHz) except for program branches, which require
two instruction cycles.
The microcontroller is composed of a 1024 x16
program memory, a 32 x8 register file, a 5x 8 stack, an
integer ALU, 32 mailbox registers, and other special
purpose registers. The microcontroller has direct access to
addresses in the register files or in data memory. The first
16 bytes of the external SCSI FIFO are mapped directly
into data memory locations 90h9Fh. The microcontroller
can monitor the FIFO contents (one byte at a time) without
removing it. The microcontroller accesses external
registers through the external access read (EARD)
instruction or the external access write (EAWR)
instruction.
Buffer Controller
The FAS660 buffer management is provided by a
multiple-channel, high-speed, bursting DMA controller.
The buffer controller connects the buffer SDRAM to the
disk channel, SCSI channel, and the microprocessor bus.
The buffer controller regulates all data movement into and
out of SDRAM buffer memory. Each DMA channel
supports DMA bursting to maintain optimal bandwidth.
The DMA, microprocessor, and SCSI channels each have
a FIFO. Each DMA channel has associated control,
configuration, and buffer memory address registers.
The buffer controller also provides round-robin
arbitration for the buffer resource, a four-byte buffer
cyclical redundancy check (BCRC), Data Flow control,
and automatic SDRAM refresh control.
The buffer controller table search tool compares 16 or
32 bit-based tables of numbers, such as an LBA, to provide
high-speed lookups for cache, zone, defect, and other
system searches.
To support the SCSI-3 RAID commands in the FAS660,
an exclusive or (XOR) engine running at DMA speeds
generates an XOR of two data buffers.
53660-580-00 A
FAS660
page 3 of 4
QLogic Corporation
DMA Interface
The FAS660 has an improved DMA interface with an
expanded 2x 256byte FIFO that provides transfer rates up
to 160 MBps. The FAS660 supports 16-bit wide data strobe
transfers of up to 80 MHz with 160 MBps data throughput.
The internal FIFO provides programmable threshold logic
for determining FIFO
full and empty conditions.
Microprocessor Interface
The FAS660 microprocessor interface provides the
interface between the internal modules (SCSI controller,
FIFO, microcontroller, and DMA engine) and an external
microprocessor.
Interfaces
The FAS660 interfaces consist of SCSI,
microprocessor, DMA, buffer controller, and differential
mode support. Pins that support these interfaces and other
chip operations are shown in
figure 2
.
Figure 2. FAS660 Functional Signal Grouping
POWER
AND GROUND
87
MICROPROCESSOR
INTERFACE
DMA
INTERFACE
BUFFER
CONTROLLER
INTERFACE
FAS660
16
20
MISCELLANEOUS
2
32
2
SCSI
INTERFACE
12
2
2
2
2
2
2
2
2
32
2
2
30
55
27
56
272
4
2
2
10
3
28
44
2
AD150, A1916
ADRSEN
ALE
ARDU
BHE
CS0
CS1
INT1
RD
SIZE
WR
CLKSEL
FILTER
NC
PORTA0
PORTA1
RESET
SCAN_ENABLE
SCAN_TEST_MODE
TEST
TESTCLKA
TESTCLKB
TESTCLKC
VCOCLOCK
WIDE
17
BA110
BD310
BS0
BS1
CAS
CKE
LDQM10
RAS
SDRAMCLK
UDQM10
WE
AF_AE
DACK
DB150
DBOE
DBP10
DMACLK
DREQ
FF_FE
LB_DIF
PAUSE
WR_CLK
ACK/ACK
ATN/ATN
BSY/BSY
CD/CD
DIFFSENS
IO/IO
LVDREF
MSG/MSG
P_CRCA/P_CRCA
REQ/REQ
RST/RST
SD150/SD150
SDP10/SDP10
SEL/SEL
VDD2
VDD2A
VDD3
VSS
VSSA
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