83140-580-01 C
ISP1040B
1
Features
s
Compliance with ANSI SCSI standard
X3.131-1994
s
Compliance with ANSI SCSI configured
automatically (SCAM) protocol levels 1 and 2
s
Compliance with ANSI X3T10/855D SCSI-3
parallel interface (SPI) standard
s
Compliance with ANSI X3T10/1071D Fast-20
standard
s
Onboard RISC processor to execute operations at
the I/O control block level from the host memory
s
Supports fast, wide, and Ultra (Fast-20) SCSI data
transfer rates
s
SCSI initiator and target modes of operation
s
32-bit, intelligent bus master, DMA PCI bus
interface
s
SCSI operations executed from start to finish
without host intervention
s
Simultaneous, multiple logical threads
s
JTAG boundary scan support
Product Description
The ISP1040B is a single-chip, highly integrated, bus
master, SCSI I/O processor for use in SCSI initiator-type
applications. The device interfaces the PCI bus to a wide,
Ultra SCSI bus and contains an onboard RISC processor.
The ISP1040B is a fully autonomous device, capable of
managing multiple I/O operations and associated data
transfers from initiation to completion without host CPU
intervention. The ISP1040B block diagram is illustrated in
figure 1.
RISC I/O DATA BUS
Figure 1. ISP1040B Block Diagram
DATA CHANNEL
SXP SCSI ENGINE
PCI INTERFACE
HOST MEMORY
HOST SOFTWARE
DRIVER
REQUEST
QUEUE
RESPONSE
QUEUE
32-BIT
PCI
BUS
IOCBS
FIFO
WCS
SEQUENCERS
CONTROL
DATA FIFO
COMMAND
FIFO
DMA
CONTROL
MAILBOX
REGISTERS
RISC
REGISTER
FILE
ALU
BOOT
CODE
MEMORY
INTERFACE
8/16-BIT
DATA 16
ADDRESS 16
EXTERNAL
CODE/DATA
MEMORY
ISP1040B
COMMAND
BUFFER
MESSAGE
BUFFER
SXP CODE
REGISTERS
PARALLEL
SCSI BUS
CTRL/CONFIG
REGISTERS
QLogic Corporation
ISP1040B Intelligent SCSI Processor
Data Sheet
2
ISP1040B
83140-580-01 C
QLogic Corporation
ISP Initiator and Target Firmware
The ISP1040B firmware implements a cooperative,
multitasking host adapter that provides the host system
with complete SCSI command and data transport
capabilities, thus freeing the host system from the demands
of the SCSI bus protocol. The ISP1040B firmware provides
two interfaces to the host system: the command interface
and the SCSI transport interface. The single-threaded
command interface facilitates debugging, configuration,
and error recovery. The multithreaded SCSI transport
interface maximizes use of the SCSI and host buses. The
ISP1040B can switch between initiator and target modes.
I/O Subsystem Organization
To maximize I/O throughput and improve host and
SCSI bus utilization, the ISP1040B incorporates a
high-speed, proprietary RISC processor; an intelligent
SCSI bus controller (SCSI executive processor [SXP]); and
a host bus, dual-channel DMA controller. The SCSI bus
controller and the host bus DMA controller operate
independently and concurrently under control of the
onboard RISC processor for maximum system
performance. The ISP1040B RISC interface requires
external program data memory.
The complete I/O subsystem solution using the
ISP1040B and associated supporting memory devices is
shown in figure 2.
Interfaces
The ISP1040B supports the following interfaces:
s
PCI bus
s
RISC processor
s
SCSI executive processor
Pins that support these interfaces and other chip
operations are shown in figure 3.
PCI Bus Interface
The ISP1040B PCI bus interface supports the
following:
s
128-byte data DMA FIFO and 64-byte command
DMA FIFO with threshold control
s
16-bit target mode
s
DMA FIFO management, data alignment, data
assembly, and data disassembly
s
PCI Local Bus Specification revision 2.1 compliant
s
Support for subsystem ID and subsystem vendor ID
s
Dual voltage (3.3V and 5.0V) PCI I/O buffers
s
Flash ROM support
The ISP1040B is designed to interface directly to the
PCI local bus and operate as a 32-bit DMA master. This
function is accomplished through the PCI bus interface unit
(PBIU) containing an onboard DMA controller. The PBIU
generates and samples PCI bus control signals, generates
host memory addresses, and facilitates data transfers
between host memory and the onboard DMA FIFO. The
PBIU also allows the host to access the ISP1040B internal
registers and communicate with the onboard RISC
processor through the PCI bus target mode operation.
The ISP1040B onboard DMA controller consists of two
independent DMA channels that initiate transactions on the
PCI bus and transfer data between the memory and DMA
FIFO. The two DMA channels are the command DMA
channel and the data DMA channel. The command DMA
channel is used mainly by the RISC processor for small
transfers such as fetching commands from and writing
status information to the host memory over the PCI bus.
The data DMA channel transfers data between the SCSI
bus and the PCI bus.
The PBIU internally arbitrates between the data DMA
channel and the command DMA channel and alternately
services them. Each DMA channel has a set of DMA
registers that are programmed for transfers by the RISC
processor.
ISP1040B
SCSI
16
SCSI
TARGETS
TARGET
TARGET
PCI
I/F
SCSI
I/F
RISC
CODE/DATA
MEMORY
PCI
BUS
PCI
HOST
MEMORY
IOCB
DATA
32
Figure 2. I/O Subsystem Design Using the
ISP1040B
83140-580-01 C
ISP1040B
3
QLogic Corporation
RISC Processor Interface
The ISP1040B RISC processor interface supports the
following:
s
Programmable cycle time for external memory
access
s
Internal 16-bit wide data paths
s
Execution of multiple I/O control blocks from the
host memory
s
Management of onboard host bus DMA controller
and SCSI bus controller
s
Reduced host intervention and interrupt overhead
s
Capacity to generate one interrupt per I/O operation
The onboard RISC processor enables the ISP1040B to
handle complete I/O transactions with no intervention from
the host. The ISP1040B RISC processor controls the chip
Figure 3. ISP1040B Functional Signal Grouping
EXTBOOT
RISC
INTERFACE
VDD
VSS
POWER
AND GROUND
MISC
CONTROL
BSY
CD
DIFFM
SCSI
INTERFACE
ISP1040B
RISCSTB/JTAG
ESC1-0
RADDR15-0
IF/VDET
ACK
ATN
IO
MSG
REQ
RST
SD15-0
SDP1-0
SEL
TRIG/60MHZ
TSTOUT/TDO
FRAME
STOP
TRDY
DEVSEL
PERR
IDSEL
SERR
IRDY
RESET
CLK
RISCOE
WE
RDATA15-0
TESTMODE0/TDI
RESET
CBE3-0
PAR
INTA
NVDATI
NVCS
NVDATO/SUBID
NVCLK/3V
NVRAM
CONTROL
BIOS PROM
PDATA7-0
POD
BSYLED
GPIO3-0
RDPAR
DIFFS
EARB
ESD
EIG
ETG
EBSY
ESEL
ERST
SCSI
DIFFERENTIAL
INTERFACE
PCI INTERFACE
AD31-0
BCLK
BGNT
BREQ
FLASH ROM
FROE
FRWE
TESTMODE1/TMS
TESTMODE2/TCK
4
ISP1040B
83140-580-01 C
QLogic Corporation
interfaces; executes simultaneous, multiple input/output
control blocks (IOCBs); and maintains the required thread
information for each transfer.
SCSI Executive Processor Interface
The ISP1040B SXP interface supports the following:
s
SCAM level 1 and level 2 support
32-byte FIFO with parity pass-through option
Command, status, message in, and message out
buffers
Device information storage area
s
SCSI synchronous transfer rates of 40 Mbytes/sec
(requires 60-MHz clock)
s
SCSI asynchronous transfer rate of 12 Mbytes/sec
s
Programmable SCSI processor
Specialized instruction set with 16-bit
microword
384-bit by 16-bit internal control store RAM
s
Diagnostic support
The SXP provides an autonomous, intelligent SCSI
interface capable of handling complete SCSI operations.
The SXP interrupts the RISC processor only to handle
higher level functions such as threaded operations or error
handling.
Packaging
The ISP1040B is available in a 208-pin plastic quad flat
pack (PQFP). Package dimensions are shown in figure 4.
Figure 4. ISP1040B Mechanical Drawings
INDEX MARK
PIN 1
PIN 53
PIN 104
PIN 208
PIN 52
PIN 105
PIN 156
PIN 157
28.0
0.1
30.6
0.25
30.6
0.25
NOTE:
ALL DIMENSIONS ARE IN MILLIMETERS.
SEE DETAIL A
DETAIL A
0.33 + 0.1
0.20 + 0.1
0.15
4.07 MAXIMUM
0.50 BSC
0.56 + 0.1
4
TYPICAL
+0.10
-0.05
28
0.1
February 5, 1997 QLogic Corporation, 3545 Harbor Blvd., Costa Mesa, CA 92626, (800) ON-CHIP-1 or (714) 438-2200
Specifications are subject to change without notice.
QLogic is a trademark of QLogic Corporation.
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