83180-580-00 B
PRELIMINARY
ISP1080
1
Features
s
Compliance with draft ANSI X3.302-199x Ultra2
SCSI (SPI-2) standard
s
64-bit PCI host bus interface, compliant with PCI
Local Bus Specification rev 2.1
s
Compliance with PCI Bus Power Management
Interface Specification Revision 1.0 (PC97)
s
Up to 80 Mbytes/sec parallel SCSI transfer rates
s
SCSI initiator and target modes of operation
s
Onboard RISC processor to execute operations at
the I/O control-block level from the host memory
s
Supports PCI dual-address cycle (64-bit
addressing)
s
No host intervention required to execute SCSI
operations from start to finish
s
Simultaneous, multiple logical threads
s
JTAG boundary scan support
Product Description
The ISP1080 adds Ultra2 (Fast-40) SCSI support to the
expanding functionality of the ISP. The product is a
single-chip, highly integrated bus master, SCSI I/O
processor for SCSI initiator and target applications. This
device interfaces the PCI bus to an ANSI Ultra2 (Fast-40)
SCSI bus and contains an onboard RISC processor. The
product is a fully autonomous device, capable of managing
multiple I/O operations and associated data transfers from
start to finish without host intervention. The ISP1080
provides power management feature support in accordance
with the PCI Bus Power Management Interface
Specification. The ISP1080 is host-software compatible
with the QLogic ISP1020 and ISP1040 chips. The ISP1080
block diagram is illustrated in figure 1.
Figure 1. ISP1080 Block Diagram
RISC I/O DATA BUS
DMA BUS
SXP SCSI ENGINE
PCI INTERFACE
HOST MEMORY
HOST SOFTWARE
DRIVER
REQUEST
QUEUE
RESPONSE
QUEUE
64-BIT
PCI
BUS
IOCBS
FIFO
WCS
SEQUENCERS
CONTROL
DATA FIFO
128-BYTE
COMMAND FIFO
DMA
CONTROL
MAILBOX
REGISTERS
RISC
REGISTER
FILE
ALU
BOOT
CODE
MEMORY
INTERFACE
16-BIT DATA
16-BIT ADDRESS
EXTERNAL
CODE/DATA
MEMORY
ISP1080
COMMAND
BUFFER
MESSAGE
BUFFER
SXP CODE
REGISTERS
Ultra2 LVD
WIDE SCSI BUS
CTRL/CONFIG
REGISTERS
FLASH
BIOS
NVRAM
512-BYTE
QLogic Corporation
ISP1080 Intelligent SCSI Processor
Data Sheet
2
ISP1080
PRELIMINARY
83180-580-00 B
QLogic Corporation
ISP Initiator and Target Firmware
The ISP1080 firmware implements a cooperative,
multitasking host adapter that provides the host system
with complete SCSI command and data transport
capabilities, thus freeing the host system from the demands
of the SCSI bus protocol. The firmware provides two
interfaces to the host system: the command interface and
the SCSI transport interface. The single-threaded
command interface facilitates debugging, configuration,
and error recovery, while the multithreaded SCSI transport
interface maximizes use of the SCSI and host buses. The
ISP1080 can switch between initiator and target modes.
Software Drivers
BIOS firmware is available for the ISP1080. Software
drivers are available for the following operating systems:
s
AIX
s
I
2
O
s
DOS/Windows
s
Novell NetWare
s
OS/2
s
SCO UNIX
s
UnixWare
s
Windows 95
s
Windows NT
Subsystem Organization
To maximize I/O throughput and improve host and
SCSI bus utilization, the ISP1080 incorporates a
high-speed proprietary RISC processor; an intelligent
SCSI bus controller (SCSI executive processor [SXP]); and
a host bus, dual-channel, first-party DMA controller. The
SCSI bus controller and the host bus DMA controller
operate independently and concurrently under the control
of the onboard RISC processor for maximum system
performance. The ISP1080 RISC interface requires
external program data memory.
The complete I/O subsystem solution including the
ISP1080 and associated supporting memory devices is
shown in figure 2.
Interfaces
The ISP1080 interfaces consist of the PCI bus interface,
SCSI interface, RISC interface, BIOS PROM interface, and
NVRAM interface. Pins that support these interfaces and
other chip operations are shown in figure 3.
ISP1080
SCSI
16
SCSI
TARGETS
TARGET
TARGET
PCI
I/F
SCSI
I/F
RISC
CODE/DATA
MEMORY
PCI
HOST
MEMORY
IOCB
DATA
Figure 2. I/O Subsystem Design Using the ISP1080
PCI B
U
S
83180-580-00 B
PRELIMINARY
ISP1080
3
QLogic Corporation
PCI Interface
The ISP1080 PCI interface supports the following:
s
64-bit (address and data), intelligent bus master,
burst DMA host interface for fetching I/O control
blocks and data transfers
s
Supports PCI dual-address cycle (64-bit
addressing)
s
Backward compatible to 32-bit PCI
s
Dual-channel DMA controller
s
Data DMA FIFO and command DMA FIFO with
threshold control
s
16-bit slave mode for communication with host
s
Pipelined DMA registers for efficient scatter and
gather operations
s
32-bit DMA transfer counter for I/O transfer lengths
of up to four gigabytes
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Support for subsystem ID
s
Support for flash BIOS PROM
Figure 3. ISP1080 Functional Signal Grouping
IF
RISC
INTERFACE
VDD
VSS
POWER
AND GROUND
MISC
CONTROL
SDP0, SDP0
DIFFSENS
C/D, C/D
SCSI INTERFACE
ISP1080
ROE
ECS3-0
RADDR15-0
IOCS
FRAME
PCI BUS
INTERFACE
STOP
AD63-0
TRDY
DEVSEL
PERR
IDSEL
SERR
IRDY
RESET
RISCSTB
WE
RDATA15-0
BREQ
RESET
CBE7-0
PAR64
INTA
BCLK
NVDATI
NVCS
NVDATO
NVCLK
NVRAM
CONTROL
BGNT
SD15-0, SD15-0
SDP1, SDP1
TESTMODE2-0
TRIG
CLK
TSTOUT
ACK, ACK
BSY, BSY
RDPAR
ACK64
REQ64
I/O, I/O
MSG, MSG
REQ, REQ
RST, RST
SEL, SEL
TERMPWR
ATN, ATN
TDO
TDI
TMS
TCK
JTAG INTERFACE
TRST
DIFFM
DIFFS
EARB
EBSY
EIG
ERST
ESEL
ESD
ETG
SCSI
DIFFERENTIAL
INTERFACE
FLASH BIOS
PDATA7-0
FLASHCS
FLASHOE
FLASHWR
EXTINT
4
ISP1080
PRELIMINARY
83180-580-00 B
QLogic Corporation
s
Support for PCI cache commands
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3.3V and 5.0V tolerant PCI I/O buffers
The ISP1080 is designed to interface directly to the PCI
bus and operate as a 64-bit DMA bus master. This operation
is accomplished through a PCI bus interface unit (PBIU)
that contains an onboard DMA controller. The PBIU
generates and samples PCI control signals, generates host
memory addresses, and facilitates the transfer of data
between host memory and the onboard DMA FIFO. It also
allows the host to access the ISP1080 internal registers and
communicate with the onboard RISC processor through the
PCI target mode operation.
The ISP1080 onboard DMA controller consists of two
independent DMA channels that initiate transactions on the
PCI bus and transfer data between the host memory and
DMA FIFO. The two DMA channels are the command
DMA channel and the data DMA channel. The command
DMA channel is used mainly by the RISC processor for
small transfers such as fetching commands from and
writing status information to the host memory over the PCI
bus. The data DMA channel transfers data between the
SCSI bus and the PCI bus.
The PBIU internally arbitrates between the data DMA
channel and the command DMA channel and alternately
services them. Each DMA channel has a set of DMA
registers that are programmed for transfers by the RISC
processor.
SCSI Executive Processor
The ISP1080 SXP supports the following:
s
Ultra and Ultra2 (Fast-40) SCSI synchronous data
transfer rates up to 80 Mbytes/sec
s
Asynchronous SCSI data transfer rates up to
12 Mbytes/sec
s
Programmable SCSI processor
Specialized instruction set with 16-bit
microword
384-bit by 16-bit internal RAM control store
s
32-bit, configurable SCSI transfer counter
s
Command, status, message in, and message out
buffers
s
Device information storage area
s
On-chip, LVD SCSI transceivers
s
Programmable active negation
The SXP provides an autonomous, intelligent SCSI
interface capable of handling complete SCSI operations.
The SXP interrupts the RISC processor only to handle
higher level functions such as threaded operations or error
handling.
RISC Processor
The ISP1080 RISC processor supports the following:
s
Execution of multiple I/O control blocks from the
host memory
s
Reduced host intervention and interrupt overhead
s
One interrupt or less per I/O operation
The onboard RISC processor enables the ISP1080 to
handle complete I/O transactions with no intervention from
the host. The ISP1080 RISC processor controls the chip
interfaces; executes simultaneous, multiple input/output
control blocks (IOCB); and maintains the required thread
information for each transfer.
Packaging
The ISP1080 is available in a 352-pin, thermally
enhanced ballgrid array (TE BGA) package.
AIX is a trademark of IBM Corporation.
DOS, OS/2, Windows NT, and Windows 95 are trademarks or registered trademarks of Microsoft Corp.
Novell and NetWare are registered trademarks of Novell, Inc.
SCO UNIX is a registered trademark of Santa Cruz Operations.
UNIX is a trademark of AT&T Bell Laboratories.
All other brand and product names are trademarks or registered trademarks of their respective holders.
July 29, 1997 QLogic Corporation, 3545 Harbor Blvd., Costa Mesa, CA 92626, (800) ON-CHIP-1 or (714) 438-2200
Specifications are subject to change without notice.
QLogic is a trademark of QLogic Corporation.
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