Document Outline
- Cover
- Cautions
- Preface
- Contents
- Section 1 Overview
- 1.1 Overview
- 1.2 Internal Block Diagrams
- 1.3 Pin Arrangement and Functions
- 1.3.1 Pin Arrangement
- 1.3.2 List of Pin Functions
- 1.3.3 Pin Functions
- Section 2 CPU
- 2.1 Overview
- 2.1.1 Features
- 2.1.2 Address Space
- 2.1.3 Register Configuration
- 2.2 Register Descriptions
- 2.2.1 General Registers
- 2.2.2 Control Registers
- 2.2.3 Initial Register Values
- 2.3 Data Formats
- 2.3.1 Data Formats in General Registers
- 2.3.2 Memory Data Formats
- 2.4 Addressing Modes
- 2.4.1 Addressing Modes
- 2.4.2 Effective Address Calculation
- 2.5 Instruction Set
- 2.5.1 Data Transfer Instructions
- 2.5.2 Arithmetic Operations
- 2.5.3 Logic Operations
- 2.5.4 Shift Operations
- 2.5.5 Bit Manipulations
- 2.5.6 Branching Instructions
- 2.5.7 System Control Instructions
- 2.5.8 Block Data Transfer Instruction
- 2.6 Basic Operational Timing
- 2.6.1 Access to On-Chip Memory (RAM, ROM)
- 2.6.2 Access to On-Chip Peripheral Modules
- 2.7 CPU States
- 2.7.1 Overview
- 2.7.2 Reset State
- 2.7.3 Program Execution State
- 2.7.4 Program Halt State
- 2.7.5 Exception-Handling State
- 2.8 Application Notes
- 2.8.1 Notes on Bit Manipulation
- 2.8.2 Notes on Use of the EEPMOV Instruction (Cannot be used in the H8/3577 Series and H8/3567 Series)
- Section 3 MCU Operating Modes
- 3.1 Overview
- 3.1.1 Operating Mode Selection
- 3.1.2 Register Configuration
- 3.2 Register Descriptions
- 3.2.1 Mode Control Register (MDCR)
- 3.2.2 System Control Register (SYSCR)
- 3.2.3 Serial Timer Control Register (STCR)
- 3.3 Address Map
- Section 4 Exception Handling
- 4.1 Overview
- 4.1.1 Exception Handling Types and Priority
- 4.1.2 Exception Handling Operation
- 4.1.3 Exception Sources and Vector Table
- 4.2 Reset
- 4.2.1 Overview
- 4.2.2 Reset Sequence
- 4.2.3 Interrupts after Reset
- 4.3 Interrupts
- 4.4 Stack Status after Exception Handling
- 4.5 Note on Stack Handling
- Section 5 Interrupt Controller
- 5.1 Overview
- 5.1.1 Features
- 5.1.2 Block Diagram A block diagram of the interrupt controller is
- 5.1.3 Pin Configuration
- 5.1.4 Register Configuration
- 5.2 Register Descriptions
- 5.2.1 System Control Register (SYSCR)
- 5.2.2 IRQ Enable Register (IER)
- 5.2.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL)
- 5.2.4 IRQ Status Register (ISR)
- 5.3 Interrupt Sources
- 5.3.1 External Interrupts
- 5.3.2 Internal Interrupts
- 5.3.3 Interrupt Exception Vector Table
- 5.4 Interrupt Operation
- 5.4.1 Interrupt Operation
- 5.4.2 Interrupt Control Mode 0
- 5.4.3 Interrupt Exception Handling Sequence
- 5.4.4 Interrupt Response Times
- 5.5 Usage Notes
- 5.5.1 Contention between Interrupt Generation and Disabling
- 5.5.2 Instructions that Disable Interrupts
- 5.5.3 Interrupts during Execution of EEPMOV Instruction
- Section 6 Bus Controller
- 6.1 Overview
- 6.2 Register Descriptions
- 6.2.1 Bus Control Register (BCR)
- 6.2.2 Wait State Control Register (WSCR)
- Section 7 Universal Serial Bus Interface (USB)
- 7.1 Overview
- 7.1.1 Features
- 7.1.2 Block Diagram
- 7.1.3 Pin Configuration
- 7.1.4 Register Configuration
- 7.2 Register Descriptions
- 7.2.1 USB Data FIFO
- 7.2.2 Endpoint Size Register 1 (EPSZR1)
- 7.2.3 Endpoint Data Registers 0I, 0O, 1, 2 (EPDR0I, EPDR0O, EPDR1, EPDR2)
- 7.2.4 FIFO Valid Size Registers 0I, 0O, 1, 2 (FVSR0I, FVSR0O, FVSR1, FVSR2)
- 7.2.5 Endpoint Direction Register (EPDIR)
- 7.2.6 Packet Transmit Enable Register (PTTER)
- 7.2.7 USB Interrupt Enable Register (USBIER)
- 7.2.8 USB Interrupt Flag Register (USBIFR)
- 7.2.9 Transfer Success Flag Register (TSFR)
- 7.2.10 Transfer Fail Flag Register (TFFR)
- 7.2.11 USB Control/Status Register 0 (USBCSR0)
- 7.2.12 Endpoint Stall Register (EPSTLR)
- 7.2.13 Endpoint Reset Register (EPRSTR)
- 7.2.14 Device Resume Register (DEVRSMR)
- 7.2.15 Interrupt Source Select Register 0 (INTSELR0)
- 7.2.16 Interrupt Source Select Register 1 (INTSELR1)
- 7.2.17 Hub Overcurrent Control Register (HOCCR)
- 7.2.18 USB Control Register (USBCR)
- 7.2.19 USB PLL Control Register (UPLLCR)
- 7.2.20 USB Port Control Register (UPRTCR)
- 7.2.21 USB Test Registers 2, 1, 0 (UTESTR2, UTESTR1, UTESTR0)
- 7.2.22 Module Stop Control Register (MSTPCR)
- 7.2.23 Serial Timer Control Register (STCR)
- 7.3 Operation
- 7.3.1 USB Compound Device Configuration
- 7.3.2 Functions of USB Hub Block
- 7.3.3 Functions of USB Function
- 7.3.4 Operation when SETUP Token is Received (Endpoint 0)
- 7.3.5 Operation when OUT Token is Received (Endpoints 0 and 2)
- 7.3.6 Operation when IN Token is Received (Endpoints 0, 1, and 2)
- 7.3.7 Suspend/Resume Operations
- 7.3.8 USB Module Reset and Operation-Halted States
- 7.3.9 USB Module Startup Sequence
- 7.3.10 USB Module Slave CPU Interrupts
- Section 8 I/O Ports
- 8.1 Overview
- 8.2 Port 1
- 8.2.1 Overview
- 8.2.2 Register Configuration
- 8.2.3 Pin Functions
- 8.2.4 MOS Input Pull-Up Function
- 8.3 Port 2 [H8/3577 Series Only]
- 8.3.1 Overview
- 8.3.2 Register Configuration
- 8.3.3 Pin Functions
- 8.3.4 MOS Input Pull-Up Function
- 8.4 Port 3 [H8/3577 Series Only]
- 8.4.1 Overview
- 8.4.2 Register Configuration
- 8.4.3 Pin Functions
- 8.4.4 MOS Input Pull-Up Function
- 8.5 Port 4
- 8.5.1 Overview
- 8.5.2 Register Configuration
- 8.5.3 Pin Functions
- 8.6 Port 5
- 8.6.1 Overview
- 8.6.2 Register Configuration
- 8.6.3 Pin Functions
- 8.7 Port 6
- 8.7.1 Overview
- 8.7.2 Register Configuration
- 8.7.3 Pin Functions
- 8.8 Port 7
- 8.8.1 Overview
- 8.8.2 Register Configuration
- 8.8.3 Pin Functions
- 8.9 Port C [H8/3567 Series Version with On-Chip USB Only]
- 8.9.1 Overview
- 8.9.2 Register Configuration
- 8.9.3 Pin Functions
- 8.10 Port D [H8/3567 Series Version with On-Chip USB Only]
- 8.10.1 Overview
- 8.10.2 Register Configuration
- 8.10.3 Pin Functions
- Section 9 8-Bit PWM Timers
- 9.1 Overview
- 9.1.1 Features
- 9.1.2 Block Diagram
- 9.1.3 Pin Configuration
- 9.1.4 Register Configuration
- 9.2 Register Descriptions
- 9.2.1 PWM Register Select (PWSL)
- 9.2.2 PWM Data Registers (PWDR0 to PWDR15)
- 9.2.3 PWM Data Polarity Registers A and B (PWDPRA and PWDPRB)
- 9.2.4 PWM Output Enable Registers A and B (PWOERA and PWOERB)
- 9.2.5 Peripheral Clock Select Register (PCSR)
- 9.2.6 Port 1 Data Direction Register (P1DDR)
- 9.2.7 Port 2 Data Direction Register (P2DDR)
- 9.2.8 Port 1 Data Register (P1DR)
- 9.2.9 Port 2 Data Register (P2DR)
- 9.2.10 Module Stop Control Register (MSTPCR)
- 9.3 Operation
- 9.3.1 Correspondence between PWM Data Register Contents and Output Waveform
- Section 10 14-Bit PWM Timer
- 10.1 Overview
- 10.1.1 Features
- 10.1.2 Block Diagram
- 10.1.3 Pin Configuration
- 10.1.4 Register Configuration
- 10.2 Register Descriptions
- 10.2.1 PWM D/A Counter (DACNT)
- 10.2.2 D/A Data Registers A and B (DADRA and DADRB)
- 10.2.3 PWM D/A Control Register (DACR)
- 10.2.4 Module Stop Control Register (MSTPCR)
- 10.3 Bus Master Interface
- 10.4 Operation
- Section 11 16-Bit Free-Running Timer
- 11.1 Overview
- 11.1.1 Features
- 11.1.2 Block Diagram
- 11.1.3 Input and Output Pins
- 11.1.4 Register Configuration
- 11.2 Register Descriptions
- 11.2.1 Free-Running Counter (FRC)
- 11.2.2 Output Compare Registers A and B (OCRA, OCRB)
- 11.2.3 Input Capture Registers A to D (ICRA to ICRD)
- 11.2.4 Output Compare Registers AR and AF (OCRAR, OCRAF)
- 11.2.5 Output Compare Register DM (OCRDM)
- 11.2.6 Timer Interrupt Enable Register (TIER)
- 11.2.7 Timer Control/Status Register (TCSR)
- 11.2.8 Timer Control Register (TCR)
- 11.2.9 Timer Output Compare Control Register (TOCR)
- 11.2.10 Module Stop Control Register (MSTPCR)
- 11.3 Operation
- 11.3.1 FRC Increment Timing
- 11.3.2 Output Compare Output Timing
- 11.3.3 FRC Clear Timing
- 11.3.4 Input Capture Input Timing
- 11.3.5 Timing of Input Capture Flag (ICFA to ICFD) Setting
- 11.3.6 Setting of Output Compare Flags A and B (OCFA, OCFB)
- 11.3.7 Setting of FRC Overflow Flag (OVF)
- 11.3.8 Automatic Addition of OCRA and OCRAR/OCRAF
- 11.3.9 ICRD and OCRDM Mask Signal Generation
- 11.4 Interrupts
- 11.5 Sample Application
- 11.6 Usage Notes
- Section 12 8-Bit Timers
- 12.1 Overview
- 12.1.1 Features
- 12.1.2 Block Diagram
- 12.1.3 Pin Configuration
- 12.1.4 Register Configuration
- 12.2 Register Descriptions
- 12.2.1 Timer Counter (TCNT)
- 12.2.2 Time Constant Register A (TCORA)
- 12.2.3 Time Constant Register B (TCORB)
- 12.2.4 Timer Control Register (TCR)
- 12.2.5 Timer Control/Status Register (TCSR)
- 12.2.6 Serial/Timer Control Register (STCR)
- 12.2.7 System Control Register (SYSCR)
- 12.2.8 Timer Connection Register S (TCONRS)
- 12.2.9 Input Capture Register (TICR) [TMRX Additional Function]
- 12.2.10 Time Constant Register C (TCORC) [TMRX Additional Function]
- 12.2.11 Input Capture Registers R and F (TICRR, TICRF) [TMRX Additional Functions]
- 12.2.12 Timer Input Select Register (TISR) [TMRY Additional Function]
- 12.2.13 Module Stop Control Register (MSTPCR)
- 12.3 Operation
- 12.3.1 TCNT Incrementation Timing
- 12.3.2 Compare-Match Timing
- 12.3.3 TCNT External Reset Timing
- 12.3.4 Timing of Overflow Flag (OVF) Setting
- 12.3.5 Operation with Cascaded Connection
- 12.4 Interrupt Sources
- 12.5 8-Bit Timer Application Example
- 12.6 Usage Notes
- 12.6.1 Contention between TCNT Write and Clear
- 12.6.2 Contention between TCNT Write and Increment
- 12.6.3 Contention between TCOR Write and Compare-Match
- 12.6.4 Contention between Compare-Matches A and B
- 12.6.5 Switching of Internal Clocks and TCNT Operation
- Section 13 Timer Connection
- 13.1 Overview
- 13.1.1 Features
- 13.1.2 Block Diagram
- 13.1.3 Input and Output Pins
- 13.1.4 Register Configuration
- 13.2 Register Descriptions
- 13.2.1 Timer Connection Register I (TCONRI)
- 13.2.2 Timer Connection Register O (TCONRO)
- 13.2.3 Timer Connection Register S (TCONRS)
- 13.2.4 Edge Sense Register (SEDGR)
- 13.2.5 Module Stop Control Register (MSTPCR)
- 13.3 Operation
- 13.3.1 PWM Decoding (PDC Signal Generation)
- 13.3.2 Clamp Waveform Generation (CL1 /CL2 /CL3 Signal Generation)
- 13.3.3 Measurement of 8-Bit Timer Divided Waveform Period
- 13.3.4 IHI Signal and 2fH Modification
- 13.3.5 IVI Signal Fall Modification and IHI Synchronization
- 13.3.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation)
- 13.3.7 HSYNCO Output
- 13.3.8 VSYNCO Output
- 13.3.9 CBLANK Output
- Section 14 Watchdog Timer (WDT)
- 14.1 Overview
- 14.1.1 Features
- 14.1.2 Block Diagram
- 14.1.3 Register Configuration
- 14.2 Register Descriptions
- 14.2.1 Timer Counter (TCNT)
- 14.2.2 Timer Control/Status Register (TCSR0)
- 14.2.3 System Control Register (SYSCR)
- 14.2.4 Notes on Register Access
- 14.3 Operation
- 14.3.1 Watchdog Timer Operation
- 14.3.2 Interval Timer Operation
- 14.3.3 Timing of Setting of Overflow Flag (OVF)
- 14.4 Interrupts
- 14.5 Usage Notes
- 14.5.1 Contention between Timer Counter (TCNT) Write and Increment
- 14.5.2 Changing Value of CKS2 to CKS0
- 14.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode
- Section 15 Serial Communication Interface (SCI)
- 15.1 Overview
- 15.1.1 Features
- 15.1.2 Block Diagram
- 15.1.3 Pin Configuration
- 15.1.4 Register Configuration
- 15.2 Register Descriptions
- 15.2.1 Receive Shift Register (RSR)
- 15.2.2 Receive Data Register (RDR)
- 15.2.3 Transmit Shift Register (TSR)
- 15.2.4 Transmit Data Register (TDR)
- 15.2.5 Serial Mode Register (SMR)
- 15.2.6 Serial Control Register (SCR)
- 15.2.7 Serial Status Register (SSR)
- 15.2.8 Bit Rate Register (BRR)
- 15.2.9 Serial Interface Mode Register (SCMR)
- 15.2.10 Module Stop Control Register (MSTPCR)
- 15.3 Operation
- 15.3.1 Overview
- 15.3.2 Operation in Asynchronous Mode
- 15.3.3 Multiprocessor Communication Function
- 15.3.4 Operation in Synchronous Mode
- 15.4 SCI Interrupts
- 15.5 Usage Notes
- Section 16 I 2 C Bus Interface (IIC)
- 16.1 Overview
- 16.1.1 Features
- 16.1.2 Block Diagram
- 16.1.3 Input/Output Pins
- 16.1.4 Register Configuration
- 16.2 Register Descriptions
- 16.2.1 I 2 C Bus Data Register (ICDR)
- 16.2.2 Slave Address Register (SAR)
- 16.2.3 Second Slave Address Register (SARX)
- 16.2.4 I 2 C Bus Mode Register (ICMR)
- 16.2.5 I 2 C Bus Control Register (ICCR)
- 16.2.6 I 2 C Bus Status Register (ICSR)
- 16.2.7 Serial/Timer Control Register (STCR)
- 16.2.8 DDC Switch Register (DDCSWR)
- 16.2.9 Module Stop Control Register (MSTPCR)
- 16.3 Operation
- 16.3.1 I 2 C Bus Data Format
- 16.3.2 Master Transmit Operation
- 16.3.3 Master Receive Operation
- 16.3.4 Slave Receive Operation
- 16.3.5 Slave Transmit Operation
- 16.3.6 IRIC Setting Timing and SCL Control
- 16.3.7 Automatic Switching from Formatless Mode to I 2 C Bus Format
- 16.3.8 Noise Canceler
- 16.3.9 Sample Flowcharts
- 16.3.10 Initialization of Internal State
- 16.4 Usage Notes
- Section 17 A/D Converter
- 17.1 Overview
- 17.1.1 Features
- 17.1.2 Block Diagram
- 17.1.3 Pin Configuration
- 17.1.4 Register Configuration
- 17.2 Register Descriptions
- 17.2.1 A/D Data Registers A to D (ADDRA to ADDRD)
- 17.2.2 A/D Control/Status Register (ADCSR)
- 17.2.3 A/D Control Register (ADCR)
- 17.2.4 Module Stop Control Register (MSTPCR)
- 17.3 Interface to Bus Master
- 17.4 Operation
- 17.4.1 Single Mode (SCAN = 0)
- 17.4.2 Scan Mode (SCAN = 1)
- 17.4.3 Input Sampling and A/D Conversion Time
- 17.4.4 External Trigger Input Timing
- 17.5 Interrupts
- 17.6 Usage Notes
- Section 18 RAM
- 18.1 Overview
- 18.1.1 Block Diagram
- 18.1.2 Register Configuration
- 18.2 System Control Register (SYSCR)
- 18.3 Operation
- Section 19 ROM
- 19.1 Overview
- 19.2 Operation
- 19.3 Writer Mode (H8/3577, H8/3567, H8/3567U)
- 19.3.1 Writer Mode Setup
- 19.3.2 Socket Adapter Pin Assignments and Memory Map
- 19.4 PROM Programming
- 19.4.1 Programming and Verification
- 19.4.2 Notes on Programming
- 19.4.3 Reliability of Programmed Data
- Section 20 Clock Pulse Generator
- 20.1 Overview
- 20.1.1 Block Diagram
- 20.1.2 Register Configuration
- 20.2 Register Descriptions
- 20.2.1 Standby Control Register (SBYCR)
- 20.3 Oscillator
- 20.3.1 Connecting a Crystal Resonator
- 20.3.2 External Clock Input
- 20.4 Duty Adjustment Circuit
- 20.5 Medium-Speed Clock Divider
- 20.6 Bus Master Clock Selection Circuit
- 20.7 Universal Clock Pulse Generator [H8/3567 Series Version with On-Chip USB]
- 20.7.1 Block Diagram
- 20.7.2 Registers
- Section 21 Power-Down State
- 21.1 Overview
- 21.1.1 Register Configuration
- 21.2 Register Descriptions
- 21.2.1 Standby Control Register (SBYCR)
- 21.2.2 Module Stop Control Register (MSTPCR)
- 21.3 Medium-Speed Mode
- 21.4 Sleep Mode
- 21.4.1 Sleep Mode
- 21.4.2 Clearing Sleep Mode
- 21.5 Module Stop Mode
- 21.5.1 Module Stop Mode
- 21.5.2 Usage Note
- 21.6 Software Standby Mode
- 21.6.1 Software Standby Mode
- 21.6.2 Clearing Software Standby Mode
- 21.6.3 Setting Oscillation Settling Time after Clearing Software Standby Mode
- 21.6.4 Software Standby Mode Application Example
- 21.6.5 Usage Note
- 21.7 Hardware Standby Mode
- 21.7.1 Hardware Standby Mode
- 21.7.2 Hardware Standby Mode Timing
- Section 22 Electrical Characteristics
- 22.1 Absolute Maximum Ratings
- 22.2 DC Characteristics
- 22.3 AC Characteristics
- 22.3.1 Clock Timing
- 22.3.2 Control Signal Timing
- 22.3.3 Timing of On-Chip Supporting Modules
- 22.4 A/D Conversion Characteristics
- 22.5 USB Function Pin Characteristics
- 22.6 Usage Notes
- Appendix A CPU Instruction Set
- A.1 Instruction Set List
- A.2 Operation Code Map
- A.3 Number of States Required for Execution
- Appendix B Internal I/O Registers
- B.1 Addresses
- B.2 Register Selection Conditions
- B.3 Functions
- Appendix C I/O Port Block Diagrams
- C.1 Port 1 Block Diagrams
- C.2 Port 2 Block Diagrams
- C.3 Port 3 Block Diagram
- C.4 Port 4 Block Diagrams
- C.5 Port 5 Block Diagrams
- C.6 Port 6 Block Diagrams
- C.7 Port 7 Block Diagram
- C.8 Port 8 Block Diagrams
- C.9 Port D Block Diagram
- Appendix D Pin States
- D.1 Port States in Each Mode
- Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
- E.1 Timing of Transition to Hardware Standby Mode
- E.2 Timing of Recovery from Hardware Standby Mode
- Appendix F Product Code Lineup
- Appendix G Package Dimensions
- Colophon
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
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names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
Cautions
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contained therein.
Hitachi Single-Chip Microcomputer
H8/3577 Series, H8/3567 Series
H8/3577
HD6433577, HD6473577
H8/3574
HD6433574
H8/3567
HD6433567, HD6473567
H8/3564
HD6433564-20, HD6433564-10
H8/3567U
HD6433567U, HD6473567U
H8/3564U
HD6433564U
Hardware Manual
ADE-602-200A
Rev. 2.0
11/30/00
Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party's
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi's sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi's sales office for any questions regarding this document or Hitachi
semiconductor products.
Preface
The H8/3577 Series and H8/3567 Series comprise single-chip microcomputers built around the
H8/300 CPU and equipped with on-chip supporting functions required for system configuration.
Versions are available with PROM (ZTATTM) or mask ROM as on-chip ROM.
On-chip supporting functions include a16-bit free-running timer (FRT), 8-bit timer (TMR),
watchdog timer (WDT), two PWM timers (PWM and PWMX), a serial communication interface
(SCI), I
2
C bus interface (IIC), A/D converter (ADC), and I/O ports.
The H8/3577 Series comprises 64-pin models with the above supporting functions on-chip. The
H8/3567 Series comprises the 42-pin H8/3567 and H8/3564 with fewer PWM, ADC, and I/O port
channels, and the 64-pin H8/3567U and H8/3564U with on-chip universal serial bus (USB) hubs
and function.
Use of the H8S/3577 Series or H8S/3567 Series enables compact, high-performance systems to be
implemented easily. The comprehensive timer functions and their interconnectability (timer
connection facility) make these series ideal for applications such as PC monitor systems.
This manual describes the hardware of the H8/3577 Series and H8/3567 Series. Refer to the
H8/300 Series Programming Manual for a detailed description of the instruction set.
Note: * ZTAT (Zero Turn-Around Time) is a trademark of Hitachi, Ltd.