11-321
Product Description
Ordering Information
Typical Applications
Features
Functional Block Diagram
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Optimum Technology Matching Applied
Si BJT
GaAs MESFET
GaAs HBT
Si Bi-CMOS
SiGe HBT
Si CMOS
InGaP/HBT
GaN HEMT
SiGe Bi-CMOS
CCA
RX VGC
802.11
Preamble/
Header
802.11
Preamble/
Header
Control
Port
RXVGC
DAC
Q IN
ADC
TX VGC
DAC
I OUT
DAC
Q OUT
DAC
M
odu
l
a
tor
Mode Control
Tx Length
Tx Signal
Service
D
e
m
o
dul
at
or
RX VGC
ANT SEL
TX VGC
I OUT
Q OUT
M CLK
TX PE
RX PE
TX DATA
TX RDY
SPI
RX RDY
RX DATA
CCA
VREF IN
Q IN
I IN
ADC
I IN
Data Converter
Reference
LNA GS
DATA CLK
RF3000
SPREAD-SPECTRUM BASEBAND MODEM
IEEE802.11b Wireless LAN Systems
ISM Band Systems
Direct Sequence Systems
Wireless Modems
Wireless Point-to-Point
The RF3000 is a monolithic CMOS baseband processor.
It is suitable for use in 11Mbps IEEE802.11b wireless
LAN systems, and contains all functions required to con-
vert a spread-spectrum signal to bit stream. The on-chip
equalizer provides protection against multi-path in high
data rate modes. All functions are configurable via an SPI
port. A complete 2.4GHz radio reference design is avail-
able from RFMD.
On-Chip ADCs and DACs, RSSI, AGC
BPSK/QPSK/CCK
250nS Delay Spread Equalizer
Supports Antenna Diversity
Reference Design Available
RF3000
Spread-Spectrum Baseband Modem
RF3000 PCBA
Fully Assembled Evaluation Board
0
Rev A4 031216
0.25
0.19
8 MAX
0 MIN
1.27
0.40
6.20
5.80
0.64
0.30
0.20
4.00
3.80
10.00
9.80
1.75
1.35
0.25
0.10
-A-
NOTES:
1. Shaded lead is Pin 1.
2. All dimensions are excluding mold flash.
3. Lead coplanarity - 0.10 with respect to datum "A".
Package Style: SSOP-28
11-322
RF3000
Rev A4 031216
Absolute Maximum Ratings
Parameter
Rating
Unit
Supply Voltage
+4.0
V
DC
Input, Output or I/O Voltage
Ground-0.5 to VCC+0.5
V
DC
Voltage
2.7 to 3.6
V
VDDD Output
2.7
V
DC
Max. Storage Temperature
-65 to +150
C
Max. Junction Temperature
+150
C
Operating Ambient Temperature
-40 to +85
C
Parameter
Specification
Unit
Condition
Min.
Typ.
Max.
DC Electrical
See Figures 15 and 16.
V
CC
=3.0V to 3.3V+10%,
T
Z
=-40C to +85C
Power Supply Voltage
2.7
3.3
3.6
V
VDDA
TBD
2.2
TBD
V
VDDD, Output Only.
V
REF
1.6
1.7
1.8
V
No current draw.
Input Voltage
2.5
VDDA+0.2
V
Logical "1" (V
IH
)
-0.2
+0.7
V
Logical "0" (V
IL
)
Output Voltage
TBD
VDDA-1.0
TBD
V
Logical "1" (V
OH
)
TBD
0.2
0.7
V
Logical "0" (V
OL
)
Current Consumption
25
TBD
mA
Transmit Mode (I
TX
)
50
TBD
mA
Receive Mode (I
RX
)
Sleep Mode
500
500
A
Mode 1, Reset Active, No Clocks (I
S1
)
1.5
1.5
mA
Mode 2, Reset Inactive, No Clocks (I
S2
)
Input Leakage Current
10
A
I
I
Output Leakage Current
10
A
I
O
Output Loading
20
20
pF
AC Electrical
V
CC
=3.0V to 3.3V+10%,
T
A
=-40C to +85C. See Note 1.
M CLK Duty Cycle
40/60
60/40
%
Rise/Fall
-
10
nS
All outputs. See Notes 2 and 3.
TXPE to I
OUT
/Q
OUT
3.0
3.1
S
1st valid chip. 802.11 modes.
TXDATA to I/Q
OUT
1.0
S
TXPE Inactive Width
1
S
See Notes 2 and 4.
TXRDY Active to
1st DATACLK Hi
500
nS
Setup TXDATA to DATACLK
10
nS
Hold TXDATA to DATACLK Hi
10
nS
Reset to TXPE
100
S
Reset to RXPE
100
S
TXDATA Modulation Extension
2
S
See Notes 2 and 5.
RXPE Inactive Width
0
nS
See Notes 2 and 6.
DATACLK Period
90
nS
11Mbps Mode
DATACLK Width Hi or Low
22
44
68
nS
11Mbps Mode
DATACLK to RX Data
30
nS
RXRDY to 1st DATACLK
40
nS
See Note 2.
RXDATA to 1st DATACLK
40
nS
Setup RXDATA to DATACLK
30
nS
RESET Width Active
40
nS
See Note 2.
RXPE to CCA Valid
15
S
See Note 2.
RXPE to RSSI Valid
15
S
See Note 8.
I/Q
IN
to RXDATA
2.25
S
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
11-323
RF3000
Rev A4 031216
Notes:
1. AC tests performed with C
L
=20pF, I
OL
=2mA, and I
OH
=-1mA. Input reference level all inputs V
CC
/2. Test V
IH
=V
CC
,
V
IL
=0V; V
OH
=V
OL
=V
CC
/2.
2. Not tested, but characterized at initial design and at major process/design changes.
3. Measured from V
IL
to V
IH
.
4. TX PE must be inactive before going active to generate a new packet.
5. I
OUT
/Q
OUT
are modulated after last chip of valid data to provide ramp-down time for RF/IF circuits.
6. A new search will begin after last bit of 802.11 packet in 802.11 modes.
7. Centered about 1.7V V
REF
.
8. Accurate to within 3dB of final gain setting.
Parameter
Specification
Unit
Condition
Min.
Typ.
Max.
I/Q ADC
Full Scale Input Voltage
0.7
+10%
V
P-P
See Note 7.
Input Bandwidth
11
MHz
Input Capacitance
5
pF
Input Impedance
50
k
I/Q DAC
Full Scale Output Voltage
200
mV
See Note 7.
Sample Rate
11
MHz
Resolution
6
bits
DNL
0.5
LSB
INL
0.5
1.0
LSB
Tested for monotonicity.
TX VGC DAC
Maximum Gain Output Voltage
1.2
V
Minimum Gain Output Voltage
2.0
V
Resolution
6
bits
DNL
0.5
LSB
INL
0.5
1.0
LSB
Tested for monotonicity.
RX VGC DAC
Maximum Gain Output Voltage
1.2
V
Minimum Gain Output Voltage
2.0
V
Resolution
6
bits
DNL
0.5
LSB
INL
0.5
1.0
LSB
Tested for monotonicity.
Control Port Timing
Characteristics
SPI Mode
Mode Switching Characteristics.
See Figure 3.
C CLK Clock Frequency
6
MHz
f
CLK
CS High Time Between
Transmissions
1.1
S
t
CSH
CS Falling to C CLK Edge
22
nS
t
CSS
C CLK Low Time
68
nS
t
CLKL
C CLK High Time
68
nS
t
CLKH
CD IN to C CLK Setup Time
42
nS
t
DSU
C CLK Rising to Data Hold Time
16
nS
t
DHLD
C CLK Falling to CD OUT Stable
47
nS
t
PD
11-324
RF3000
Rev A4 031216
For more information on Figure 1, see parameter table (on previous pages).
CCLK
CDIN
CSb
CDOUT
Figure 1. SPI Timing Transition Detail
DATACLK
TXDATA
TXPE
TXRDY
ss
ss
ss
ss
Figure 2. Transmit Port Detail Timing
DATACLK
RXDATA
RXPE
RXRDY
ss
ss
ss
ss
Figure 3. Receiver Port Detail Timing
11-325
RF3000
Rev A4 031216
Index
G
ENERAL
D
ESCRIPTION
Figure 4. 2.4GHz IEEE802.11b Chipset Diagram
Figure 5. RF3000 Block Diagram
SPI C
ONTROL
P
ORT
SPI Mode Description
SPI Mode Pin Definitions Table
SPI Method of Operation
Write
Read
SPI Operation Summary
Write
Read
SPI Mode Functional Timing Diagrams
Figure 6. SPI Write Functional Timing Diagram
Figure 7. SPI Read Functional Timing Diagram
M
ETHOD
OF
O
PERATION
IEEE802.11b Transmit Modes
IEEE802.11b DSSS Transmit Modes
IEEE802.11b DSSS Transmission Summary
Figure 8. IEEE802.11b Transmit Timing Overview
Figure 8a. Alternate Transmit Interface
IEEE802.11b Receive Mode
Diversity
Figure 9. Diversity and AGC Algorithm
AGC Algorithm
Figure 10. AGC Decision Structure
AGC Calibration
Figure 11. High Gain Mode (LNAGS=1) Plot of
RXVGC Showing Normal Operation and Calibration
Ranges
Figure 12. Low Gain Mode (LNAGS=0) Plot of
RXVGC Showing Normal Operation and Calibration
Ranges
High Gain Calibration Procedure
Low Gain Calibration Procedure
Post-AGC
IEEE802.11b DSSS Receive Summary
Figure 13. IEEE802.11b Receive Timing Overview
Figure 13a. Alternate Receiver Interface
B
LOCK
D
IAGRAM
B
REAKOUT
Modulator
PSK Modes
CCK Mode
IEEE802.11b Preamble/Header Creation and
Assembly
Demodulator
PSK Modes
CCK Mode
IEEE802.11b Preamble/Header Detection and
Extraction
Data Converters
A/D Converters
D/A Converters
RSSI, CCA and AGC
Scramblers
Diversity
Equalizer
C
ONTROL
P
ORT
R
EGISTER
D
EFINITIONS
FOR
RF3000
Register 0x0 - Reserved
Register 0x01 - Modem Control and RX Status
Mode 3-0 - TX Mode Table
Register 0x02 - CCA Control
CCA1, CCA0 - 802.11 CCA Mode Table
Register 0x03 - Diversity and RSSI Value
Register 0x04 - RX Signal Field
Register 0x05 - RX Length Field MSB's
Register 0x06 - RX Length Field LSB's
Register 0x07 - RX Service Field
Register 0x08 - Reserved
Register 0x09 - Reserved
Register 0x0A - Reserved
Register 0x0B - Reserved
Register 0x0C - Reserved
Register 0x0D - Reserved
Register 0x0E - Reserved
Register 0x0F - Reserved
Register 0x10 - Reserved
Register 0x11 - TX Variable Gain and TX Length Field
Extension
Scrambler Mode Table
Register 0x12 - TX Length Field MSB's
Register 0x13 - TX Length Field LSB's
Register 0x14 - Low Gain Calibration
Register 0x15 - High Gain Calibration
Register 0x16 - Reserved
Register 0x17 - Reserved
Register 0x18 - Reserved
Register 0x19 - Reserved
Register 0x1A - Reserved
Register 0x1B - Reserved
Register 0x1C - Options Register 1
Register 0x1D - Options Register 2
Register 0x1E - Reserved
Register 0x1F - Reserved
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