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Product Description
Ordering Information
Typical Applications
Features
Functional Block Diagram
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Optimum Technology Matching Applied
Si BJT
GaAs MESFET
GaAs HBT
Si Bi-CMOS
SiGe HBT
Si CMOS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
NC
VCC1
VCC2
GND1
LNA IN
GND2
GND3
NC
GND4
VCC3
LO BUFF EN
LO IN
NC
GND9
VCC4
GND8
LNA OUT
GND7
MIX RF IN
GND6
IF-
IF+
GND5
LO BUFF OUT
RF9986
PCS LOW NOISE AMPLIFIER/MIXER
CDMA/TDMA/DCS1900 PCS Systems
PHS 1500/WLAN 2400 Systems
General Purpose Down Converter
Micro-Cell PCS Base Stations
Portable Battery-Powered Equipment
The RF9986 is a monolithic integrated receiver front-end
for PCS, PHS, and WLAN applications. The IC contains
all of the required components to implement the RF func-
tions of the receiver front-end except for the passive filter-
ing and LO generation. It contains an LNA (low-noise
amplifiers), a double-balanced Gilbert cell mixer, a bal-
anced IF output, an LO isolation buffer amplifier, and an
LO output buffer amplifier for providing the buffered LO
signal as an output. The IC is designed to operate from a
single 3.6V power supply.
Complete Receiver Front-End
Extremely High Dynamic Range
Single 3.6V Power Supply
External LNA IP3 Adjustment
1500MHz to 2500MHz Operation
RF9986
PCS Low Noise Amplifier/Mixer
RF9986 PCBA
Fully Assembled Evaluation Board
8
Rev B1 010717
8MAX
0MIN
1
0.050
0.016
0.0098
0.0075
0.2440
0.2284
0.025
0.012
0.008
0.0688
0.0532
0.157
0.150
0.0098
0.0040
0.344
0.337
Package Style: SSOP-24
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Absolute Maximum Ratings
Parameter
Rating
Unit
Supply Voltage
-0.5 to 7.0
V
DC
Input LO and RF Levels
+6
dBm
Ambient Operating Temperature
-40 to +85
C
Storage Temperature
-40 to +150
C
Parameter
Specification
Unit
Condition
Min.
Typ.
Max.
Overall
T = 25C, V
CC
= 3.6V, RF = 1959MHz,
LO= 1749MHz @ -2dBm
RF Frequency Range
1500
2500
MHz
LO Frequency Range
1200
2500
MHz
IF Frequency Range
DC to 500
MHz
Cascaded Performance
1k
balanced load, 2.5dB Image Filter Loss.
Cascade Conversion Gain
22
25
dB
Cascade Input IP3
-15.0
-10.0
dBm
Cascade Noise Figure
2.5
dB
Single Sideband
First Section (LNA)
The LNA section may be left unused. Power
is not connected to pin 1. The performance
is then as specified for the Second Section
(Mixer).
Noise Figure
1.4
dB
Input VSWR
<2:1
Input is internally matched for optimum noise
figure from a 50
source.
Input IP3
+5.5
dBm
IP3 may be increased 10dB by connecting
pin 22 to V
CC
through the matching inductor.
The LNA's current then increases by 10mA.
Other in-between IP3 vs. I
CC
trade-offs may
be made. See pin description for pin 20.
Gain
12
dB
Reverse Isolation
23
dB
Output VSWR
<1.5:1
Second Section (Mixer)
With 1k
balanced load.
Noise Figure
5.5
dB
Single Sideband
Input VSWR
1.5:1
Input IP3
-0.5
dBm
Conversion Gain
15.5
dB
Output Impedance
1
k
Balanced
LO Input
LO Input Range
-5 to +3
dBm
LO Output Level
-4
+1
dBm
Buffer On, -2dBm input
-25
-20
dBm
Buffer Off, -2dBm input
LO to RF (Mix In) Rejection
30
dB
LO to IF1, IF2 Rejection
20
dB
LO Input VSWR
<2:1
Single ended
Power Supply
Voltage
2.7
3.65%
5.0
V
Current Consumption
5
mA
LNA only
52
mA
LNA + Mixer, LO Buffer On
48
mA
LNA + Mixer, LO Buffer Off
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
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Pin
Function
Description
Interface Schematic
1
NC
No connection. This pin may be grounded (recommended) or left open.
2
VCC1
Supply voltage for the mixer and RF buffer amplifier. External RF
bypassing is required. The trace length between the pin and the bypass
capacitor should be minimized. The ground side of the bypass capaci-
tor should connect immediately to ground plane.
3
VCC2
Supply voltage for the LNA. External RF bypassing is required. The
trace length between the pin and the bypass capacitor should be mini-
mized. The ground side of the bypass capacitor should connect imme-
diately to ground plane.
4
GND1
Ground connection for the LNA. For best performance, keep traces
physically short and connect immediately to ground plane.
5
LNA IN
RF Input pin for the LNA. This pin is internally DC-blocked and inter-
nally matched for minimum noise figure (NOT for minimum VSWR),
given a 50
source impedance.
6
GND2
Same as pin 4.
7
GND3
Ground connection for the RF buffer amplifier. For best performance,
keep traces physically short and connect immediately to ground plane.
8
NC
No connection. This pin may be grounded (recommended) or left open.
9
GND4
Same as pin 7.
10
VCC3
Supply voltage for both LO buffer amplifiers. External RF bypassing is
required. The trace length between the pin and the bypass capacitor
should be minimized. The ground side of the bypass capacitor should
connect immediately to ground plane.
11
LO BUFF
EN
Enable pin for the LO output buffer amplifier. This is a digitally con-
trolled input. A logic "high" (
3.1V) turns the buffer amplifier on, and the
current consumption increases by 3mA (with -2dBm LO input). A logic
"low" (
0.5V) turns the buffer amplifier off.
12
LO IN
Mixer LO input pin. This pin is internally DC-blocked and matched to
50
.
13
LO BUFF
OUT
Optional buffered LO output. This pin is internally DC-blocked and
matched to 50
. The buffer amplifier is switched on or off by the volt-
age level at pin 11.
14
GND5
Ground connection for both LO buffer amplifiers. For best performance,
keep traces physically short and connect immediately to ground plane.
15
IF+
Open-collector IF output pin. This is a balanced output. The output
impedance is set by an internal 1000
resistor to pin 16. Thus the dif-
ferential IF output impedance is 1000
. The resistor sets the operating
impedance, but an external choke or matching inductor to V
CC
must be
supplied in order to bias this output. This inductor is typically incorpo-
rated in the matching network between the output and IF filter. Because
this pin is biased to V
CC
, a DC blocking capacitor must be used if the IF
filter input has a DC path to ground.
16
IF-
Same as pin 15, except complementary output.
See pin 15.
17
GND6
Ground connection for the mixer. For best performance, keep traces
physically short and connect immediately to ground plane.
18
MIX RF IN
Mixer RF Input Pin. This pin is internally DC-blocked and matched to
50
.
19
GND7
Same as pin 17.
150
VCC1
VCC4
BIAS
7.5 k
LO
BUFF
EN
1 k
IF-
IF+
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Application Schematic
Pin
Function
Description
Interface Schematic
20
LNA OUT
LNA output pin. This is an open-collector output. This pin is typically
connected to pin 22 through a bias/matching inductor. This inductor, in
conjunction with a series blocking/matching capacitor, forms a match-
ing network to the 50
image filter and provides bias (see Application
Schematic). The LNA's IP3 may be increased 10dB by connecting pin
20 to V
CC
through the inductor. The LNA's current then increases by
10mA. Other in-between IP3 vs. I
CC
trade-offs may be made by con-
necting resistance values between V
CC
and the matching inductor. The
two reference points for consideration are with 150
used, which is
what connection to pin 22 achieves, the Input IP3 is +5.5dBm and the
LNA I
CC
is 5mA. Using no resistance, the Input IP3 is +15.5 dBm and
the LNA I
CC
is 15 mA. Desired operating points in between these val-
ues may be interpolated, roughly.
21
GND8
Same as pin 17.
22
VCC4
Output supply voltage for the LNA output (pin 20). This pin is typically
connected to pin 20 through a bias/matching inductor (see application
schematic). External RF bypassing is required. The trace length
between the pin and the bypass capacitor should be minimized. The
ground side of the bypass capacitor should connect immediately to
ground plane.
See pin 2.
23
GND9
Same as pin 17.
24
NC
No connection. This pin may be grounded (recommended) or left open.
LNA
OUT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
22 pF
LO BUFF EN
(On:
3.1 V;
Off:
0.5 V)
LO IN
V
CC
22 pF
2.7 nH
1.8 pF
RF Image
Filter, 50
22 pF
V
CC
C2
Filter
IF-
IF+
1 nF
C1
L1
22 pF
C1
L1
1 nF
V
CC
LO BUFF OUT
Z
FILTER
= 1 k
Z
OUT
= 1 k
Measurement
Reference Plane
L1 and C2 serve dual purposes. L1 serves as an output bias choke, and C2 serves as a series DC block. In addition, the
values of L1 and C2 may be chosen to form an impedance matching network if the IF filter's input impedance is not 1000
.
Otherwise, the values of L1 and C1 are chosen to form a parallel-resonant tank circut at the IF when the IF filter's input
impedance is 1000
.
RF IN
22 pF
C2
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Evaluation Board Schematic
(IF=210MHz)
(Download Bill of Materials from www.rfmd.com.)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
P1-1
C16
22 pF
C17
1 nF
P1-1
C18
22 pF
C19
1 nF
P1-3
C23
1 nF
C20
22 pF
R2
1 k
J1
LNA IN
J2
LO IN
C29
100 pF
C30
100 pF
L5
220 nH
T1
5.5:1
C11
1.5 pF
L4
47 nH
C8
5 pF
L1
2.7 nH
R3
See Note 2
P1-1
C10
22 pF
C4
1 pF
50
strip
C1
22 pF
C5
22 pF
C2
22 pF
C3
22 pF
50
strip
J4
IF OUT
J5
MIXER IN
J6
LNA OUT
J3
LO OUT
L2
470 nH
L3
470 nH
P1-1
C21
22 pF
C22
1 nF
C24
4.7
F
Drawing 9986400, Rev -
Notes:
1. C11 is selected to fine tune L4 for IF output match at 210 MHz.
2. R3 is not normally populated. For applications requiring additional LNA IP3, see the datasheet for
recommended resistance values.
3. C2 and C3 are not normally populated. If C2 and C3 are populated, the LNA and mixer can be tested
independently; in this case, C1 and C5 should be removed.
50
strip
1
2
3
P1
P1-3
BUFFER ENABLE
GND
P1-1
VCC
50
strip
50
strip
50
strip
50
strip
FL1
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Evaluation Board Layout
3" x 3"
Assembly
Top layer
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RF9986
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Bottom Layer
Internal Ground
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