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RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Product Description
Features
Optimum Technology Matching Applied
Si BJT
Si Bi-CMOS
GaInP/HBT
GaAs HBT
SiGe HBT
GaN HEMT
GaAs MESFET
Si CMOS
SiGe Bi-CMOS
Ordering Information
To Antenna
Voltage
Reg
2.4 GHz
Direct
Conversion
Transceiver
MODEM
Internal
32 kHz
Clock
Sleep Control
Bluetooth
Baseband
with CVSD
Fast
Locking
PLL
Up to 2 Mbs
ROM
HCI
Firmware
Audio
CODEC
Interface
SRAM
Data
GPIO
USB
Power
Management
UART
ARM7TDMI
Processor
USB Full
Speed
System I/O
CODEC
Master or
Slave
2.
3 ~
3.
63
V
Crystal or Reference Clock
SiW3000
ULTIMATEBLUETM
RADIO PROCESSOR
The SiW3000 UltimateBlueTM Radio Processor is a recent innovation for
Bluetooth wireless technology. It combines the industry's best performing
and most highly integrated radio design with an ARMTDMI processor
using CMOS technology. The SiW3000 uses direct conversion (zero-IF)
architecture. This allows digital filtering for excellent interference rejection as
compared to low IF solutions and also results in fewer spurious responses.
The lower-layer protocol stack software is integrated into the on-chip ROM.
Optional external Flash memory is also supported. The SiW3000 is
compliant with Bluetooth specification 1.2 features.
The device is available in multiple packages and bare die form with a
guaranteed operating temperature range from -40C to +85C and an
extended high temperature range to +105C.
Single-chip IC with 2.4 GHz
transceiver, baseband processor,
and on-chip protocol stack for
Bluetooth wireless technology
Compliant with Bluetooth
specification 1.2 features.
Low cost 0.18 m CMOS process
technology.
1.8 V analog and digital core
voltages; 1.62 V to 3.63 V external
I/O interface voltage.
Typical -85 dBm receiver sensitivity,
+2 dBm transmitter power for up to
100 meters nominal range.
On-chip VCO and PLL support
multiple GSM/GPRS and CDMA
cellular reference clock frequencies.
Hardware AGC dynamically adjusts
receiver performance in changing
environments.
Integrated 32-bit ARMTDMI
processor for extended features.
Full piconet connectivity with support
for up to 7 active and 8 parked
slaves.
Scatternet compatible with
Microsoft HID devices.
Supports three SCO voice channels.
Channel Quality Driven Data Rate
(CQDDR) controls multi-slot packets
to minimize packet overhead and
maximize data throughput.
Option for Bluetooth + Wi-Fi
coexistence.
Applications
Mobile phones.
Notebook and desktop PCs.
Cordless headsets.
Personal digital assistants (PDAs).
Computer accessories, peripherals,
and wireless printers/
keyboards/mice).
SiW3000
UltimateBlueTM Radio Processor
0
60 0049 R01Drf SiW3000 Radio Processor DS
Block Diagram
September 30, 2004
2 of 24
SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
Radio Features
Direct-conversion architecture with no external IF filter or VCO resonator components.
Single ended RF I/O reduces system bill of materials (BOM) costs by eliminating the need to use external balun and
switch circuits.
On-chip VCO and PLL support multiple GSM, CDMA, GPRS standard reference clock frequencies.
Low out-of-band spurious emission transmitter prevents blocking of sensitive mobile phone RF circuits.
No tuning during production.
Internal temperature compensation circuit stabilizes performance across wide operating temperature.
Fast settling synthesizer reduces power consumption.
Up to 100 meter operating range in standard configuration without using an external PA.
Baseband Features
ARM7TDMI processor core running at 16 MHz.
Digital GFSK modem for maximum performance and lower packet error rate.
On-chip CVSD conversion with hardware based gain adjustments to enhance audio quality.
Sleep control interface for low power operation modes.
Software execution from ROM or external FLASH memory.
Standard Protocol Stack Features
Full piconet connectivity with support for up to 7 active and 8 parked slaves.
Able to establish up to 3 SCO connections.
Scatternet capable and compatible with Microsoft HID devices.
Standard Bluetooth test modes.
Low power connection states supported with hold, sniff, and park modes.
Additional Protocol Stack Features
Channel Quality Driven Data Rate (CQDDR) optimizes data transfer rate in noisy or weak signal environments
Audio (SCO) routing over HCI interface for VOIP applications.
Support for Bluetooth + Wi-Fi coexistence technology.
Verified compatibility with multiple upper-layer stack vendors.
Extensive vendor specific HCI commands enables hardware specific controls.
Optional upper-layer stack and profiles can be licensed and integrated into the IC.
Bluetooth 1.2 Features
Adaptive frequency hopping (AFH).
Faster connections.
LMP improvements.
External System Interfaces
Host HCI Transport (H:2 USB)
The USB device interface provides a physical transport between the SiW3000 and the host for the transfer of Bluetooth
control signals and data. This transport layer is fully compliant with Section H:2 of the Bluetooth specification with all end
points supported. The SiW3000 USB interface encompasses three I/O signals: USB_DPLS, USB_DMNS, and
USB_DPLS_PULLUP. If the USB transport is not used, the USB_DPLS and USB_DMNS pins should be grounded to
reduce current consumption.
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SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
Host HCI Transport (H:4 UART)
The high speed UART interface provides the physical transport between the SiW3000 and the application host for the
transfer of Bluetooth control signals and data compliant to Section H:4 of the Bluetooth specification. The table below
shows the supported baud rates. The default baud rate is 115,200, but can be configured depending on the application.
Host HCI Transport (H:5 3-Wire UART)
To reduce the number of signals and increase reliability of the HCI UART interface, a 3-wire UART using either the
Bluetooth H:5 or BCSP protocol is supported. The selection between H:4, H:5, and BCSP is done automatically by the
SiW3000, or can be set in NVM.
Audio CODEC Interface
The SiW3000 supports direct interface to an external audio CODEC or PCM host device. The interface is easily config-
ured to support:
Standard 64-kHz PCM clock rate.
Up to 2-MHz clock rates with support for multi-slot handshakes and synchronization.
Either master or slave (Motorola SSI) mode.
Configuration of the CODEC interface is done by the firmware during boot-up by reading non-volatile memory (NVM)
parameters. The following are examples of supported CODEC modes:
Generic 64-kHz audio CODEC (e.g., OKI MSM-7702).
Motorola MC145481 or similar CODEC as master.
QUALCOMM MSM chip set audio port.
GSM/GPRS baseband IC audio ports.
Programmable I/O (PIO)
Up to twenty-nine (29) programmable IO (PIO) ports are available for customer use in the SiW3000. Three of these PIOs
are dedicated and the remaining PIOs are shared with other functions. Availability of PIOs will depend on system config-
uration. The table below identifies the all twenty-nine PIOs and their usage. The PIO ports can be set to input or output.
Reading, writing, and controlling the PIO pins by the host application software can be done via vendor specific HCI com-
mands.
SiW3000 Radio Processor HCI UART Parameters
Required Host Setting
Number of data bits
8
Parity bit
No parity
Stop bit
1 stop bit
Flow control
RTS/CTS
Host flow-off response requirement from the SiW3000
8 bytes
SiW3000 IC flow-off response requirement from host
2 bytes
Supported baud rates
9.6k, 19.2k, 38.4k, 57.6k, 115.2k
a
, 230.4k, 460.8k, 500k, 921.6k,
1M, 1.5M, 2M
a.Default baud rate.
SiW3000 Radio Processor HCI 3-Wire UART Parameters
Required Host Setting
Number of data bits
8
Parity bit
Even
Stop bit
1 stop bit
Error detection
Slip and checksum
Sleep modes
Shallow and deep
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SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
External Memory Interface
The Ultimate 3000 Radio Processor is a true single chip device and does not require additional memory for standard
below HCI protocol functions. An external memory interface is available for adding optional memory. If external Flash
memory will be used, the read access time of the device must be 100 ns or less.
The external memory interface permits connection to Flash and SRAM devices. The interface has an 18-bit address bus
and a 16-bit data bus for a total addressable memory of 512 KB. In certain embedded applications, both SRAM and
Flash can be installed by using the high order address bit as an alternate chip select.
External EEPROM Controller and Interface
This interface is intended for use with ROM-based solutions. The EEPROM is not required for configurations with exter-
nal flash. The EEPROM is the non-volatile memory (NVM) in the system and contains the system configuration parame-
ters such as the Bluetooth device address, the CODEC type, as well as other parameters. These default parameters are
set at the factory, and some parameters will change depending on the system configuration. Optionally, the non-volatile
memory parameters can be downloaded from the host processor at boot up eliminating the need for EEPROM. Please
consult the application support team for details. The EEPROMs should have a serial I
2
C interface with a minimum size of
2 Kbits and 16-byte page write buffer capabilities.
Power Management
The HOST_WAKEUP and EXT_WAKE signals are used for power management. HOST_WAKEUP is an output signal
used to wake up the host. EXT_WAKE is an input signal used by the host to wake up the SiW3000 Radio Processor from
sleep mode. For more information on the usage of HOST_WAKE and EXT_WAKE, please refer to RFMD application
note 62 0031.
PIO#
Shared I/O
Sampled at Reset
PIO#
Shared I/O
Sampled at Reset
0
None
Yes
15
PCM_OUT No
1
None
Yes
16
PCM_IN No
2
None
Yes
17
PCM_CLK No
3
D[8] No
18
PCM_SYNC
No
4
D[4] No
19
EXT_WAKE
No
5
D[5] No
20
HOST_WAKEUP
No
6
D[6] No
21
UART_RXD
No
7
D[7] No
22
UART_TXD
No
8
PWR_REG_EN No
23
UART_CTS No
9
D[15] No
24
UART_RTS
No
10
WE_N No
25
A[18] No
11
A[16] No
26
TX_RX_SWITCH
No
12
A[17] No
27
D[9] No
13
A[11] No
28
D[10] No
14
USB_DPLS_PULLUP No
Signal
Description
Address A[1] - A[18]
18-bit address bus
Data D[0] - D[15]
16-bit data bus
FCS_N
Chip select
OE_N
Output enable
WE_N
Write enable
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SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
General System Requirements
System Reference Clock
The SiW3000 chip can use either an external crystal or a reference clock as the system clock input. The supported fre-
quencies are: 9.6 MHz, 12 MHz, 12.8 MHz, 13 MHz, 14.4 MHz, 15.36 MHz, 16 MHz, 16.8 MHz, 19.2 MHz, 19.68 MHz,
19.8 MHz, 26 MHz, 32 MHz, 38.4 MHz, and 48 MHz. The default reference frequency can be selected by setting the
proper system configuration parameter in the non-volatile memory (NVM). If the USB HCI transport will be used, the ref-
erence clock must be 32 MHz.
The system reference crystal/clock must have accuracy of 20 PPM or better to meet the specification of Bluetooth. To
facilitate design and production, the SiW3000 processor incorporates internal crystal calibration circuits to allow factory
calibration of initial crystal frequency accuracy.
Low Power Clock
For the Bluetooth low power clock, a 32.768-kHz crystal may be used to drive the SiW3000 oscillator circuit, or alterna-
tively, a 32.768-kHz reference clock signal can be used instead of a crystal. If the lowest power consumption is not
required during low-power modes such as sniff, hold, park, and idle modes, the 32.768-kHz crystal may be omitted in the
design. If the 32.768-kHz clock source will be used, the clock source should be connected to the CLK32_IN pin and must
meet the following requirements:
For AC-coupled via 100 pF or greater (peak-to-peak voltage):
400 mV
P-P
< CLK32_IN < V
DD_C
For DC-coupled:
CLK32_IN minimum peak voltage < VIL
CLK32_IN maximum peak voltage > VIH
Where V
IL
= 0.3 * V
DD_C
Where V
IH
= 0.7 * V
DD_C
For both cases, the signal is not to exceed:
-0.3 V < CLK32_IN < V
DD_C
+ 0.3 V
Also, the CLK32_OUT pin must be coupled to V
DD_P
or GND through a 100 nF capacitor.
Power Supply Description
The SiW3000 Radio Processor operates at 1.8 V core voltage for internal analog and digital circuits. The chip has inter-
nal analog and digital voltage regulators simplifying power supply requirements to the chip. The internal voltage regula-
tors can be supplied directly from a battery or from other system voltage sources. Optionally, the internal regulators can
be by-passed if 1.8 V regulated source is available on the system.
Note: Both regulators can be bypassed if external regulation is desired. When bypassing the analog regulator, the VBATT_ANA and VCC_OUT pins
must be tied together and the external analog voltage (1.8 V) should be applied to the VBATT_ANA pin. When bypassing the digital regulator, the
VBATT_DIG pin should be left unconnected and the external digital voltage (1.8 V) should be applied to VBB_OUT pin.
The power for the I/Os is taken from a separate source (V
DD_P
). V
DD_P
can range from 1.62
to
3.63 Volts to maintain
compatibility with a wide range of peripheral devices. Please check the pin list for the exact pins that are powered from
the V
DD_P
source. Power for the USB circuits is taken from a separate source (V
DD_USB
).
Function
Internal Analog Regulator
Internal Digital Regulator
Regulator input pin
V
BATT_ANA
= 2.3 to 3.63 V
V
BATT_DIG
= 2.3 to 3.63 V
Regulator output pin
V
CC_OUT
= 1.8 V
V
DD_C
= 1.8 V
Table 1. Internal Regulator Used
Function
Analog Core Circuits
Digital Core Circuits
Circuit voltage supply pin
V
CC
= 1.8 V
V
DD_C
= 1.8 V
Table 2. Internal Regulator Bypassed
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SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
RF I/O Description
The SiW3000 processor employs single-ended RF input and output pins for reduced external components. In typical
Class-2 (0 dBm nominal) applications, simple LC network matching circuits will be required to combine the two ports into
a single antenna port and provide impedance matching. Please refer to the RF impedance table and the application cir-
cuits for values and matching circuit examples. The SiW3000 can be used to design Class-1 (+20 dBm) products with
the addition of power amplifier circuits. Control signals are available to facilitate the design of the external PA circuit.
Reset
The SiW3000 processor can be reset by asserting the RESET_N signal to the chip (active low). Upon applying power,
the RESET_N must be asserted until voltage supply and internal voltage regulators have stabilized. A simple RC circuit
can be used to provide the power-on reset signal to the SiW3000.
On-Chip Memory
The SiW3000 Radio Processor integrates both SRAM and ROM. The ROM is pre-programmed with Bluetooth protocol
stack software (HCI software) and boot code that executes automatically upon reset. The boot code serves to control the
boot sequence as well as to direct the execution to the appropriate memory for continued operation.
Configuration Selection
HCI Transport Interface Selection
The HCI transport (USB or UART) is selected on power up by sampling PIO2. If UART is selected, the selection of the
particular UART transport (H:4 or H:5) is performed automatically by the software.
Reference Frequency Selection
The SiW3000 radio processor is designed to operate with multiple reference frequencies. During boot up the processor
samples PIO pins to determine the default reference frequency. If the USB transport is selected, the default reference
frequency will always be 32 MHz. If the UART transport is selected, the reference frequency setting will be set according
to the following table:
Application Software Memory Selection
The SiW3000 can support application (protocol stack) software execution from internal ROM and external FLASH mem-
ory. To run from internal ROM, D[9] and D[10] pins must be connected together as shown in the application circuit sec-
tion of this document. To run from external FLASH memory the FLASH must be connected as shown in the application
circuit diagram and contain valid application code. If an external memory does not have valid program data, the device
enters a download mode in which a valid program may be loaded into the external memory through a sequence of com-
mands over the HCI transport layer.
Value (PIO 2)
Description
0
UART
1
USB
PIO 1
USB_DPLS_PULLUP
Reference Frequency Selection
1
Don't Care
Reference frequency per NVM system configu-
ration setting, or if NVM is not set, defaults to
32 MHz.
0
0
13 MHz
0
1
26 MHz
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SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
Pin Description
The following table provides detailed listings of pin descriptions arranged by functional groupings.
Name
Pad Type
Ball
Description
Radio (Power from VCC)
RF_IN
Analog
A2
RF signal input into the receiver.
RF_OUT
Analog
A4
RF signal output from the transmitter.
VTUNE
Analog
A6
Pin for reference PLL loop filter, only used if reference frequency is not
integer multiples of 4 MHz.
CHG_PUMP
Analog
F1
Pin for RF loop filter.
XTAL_N
Analog
A7
System clock crystal negative input. If a reference clock is used, this pin
should be left unconnected.
XTAL_P/CLK
Analog
B7
System clock crystal positive input or reference clock input.
IDAC
Analog
B1
Power control to external power amplifier. This output provides a variable
current source that can be used to control the external power amp. Leave
unconnected if not used.
VREFP_CAP
Analog
C1
Decoupling capacitor for internal A/D converter voltage reference.
VREFN_CAP
Analog
C2
Decoupling capacitor for internal A/D converter voltage reference.
Low Power Oscillator and Reset (Power from VDD_P)
CLK32K_IN
Analog
K10
For crystal or external clock input (32.768 kHz).
CLK32K_OUT
Analog
L11
Drive for crystal.
RESET_N
Analog
C6
System level reset (active low).
Power Control Interface (Power from VDD_P)
PWR_REG_EN/PIO[8]
CMOS bi-directional
G1
Enable for an external voltage regulator. Programmable active high or
active low. Also used as PIO[8], which is the default mode until the appro-
priate configuration bit is set. Tie to ground if not used.
TX_RX_SWITCH
CMOS output
J9
Output signal used to indicate the current state of the radio. This could be
used as a direction control for an external power amplifier.The polarity is
programmable with the default set as:
Low = Transmit mode
High = Receive mode
Table 3. SiW3000 Radio Processor Pin List
8 of 24
SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
Programmable I/O (Power from VDD_P)
PIO[0]
CMOS bi-directional
K5
Programmable input/output.
Needs to be low until internal reset goes high or tie to ground if not used.
PIO[1]
CMOS bi-directional
B8
Programmable input/output.
Sampled following reset for frequency selection:
If UART transport is selected and PIO[1] = 0, frequency is selected by the
state of USB_DPLS_PULLUP pin.
If UART transport is selected and PIO[1] = 1, frequency is selected by
NVM parameter. Default for proper UART operation will be configured as
32 MHz.
If USB transport is selected, PIO[1] is ignored and the frequency will be
configured as 32 MHz.
PIO[2]
CMOS bi-directional
J10
Programmable input/output.
Sampled following reset for transport selection:
PIO[2] = 0, selects UART transport
PIO[2] = 1, selects USB transport
PCM Interface (Power from VDD_P)
PCM_IN
CMOS output
E10
PCM data to the PCM CODEC.
PCM_OUT
CMOS input
F10
PCM data from the remote device. Normally an input.
PCM_CLK
CMOS bi-directional
G10
PCM synchronous data clock to the remote device.
Normally an output. Input for Motorola SSI slave mode.
PCM_SYNC
CMOS bi-directional
H10
PCM synchronization data strobe to the remote device. Normally an out-
put. Input for Motorola SSI slave mode.
UART Interface (Power from VDD_P)
UART_RXD
CMOS input
K7
UART receive data.
UART_TXD
CMOS output
K3
UART transmit data.
UART_CTS
CMOS input
K6
UART flow control clear to send.
UART_RTS
CMOS output
G9
UART flow control ready to send.
EXT_WAKE
CMOS input
F3
Wake up signal from host.
HOST_WAKEUP
CMOS output
G2
Wake up signal to host.
USB Interface (Power from VDD_USB)
USB_DPLS
Analog
K9
USB differential pair positive signal.
USB_DMNS
Analog
K8
USB differential pair negative signal.
USB_DPLS_ PULLUP
CMOS bi-directional
J8
Output signal for controlling the on/off of the pull-up of the USB_DPLS
line.
For UART transport, this pin is sampled following reset for frequency
selection if PIO[1] = 0:
USB_DPLS_ PULLUP = 0, selects 13 MHz
USB_DPLS_ PULLUP = 1, selects 26 MHz
Name
Pad Type
Ball
Description
Table 3. SiW3000 Radio Processor Pin List (Continued)
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SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
External Memory Interface (power from VDD_P)
A[18]
A[17]/EEPROM_SCL
A[16]/EEPROM_SDA
A[15]
A[14]
A[13]
A[12]
A[11]
A[10]
A[9]
A[8]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
CMOS output
L1
G3
H1
A8
H2
C9
H3
J1
K4
J7
L4
A11
L7
F9
E11
E9
D11
D9
Address lines.
Note: A[17] and A[16] can be used to support an optional external serial
EEPROM when using the internal ROM in place of the external Flash
memory.
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]/PIO[3]
D[7]/PIO[7]
D[6]/PIO[6]
D[5]/PIO[5]
D[4]/PIO[4]
D[3]
D[2]
D[1]
D[0]
CMOS bi-directional
with internal pull-down
B11
C10
C11
B10
G11
H11
H9
J2
J11
D10
L3
L2
J4
J3
K2
K1
Data lines.
Note: D[4] through D[8] can be used as programmable I/O when using
the internal ROM in place of the external Flash memory.
Note: Connect D[9] to D[10] to use internal ROM.
OE_N
CMOS output
A10
Output enable for external memory (active low).
WE_N/EEPROM_WP
CMOS output
K11
Write enable for external memory (active low).
Note: Can be used to support an optional external serial EEPROM when
using the internal ROM in place of external Flash memory.
FCS_N
CMOS output
B9
Chip select for external memory (active low).
Power and Ground
VBATT_ANA
Power
D3
Positive supply to internal analog voltage regulator.
VBATT_DIG
Power
L8
Positive supply to internal digital voltage regulator.
VCC_OUT
Power
D1
Regulated output from internal analog voltage regulator.
VDD_P
Power
F11
L5
Positive supply for digital input/output ports including peripheral interface,
external memory interface, and UART interface.
VDD_USB
Power
L10
Positive supply for USB Interface.
VDD_C
Power
A9
L6
Positive supply for digital circuitry or output of internal digital voltage.
VCC
Power
A1
B6
C4
C5
E1
E3
Positive supply for RF and analog circuitry.
VSS_P
GND
C7
J5
Ground connections for digital input/output ports including peripheral
interface, external memory interface, and UART Interface.
VSS_C
GND
C8
J6
Ground connections for internal digital circuitry.
VSS_USB
GND
L9
Ground connections for USB Interface.
Name
Pad Type
Ball
Description
Table 3. SiW3000 Radio Processor Pin List (Continued)
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SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
GND
GND
A3
A5
B2
B3
B4
B5
C3
D2
E2
F2
Ground connections for RF and analog circuitry.
Name
Pad Type
Ball
Description
Table 3. SiW3000 Radio Processor Pin List (Continued)
11 of 24
SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
System Specifications
Absolute Maximum Ratings
Recommended Operating Conditions
ESD Rating
Note: This device is a high performance RF integrated circuit with an ESD rating of 2,000 volts (HBM conditions per Mil-Std-883, Method
3015). Handling and assembly of this device should only be done using appropriate ESD controlled processes.
Electrical Characteristics
DC Specification
(T
OP
=+25 C, V
DD_P
=3.0 V)
AC Characteristics
(T
OP
= +25 C, V
DD_P
=3.0 V, C
LOAD
=15 pF)
Parameter
Description
Min
Max
Unit
V
CC
Analog circuit supply voltage
-0.3
3.63
V
V
DD_IO
I/O supply voltage
-0.3
3.63
V
V
BATT_ANA
Analog regulator supply voltage
-0.3
3.63
V
V
BATT_DIG
Digital regulator supply voltage
-0.3
3.63
V
T
ST
Storage temperature
-55
+125
C
RF
MAX
Maximum RF input level
+5
dBm
Absolute maximum ratings indicate limits beyond which the useful life of the device may be impaired or damage may occur.
Parameter
Description
Min
Max
Unit
T
OP
Operating temperature (industrial grade)
-40
+85
C
T
EOP
Extended operating temperature
-40
+105
C
V
BATT_ANA
Unregulated supply voltage into internal analog regulator
2.3
3.63
V
V
BATT_DIG
Unregulated supply voltage into internal digital regulator
2.3
3.63
V
V
CC
Regulated supply voltage directly into analog circuits
1.71
1.89
V
V
DD_C
Regulated supply voltage directly into digital circuits
1.62
2.16
V
V
DD_P
Digital interface I/O supply voltage
1.62
3.63
V
V
DD_USB
Regulated supply voltage for USB Interface to meet USB specification
requirements
3.1
3.63
V
Symbol
Description
Rating
ESD
ESD protection - all pins
2000 V
Symbol
Description
Min.
Typ.
Max.
Unit
V
IL
Input low voltage
GND-0.1
0.3
.
V
DD_P
V
V
IH
Input high voltage
0.7
.
V
DD_P
V
DD_P
V
V
OL
Output low voltage
GND
0.2
.
V
DD_P
V
V
OH
Output high voltage
0.8
.
V
DD_P
V
DD_P
V
I
OH
Output high current
1
mA
Output high current (ball J8)
4
mA
I
OL
Output low current
1
mA
Output low current (ball J8)
4
mA
I
ILI
Input leakage current
1
A
Symbol
Description
Max.
Unit
t
r
Rise time
30
ns
t
f
Fall time
24
ns
12 of 24
SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
Current Consumption
(T
OP
= +25 C, V
BATT
=3.0 V using internal regulators)
Digital Regulator Specification
(T
OP
= 25 C)
Radio Specification
RF Impedances
Operating Mode
Average
Unit
Standby
25
A
Parked slave, 1.28 sec. interval
160
A
Page/Inquiry scan, 1.28 sec. interval
1.5
mA
ACL connection, sniff mode, 100 ms interval
1.2
mA
ACL data transfer 720 kbps, DH5 continuous packets
60
mA
SCO connection, HV1 packets
60
mA
SCO connection, HV3 packets
32
mA
Parameter
Description
Min
Typ
Max
Unit
Output voltage
(I
OUT
= 10 mA)
1.62
1.85
2.16
V
Line regulation
(I
OUT
= 0 mA, V
BATT_DIG
= 2.3 V to 3.63 V)
8.0
mV
Load regulation
(I
OUT
= 3 mA to 80 mA)
9.0
mV
Dropout voltage
(I
OUT
= 10 mA)
250
mV
Output maximum
current
80
mA
Quiescent current
10
A
Ripple rejection
f
RIPPLE
= 400 Hz
40
dB
Parameter
Description
Min
Typ
Max
Unit
VCO Operating
Range
Frequency
2402
2480
MHz
PLL lock time
55
100
s
Parameter
a
a.The impedance values are for typical samples in 96-pin VFBGA package.
Description
Min
Typ
Max
Unit
RF impedance
TX on
769//1.1
/pF
TX off
26//2.4
/pF
RX on
142//1.8
/pF
RX off
45.7//0
/pF
13 of 24
SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
Receiver Specification
(V
BATT
= 3.3 V, V
CC
=int. analog reg. output, nominal Bluetooth test conditions)
Note:
Nominal and extreme Bluetooth test conditions as defined by the Bluetooth Test and Interoperability Working Group published
RF Test Specification 1.1.
Transmitter Specification
(V
BATT
= 3.3 V, V
CC
= int. analog reg. output, nom. Bluetooth test conditions)
Parameter
Description
Min
Typ
Max
Unit
Receiver sensitivity BER < 0.1%
-85
-80
dBm
Maximum
usable signal
BER < 0.1%
0
dBm
C/I co-channel
(0.1% BER)
Co-channel selectivity
8
11
dB
C/I 1 MHz
(0.1% BER)
Adjacent channel selectivity
-4
0
dB
C/I 2 MHz
(0.1% BER)
2nd adjacent channel selectivity
-38
-35
dB
C/I
3 MHz
(0.1% BER)
3rd adjacent channel selectivity
-43
-40
dB
Out-of-band
blocking
30 MHz - 2000 MHz
-10
dBm
2000 MHz - 2399 MHz
-27
dBm
2498 MHz - 3000 MHz
-27
dBm
3000 MHz - 12.75 GHz
-10
dBm
Intermodulation
Max interferer level to maintain 0.1% BER, interference
signals at 3 and 6 MHz offset.
-39
-36
dBm
Receiver spurious
emission
30 MHz to 1 GHz
-57
dBm
1 GHz to 12.75 GHz
-47
dBm
Parameter
Description
Min
Typ
Max
Units
Output RF transmit
power
At maximum power output level
-2
+2
+6
dBm
Modulation index
0.28
0.306
0.35
Initial carrier fre-
quency accuracy
-75
+75
kHz
Carrier frequency
drift
One slot packet
-25
+25
kHz
Two slot packet
-40
+40
kHz
Five slot packet
-40
+40
kHz
Max drift rate
400
Hz/s
20 dB occupied
bandwidth
Bluetooth specification
1000
kHz
In-band spurious
emission
2 MHz offset
-74
-55
dBm
>3 MHz offset
-74
-55
dBm
Out-of-band
spurious
emission
30 MHz to 1 GHz, operating mode
-70
-55
dBm
1 GHz to 12.75 GHz, operating mode
a
a.Except transmit harmonics.
-70
-50 dBm
1.8 GHz to 1.9 GHz
-62
dBm
5.15 GHz to 5.3 GHz
-47
dBm
14 of 24
SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
System Requirements
Analog Voltage Supply Requirements
The SiW3000 processor is designed for use with integrated low noise analog voltage regulators and is recommended for
all applications. If necessary, the internal analog regulator can be bypassed. In situations where bypassing the internal
analog regulator is required, the supply voltage to the analog circuit must satisfy the following requirements to preserve
the RF performance characteristics.
External Reference Requirements
It is possible to provide a number of reference frequencies that are typical on most cellular phones directly into ball B7
(XTAL_P/CLK) of the device. The following reference frequencies (in MHz) can be used:
3.84, 9.6, 12, 12.8, 13, 14.4, 15.36, 16, 16.8, 19.2, 19.68, 19.8, 26, 32, 38.4, and 48 MHz. For other frequencies,
please contact RFMD.
Reference Crystal Requirements
Many reference frequencies are supported by the device. If a crystal is used as the reference frequency source, the typ-
ical required parameters are listed below:
Parameter
Description
Min
Max
Unit
VCC
Analog supply voltage to all VCC input pins
1.71
1.89
V
Minimum
load current
External regulator current
80
mA
Minimum
ripple rejection
at 400Hz
40
dB
Output noise
Integrated 10 Hz to 80 kHz noise
22
mV RMS
Parameter
Description
Min
Max
Units
Phase noise
100 Hz offset
-100
dBc/Hz
1 kHz offset
-120
dBc/Hz
10 kHz offset
-140
dBc/Hz
Drive level
AC amplitude
0.5
V
CC
V
P-P
DC level
a
a.If DC-coupled, the external reference signal voltage must stay within this range at all times.
0.3
V
CC
V
Parameter
Description
Min
Typ
Max
Unit
Drive level
0.3
mW
ESR
Effective serial resistance
a
a.For 32-MHz crystal.
150
W
C
O
Holder capacitance
b
b.The actual values for C
O
and C
L
are dependent on the crystal manufacturer and can be compensated for by an internal crystal calibra-
tion capability.
3
5
pF
C
L
Load capacitance
b
12
18
pF
C
M
Motional capacitance
6
fF
15 of 24
SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
Application Circuit for External Flash-based Products
C1
8
0
.
1
u
F
L1 1
8nH
U1
A1
B1
C1
C2
D1
D3
E1
E3
F1
G1
G2
G3
H1
H2
J1
J2
K1
L1
K2
L2
J3
K3
L3
J4
K4
L4
H3
K5
L6
K6
F3
L7
J7
K7
L8
J8
L9
K8
K9
L10
J9
L1
1
K1
0
K11
H9
J1
0
J11
H11
H1
0
G1
0
G11
F11
F1
0
F9
E11
E1
0
G9
D11
E9
D10
C11
D9
C10
B11
A11
B10
C9
A10
L5
B9
A9
B8
A8
C6
A7
B7
B6
A6
C5
A4
C4
A2
J5
C7
A3
A5
B2
B3
B4
B5
C3
C8
D2
E2
F2
J6
VCC
ID
A
C
VREF
P
_
CAP
VREF
N_
CAP
VCC_OUT
VBAT
T_
ANA
VCC
VCC
CHG
_
P
UM
P
PWR
_
R
E
G
_
EN
/
P
IO
[8
]
HO
ST
_
W
AKEUP
A[1
7]/
EEPROM
_S
CL
A[1
6]/
EEPROM
_S
DA
A[1
4]
A[1
1]
D[8
]/PIO
[3]
D[0
]
A[1
8]
D[1
]
D[4
]/PIO
[4]
D[2
]
UART
_
T
XD
D[5
]/PIO
[5]
D[3
]
A[1
0]
A[8
]
A[1
2]
PI
O
[
0
]
VDD_C
UART
_
C
T
S
EXT
_
W
AKE
A[6
]
A[9
]
UART
_
R
XD
VBAT
T_
DIG
USB_
DP
L
S
_
P
UL
L
U
P
VSS_
USB
USB_
DM
NS
USB_
D
P
L
S
VDD_US
B
T
X
_
R
X_
SW
IT
CH
CL
K3
2
K
_
O
UT
C
L
K
3
2K
_I
N
WE
_N
/EEPRO
M_W
P
D[9
]
PI
O
[
2
]
D[7
]/PIO
[7]
D[1
0]
PCM
_
SYNC
PC
M_
C
L
K
D[1
1]
VDD_P
PCM
_
O
U
T
A[5
]
A[4
]
PCM
_
IN
UART
_
R
T
S
A[2
]
A[3
]
D[6
]/PIO
[6]
D[1
3]
A[1
]
D[1
4]
D[1
5]
A[7
]
D[1
2]
A[1
3]
OE_
N
VDD_P
FCS
_N
VDD_C
PI
O
[
1
]
A[1
5]
RESET
_
N
XTAL
_N
XTA
L_
P/C
LK
VCC
VT
UNE
VCC
RF
_
O
UT
VCC
RF
_
I
N
VSS_
P
VSS_
P
GND
GND
GND
GND
GND
GND
GND
VSS_
C
GND
GND
GND
VSS_
C
C1
9
0
.
1
u
F
C2 1u
F
Y1
XT
L
3
2
M
H
z
1
3
U2
2M
o
r
4M
FL
A
S
H
E1
D1
C1
A1
B1
D2
C2
A2
B5
A5
C5
D5
B6
A6
C6
D6
E6
B2
G1
A4
F1
A3
B3
C3
D3
B4
C4
D4
F6
E2
H2
E3
H3
H4
E4
H5
E5
F2
G2
F3
G3
F4
G5
F5
G6
G4
H1
H6
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
OE
WE
CE
RY/
BY#
NC
NC
NC
RESET
#
NC
NC
BYT
E#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VCC
GND
GND
C4 0.
1
u
F
VCC
VDD_
P
C
1
6
DNI
R2
, C16, and C17 are
not required for
32
MHz applications.
For component values
us
ing other frequenci
es, refer to the
re
ference design appl
ication note.
C2
1
0.
1u
F
C5 8.
2p
F
C1 1uF
C
1
5
1
80
pF
R3
10
0K
C2
0
0.
1
u
F
L4 4.
7
n
H
R1
47
K
VDD_
P
C1
0
1u
F
RF
_
I
N_
OUT
C6 8.
2
p
F
V
BAT
T
HOST INTERFACE
IN
OUT
FL1 S
h
o
s
in
Filte
r
HM
D
8
4
6
H
1
2
C7
8.
2
p
F
(
E
X
T
E
R
N
A
L
F
L
A
SH
CO
NF
IG
UR
AT
IO
N)
C1
4
2
2
p
F
L6
2.
7n
H
C1
2
2.
7
p
F
C1
1
2.
7
p
F
C8
18
pF
SiW3000
C9 18
pF
C1
3
1.
8p
F
L3 3.
9
n
H
VCC
L5 3.
3
n
H
L2 3.
3n
H
V
DD_
USB
VC
C
VCC is the outp
ut from the internal
voltage regulat
or.
C3
0.
1
u
F
C1
7
DNI
R2
DN
I
Note: Filter is no
t required to meet
BT and FCC specifi
cations but may be
added if better ou
t-of-band
performance is des
ired.
16 of 24
SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
Application Circuit for Internal ROM-based Products
VCC
C1
1
2.
7
p
F
C2
0
0.
1
u
F
C1 1u
F
C1
0
1uF
C3 0.
1u
F
L5 3.
3
n
H
R2
DNI
SiW3000
R2, C16, a
nd C17 are not re
quired for
32MHz appl
ications. For co
mponent values
using othe
r frequencies, re
fer to the
reference
design applicatio
n note.
C5 8.
2p
F
VDD_
P
VDD_
USB
U1
A1
B1
C1
C2
D1
D3
E1
E3
F1
G1
G2
G3
H1
H2
J1
J2
K1
L1
K2
L2
J3
K3
L3
J4
K4
L4
H3
K5
L6
K6
F3
L7
J7
K7
L8
J8
L9
K8
K9
L10
J9
L1
1
K1
0
K11
H9
J1
0
J11
H11
H1
0
G1
0
G11
F11
F1
0
F9
E11
E1
0
G9
D11
E9
D10
C11
D9
C10
B11
A11
B10
C9
A10
L5
B9
A9
B8
A8
C6
A7
B7
B6
A6
C5
A4
C4
A2
J5
C7
A3
A5
B2
B3
B4
B5
C3
C8
D2
E2
F2
J6
VCC
ID
A
C
VREF
P
_
CAP
VREF
N_
CAP
VCC_O
UT
VBAT
T_
ANA
VCC
VCC
CHG
_
PUM
P
P
W
R
_
R
E
G
_
E
N
/P
IO
[8
]
HO
ST
_
W
AKEUP
A[1
7]/
EEPRO
M_
SCL
A[1
6]/
EEPRO
M_
SDA
A[1
4]
A[1
1]
D[8
]/P
IO[3
]
D[0
]
A[1
8]
D[1
]
D[4
]/P
IO[4
]
D[2
]
UART
_
T
XD
D[5
]/P
IO[5
]
D[3
]
A[1
0]
A[8
]
A[1
2]
PI
O
[
0
]
VDD_C
UART
_
C
T
S
EXT
_
W
AKE
A[6
]
A[9
]
UART
_
R
XD
VBAT
T_
DIG
U
S
B
_
D
P
LS
_P
U
L
LU
P
VSS_
USB
USB_
DM
NS
USB_
DPL
S
VDD_US
B
T
X
_
R
X_
SW
IT
CH
CL
K3
2
K
_
O
UT
C
L
K
3
2K
_I
N
WE
_N
/EEPRO
M_W
P
D[9
]
PI
O
[
2
]
D[7
]/P
IO[7
]
D[1
0]
PCM
_
SYNC
PCM
_
CL
K
D[1
1]
VDD_P
PCM
_
O
U
T
A[5
]
A[4
]
PCM
_
IN
UART
_
R
T
S
A[2
]
A[3
]
D[6
]/P
IO[6
]
D[1
3]
A[1
]
D[1
4]
D[1
5]
A[7
]
D[1
2]
A[1
3]
OE_
N
VDD_P
FCS
_N
VDD_C
PI
O
[
1
]
A[1
5]
RESET
_
N
XTA
L_
N
XTAL
_P
/C
LK
VCC
VT
UNE
VCC
RF
_
O
UT
VCC
RF
_
I
N
VSS_
P
VSS_
P
GND
GND
GND
GND
GND
GND
GND
VSS_
C
GND
GND
GND
VSS_
C
VDD_
P
VCC
L1 18
nH
U2
EEPRO
M
1 2 3
4
5
6
7
8
A0 A1 A2
GND
SD
A
SCL
WP
VCC
C4 0.
1
u
F
VCC
C1
9
0
.
1
u
F
(
I
N
TER
NA
L RO
M CON
FI
GU
RA
TI
ON)
V
CC is the output
from the internal
v
oltage regulator.
VDD_
P
R1
47
K
RF
_
I
N_
OUT
Note: Filter is
not required to m
eet
BT and FCC speci
fications but may
be
added if better
out-of-band
performance is d
esired.
C8
18
pF
C6 8.
2
p
F
VDD_
P
HOST INTERFACE
L6
2.
7
n
H
C9 18
pF
L4 4.
7
n
H
C1
6
D
NI
C1
7
D
NI
IN
OUT
FL
1
S
h
o
s
in
F
ilte
r
H
M
D
8
46H
1
2
Connect D[9] t
o
D[10] to selec
t
internal ROM m
ode.
R4
10
K
C2 1u
F
L2 3.
3
n
H
C1
8
0
.
1
u
F
Y1
XT
L
3
2
M
H
z
1
3
C1
4
2
2
p
F
R3
100
K
L3 3.
9
n
H
VB
A
T
T
C1
3
1.
8
p
F
C
1
5
1
80
pF
C7
8.
2p
F
R5
10
K
C2
1
0.
1
u
F
C1
2
2.
7p
F
17 of 24
SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
I/O Configuration (Top View)
SiW3000
TOP VIEW
VCC
K2
K3
K4
K5
K6
K7
K8
K9
K1
K10
K11
A2
A3
A4
A5
A6
A7
A8
A9
B1
B3
B10
C1
C2
D1
D2
E1
E2
F1
F2
G1
G2
H1
H2
J1
J3
J4
J5
J6
J7
J8
J10
C9
C10
D9
D10
E9
E10
F9
F10
G9
G10
H9
H10
B2
B9
J2
J9
A1
A10
B11
J11
C11
D11
E11
F11
G11
H11
A11
C3
D3
E3
F3
G3
H3
L2
L3
L4
L5
L6
L7
L8
L9
L1
L10
L11
B4
B5
B6
B7
B8
C4
C5
C6
C7
C8
VCC
RF_IN
GND
RF_OUT
GND
VTUNE
XTAL_N
A[15]
VDD_C
OE_N
A[7]
IDAC
GND
GND
GND
GND
VCC
XTAL_P/CLK
PIO[1]
FCS_N
D[12]
D[15]
VREFP_CAP VREFN_CAP
GND
VCC
VCC
RESET_N
VSS_P
VSS_C
A[13]
D[14]
D[13]
PWR_REG_EN/
PIO[8]
HOST_
WAKEUP
A[17]/
EEPROM_SCL
UART_RTS
PCM_CLK
D[11]
A[16]/
EEPROM_SDA
A[14]
A[12]
D[9]
PCM_SYNC
D[10]
CHP_PUMP
GND
EXT_WAKE
A[5]
PCM_OUT
VDD_P
GND
VCC
A[3]
PCM_IN
A[4]
VCC_OUT
GND
VBATT_ANA
A[1]
D[6]/PIO[6]
A[2]
A
B
C
D
E
F
G
H
J
L
K
1
2
3
4
5
6
7
8
9
10
11
POWER
RF GROUND
A[18]
D[4]/PIO[4] D[5]/PIO[5]
A[8]
VDD_P
VDD_C
A[6]
VBATT_DIG
VSS_USB VDD_USB
CLK32K_OUT
A[11]
D[8]/PIO[3]
D[2]
D[3]
VSS_P
VSS_C
A[9]
USB_DPLS_
PULLUP
TX_RX_SWITCH
PIO[2]
D[7]/PIO[7]
D[0]
D[1]
UART_TXD
A[10]
PIO[0]
UART_CTS UART_RXD USB_DMNS USB_DPLS CLK32K_IN
WE_N/
EEPROM_WP
DIGITAL GROUND
18 of 24
SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
Packaging and Product Marking
Package Drawing
96-Pin, 6 mm x 6 mm, VFBGA Drawing and Dimensions
Symbol
Min
Max
Notes:
A
0.8
1.0
1. Dimension b is measured at the maximum solder ball diameter,
A1
0.2
0.3
parallel to datum plane Z.
A2
0.22 REF
2. Datum Z is defined by the spherical crowns of the
A3
0.45 REF
solder balls.
b
0.25
0.35
3. Parallelism measurement shall exclude any effect of
D
6 BSC
mark on top surface of package.
E
6 BSC
4. All dimensions are in millimeters.
e
0.5 BSC
D1
5 BSC
E1
5 BSC
19 of 24
SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
Package Drawing
96-Pin, 10 mm x 10 mm, LFBGA Drawing and Dimensions
Symbol
Min
Max
Notes:
A
-
1.4
1. Dimension b is measured at the maximum solder ball diameter,
A1
0.27
0.37
parallel to datum plane Z.
A2
0.26 REF
2. Datum Z is defined by the spherical crowns of the
A3
0.8 REF
solder balls.
b
0.35
0.45
3. Parallelism measurement shall exclude any effect of
D
10 BSC
mark on top surface of package.
E
10 BSC
4. All dimensions are in millimeters.
e
0.8 BSC
5. Dimensions and tolerances: ASME Y14.5M.
D1
8 BSC
6. Reference document: JEDEC-MO-210.
E1
8 BSC
20 of 24
SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
Product Marking
Tape and Reel Specification
Carrier Tape:
ADV ML0707-A
Reel Type:
Klik Reel (16 mm) 13" dia.
QTY/Reel
2500
Peel Test:
2080 grams
Cover Tape:
RS Standard (anti-static)
Leader:
500 mm (minimum 400 mm)
Trailer:
250 mm (minimum 160 mm)
Peel Speed:
300 mm/minute
Note: Drawing not to scale.
SiW3000AIP1
LLLLL
YYWW ARM
3000GIP1
LLLLL
YYWW ARM
SIW
Pin 1 Corner
4 Digit Date Code
Trace Code
6-by-6-mm VFBGA
10-by-10-mm LFBGA
21 of 24
SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
Tape Detail (6 mm x 6 mm VFBGA)
Note:
1. Tolerances 0.10 unless otherwise specified.
2. 10 sprocket hole pitch cumulative tolerance 0.2
3. Camber not to exceed 1mm in 100 mm.
4. Material: Black Advantek Polystyrene.
5. Ao and Bo measured on a plane 0.3 mm above the bottom of the pocket.
6. Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier.
7. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.
8. All dimensions in millimeters.
DIRECTION OF FEED
0.25
16 0.3
SECTION B-B
Ao= 6.30 mm
Bo= 6.30 mm
Ko= 1.50 mm
SECTION A-A
R0.30
(TYP.)
Ko
A
B
See Note 1
See Note 6
A
B
4.0
1.50
2.0
1.50
(MIN)
1.75
Bo
Ao
12.0
R0.25
+0.1
0.0
0.30 0.05
7.5
See Note 6
22 of 24
SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
Reel Dimensions: Klik Reel
Note:
All dimensions in millimeters (mm) unless otherwise stated.
Tape
Width
A
B(min)
C
D (min)
N (min)
W1
W2 (max)
W3 (min)
W3 (max)
16
330
1.50
13.00+0.5
20.20
100
16.4+2.0
-0.00
22.40
15.90
19.40
23 of 24
SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
Ordering Information
Part Number
Operational Temperature Range
1
Package
Ordering Quantity
SiW3000GIP1
Industrial
96-pin VFBGA
6-by-6-mm
429 pcs. per tray
SiW3000GIP1-T13
Industrial
96-pin VFBGA
6-by-6-mm
2500 on 13" reel
SiW3000GIG1
Industrial
96-pin VFBGA
6-by-6-mm Green
429 pcs. per tray
SiW3000GIG1-T13
Industrial
96-pin VFBGA
6-by-6-mm Green
2500 on 13" reel
SiW3000AIP1
Industrial
96-pin LFBGA
10-by-10-mm
360 pcs. per tray
SiW3000AIP1-T13
Industrial
96-pin LFBGA
10-by-10-mm
1500 on 13" reel
1
Industrial temperature range: -40C to +85C
24 of 24
SiW3000
60 0049 R01Drf SiW3000 Radio Processor DS
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. RF Micro
Devices reserves the right to make changes to its products without notice and advises customers to verify that
the information being used is current. The described products are not designed, manufactured or intended for
use in equipment for medical, life support, aircraft control or navigation, or any other applications that require
failsafe operation. RF Micro Devices does not assume responsibility for the use of the described products.
RF MICRO DEVICES, RFMD, Providing Communication SolutionsTM, the diamond logo design, Silicon Wave,
and the SiW product name prefix are trademarks of RFMD, LLC. BLUETOOTH is a trademark owned by
Bluetooth SIG, Inc., U.S.A. and licensed for use by RF Micro Devices, Inc. Manufactured under license from ARM
Limited. ARM, ARM7TDMI and the ARM logo are the registered trademarks of ARM Limited in the EU and other
countries. All other product, service, and company names are trademarks, registered trademarks or service
marks of their respective owners.
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