'03.09.25
12345
4-wire Serial Interface
Rx5C348A/B
OUTLINE
The Rx5C348A/B are CMOS real-time clock ICs connected to the CPU by four signal lines, CE, SCLK, SI, SO,
and configured to perform serial transmission of time and calendar data to the CPU. The periodic interrupt
circuit is configured to generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1
month. The 2 alarm interrupt circuits generate interrupt signals at preset times. As the oscillation circuit is
driven under constant voltage, fluctuation of the oscillator frequency due to supply voltage is small, and the time
keeping current is small (TYP. 0.35
A at 3V: Rx5C348A, TYP.0.55
A at 3V: Rx5C348B). The oscillation halt
sensing circuit can be used to judge the validity of internal data in such events as power-on; The supply voltage
monitoring circuit is configured to record a drop in supply voltage below two selectable supply voltage monitoring
threshold settings. The 32.768kHz clock output function (N-channel open drain output) is intended to output
sub-clock pulses for the external microcomputer. The 32-kHz clock circuit can be disabled by certain register
settings for the Rx5C348A but cannot be disabled by any register settings for the Rx5C348B. The oscillation
adjustment circuit is intended to adjust time counts with high precision by correcting deviations in the oscillation
frequency of the crystal oscillator. These models come in an ultra-compact SSOP10 (RS5C348A/B), SSOP10G
(RV5C348A/B), TSSOP10G (RT5C348B)
Package
32-kHz Clock Output
RS5C348A
Controllable by command
RS5C348B
SSOP10 (Pin Pitch 0.5mm, Height1.25mm,
6.4mm
3.5mm)
Keeping output enabled
RV5C348A
Controllable by command
RV5C348B
SSOP10G (Pin Pitch 0.5mm, Height1.2mm,
4.0mm
2.9mm)
Keeping output enabled
RT5C348B
TSSOP10G (Pin Pitch 0.5mm, Height0.85mm,
4.0mm
2.9mm)
Keeping output enabled
FEATURES
Timekeeping supply voltage ranging from 1.45 to 5.5V
Low power consumption
Rx5C348A: 0.35
A TYP (0.8
A MAX) at VDD=3V
Rx5C348B:
0.55
A TYP (1.0
A MAX)
at VDD=3V
Only four signal lines (CE, SCLK, SI, and SO) required for connection to the CPU.
Maximum clock frequency of 2 MHz (with VDD = 5V)
Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days,
and weeks) (in BCD format)
Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month)
to the CPU and provided with an interrupt flag and an interrupt halt
2 alarm interrupt circuits (Alarm_W for week, hour, and minute alarm settings and Alarm_D for hour and
minute alarm settings)
32-kHz clock output circuit (Nch. open drain output)
The Rx5C348A is designed to disable 32-kHz clock output in response to a command from the host computer
and the Rx5C348B is designed to keep 32-kHz output enabled.
Oscillation halt sensing circuit which can be used to judge the validity of internal data
Supply voltage monitoring circuit with two supply voltage monitoring threshold settings
Automatic identification of leap years up to the year 2099
Selectable 12-hour and 24-hour mode settings
Built-in oscillation stabilization capacitors (CG and CD)
High precision oscillation adjustment circuit
Ultra-compact SSOP10 (RS5C348A/B), SSOP10G (RV5C348A/B), TSSOP10G (RT5C348B)
CMOS process
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Rev.2.01 - 1 -
Rx5C348A/B
PIN CONFIGURATION
SCLK
SO
/INTR
VSS
VDD
OSCIN
CE
1
2
3
4
5
6
7
9
TOP VIEW
Rx5C348A/B
32KOUT
10
8
SI
OSCOUT
BLOCK DIAGRAM
32kHz
OUTPUT
CONTROL
OSC
COMPARATOR_D
ALARM_D REGISTER
(MIN,HOUR)
ADDRESS
DECODER
ADDRESS
REGISTER
VOLTAGE
DETECT
DIV
TIME COUNTER
(SEC,MIN,HOUR,WEEK,DAY,MONTH,YEAR)
SHIFT REGISTER
I/O
CONTROL
32KOUT
INTERRUPT CONTROL
SCLK
DIVIDER
CORREC
-TION
VDD
VSS
COMPARATOR_W
ALARM_W REGISTER
(MIN,HOUR, WEEK)
CE
OSC
DETECT
SI
/INTR
SO
OSCIN
OSCOUT
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Rev.2.01 - 2 -
Rx5C348A/B
PIN DESCRIPTION
Symbol Item
Description
CE
Chip enable
Input
The CE pin is used for interfacing with the CPU. Should be held high to
allow access to the CPU. Incorporates a pull-down resistor. Should be
held low or open when the CPU is powered off. Allows a maximum input
voltage of 5.5v regardless of supply voltage.
SCLK
Serial Clock
Input
The SCLK pin is used to input clock pulses synchronizing the input and
output of data to and from the SI and SO pins. Allows a maximum input
voltage of 5.5v regardless of supply voltage.
SI
Serial Input
The SI pin is used to input data intended for writing in synchronization with
the SCLK pin. CMOS input. Allows a maximum input voltage of 5.5v
regardless of supply voltage.
SO
Serial Output
The SO pin is used to output data intended for reading in synchronization
with the SCLK pin. CMOS output.
/INTR Interrupt
Output
The /INTR pin is used to output alarm interrupt (Alarm_W) and alarm
interrupt (Alarm_D) and output periodic interrupt signals to the CPU signals.
Disabled at power-on from 0V. N-channel open drain output. Allows a
maximum pull-up voltage of 5.5v regardless of supply voltage.
32KOUT 32kHz
Clock
Output
The 32KOUT pin is used to output 32.768-kHz clock pulses. Enabled at
power-on from 0 volts. Nch. open drain output. The Rx5C348A is designed
to disable 32-kHz clock output in response to a command from the host
computer and the Rx5C348B is designed to keep 32-kHz output enabled.
OSCIN
OSCOUT
Oscillation
Circuit
Input / Output
The OSCIN and OSCOUT pins are used to connect the 32.768-kHz crystal
oscillator (with all other oscillation circuit components built into the
Rx5C348A/B).
VDD
VSS
Positive/Negative
Power
Supply Input
The VDD pin is connected to the power supply. The VSS pin is grounded.
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Rev.2.01 - 3 -
Rx5C348A/B
ABSOLUTE MAXIMUM RATINGS
(VSS=0V)
Symbol Item
Pin
Name
Description
Unit
VDD
Supply Voltage 2
VDD
-0.3 to +6.5
V
VI
Input Voltage
CE, SCLK, SI
-0.3 to +6.5
V
Output Voltage 1
SO
-0.3 to VDD + 0.3
V
VO
Output Voltage 2
/INTR, 32KOUT
-0.3 to +6.5
V
PD Power
Dissipation Topt = 25
C
300 mW
Topt
Operating Temperature
-40 to +85
C
Tstg
Storage Temperature
-55 to +125
C
RECOMMENDED OPERATING CONDITIONS
(VSS=0V,
Topt=-40
to
+85
C)
Symbol Item
Pin
Name
Min.
Typ. Max. Unit
Vaccess Supply
Voltage
Power
supply
voltage
for interfacing
with CPU
2.0 5.5
V
VCLK
Time keeping Voltage
1.45
5.50
V
fXT Oscillation
Frequency
32.768
kHz
VPUP
Pull-up Voltage
/INTR, 32KOUT
5.5
V
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Rev.2.01 - 4 -
Rx5C348A/B
DC ELECTRICAL CHARACTERISTICS
(Unless otherwise specified:
VSS=0V, VDD=3.0V, Topt=-40 to +85
C, Crystal oscillator 32768Hz,CL=7pF,R1=30k
)
Symbol Item
Pin
Name
Conditions
Min. Typ. Max. Unit
VIH
"H" Input Voltage
0.8x
VDD
5.5
VIL
"L" Input Voltage
CE, SCLK, SI
VDD=2.0 to 5.5V
-0.3
0.2x
VDD
V
IOH "H"
Output
Current
SO
VOH=VDD-0.5V
-0.5
mA
IOL1 /INTR,
32KOUT(Rx5C348A
)
2.0
IOL2
"L" Output
Current
SO,
32KOUT(Rx5C348B
)
VOL=0.4V
0.5
mA
IIL Input
Leakage
Current
SI, SCLK
VI=5.5V or VSS
VDD=5.5V
-1.0
1.0
A
RDNCE Pull-down
Resistance CE
40 120 400 k
IOZ1
SO
VO=5.5V or VSS
VDD=5.5V
-1 1
IOZ2
Output Off-state
Current
/INTR, 32KOUT
VO=5.5V
VDD=5.5V
-1 1
A
IDD
(Rx5C34
8A)
VDD VDD=3V,
CE= OPEN
Output = OPEN
32KOUT=OFF
*1)
0.35
0.80
IDD
(Rx5C34
8B)
Time Keeping Current
VDD VDD=3V,
CE= OPEN
Output = OPEN
32KOUT=ON
0.55
1.00
A
VDETH Supply
Voltage
Monitoring Voltage "H"
VDD
Topt=-30 to +70
C
1.90 2.10 2.30
VDETL Supply
Voltage
Monitoring Voltage "L"
VDD
Topt=-30 to +70
C
1.45 1.60 1.80
V
CG Internal
Oscillation
Capacitance 1
OSCIN
12
CD Internal
Oscillation
Capacitance 2
OSCOUT
12
pF
*1) For time keeping current when outputting 32.768kHz from the 32KOUT pin, see "P.40. Typical
Characteristics".
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Rev.2.01 - 5 -
Rx5C348A/B
AC ELECTRICAL CHARACTERISTICS
Unless otherwise specified: VSS=0V,Topt=-40 to +85
C
Input and Output Conditions: VIH=0.8
VDD,VIL=0.2
VDD,VOH=0.8
VDD,VOL=0.2
VDD,CL=50pF
VDD
2.0V VDD
4.5V
Symbol Item
Condi-
tions
Min. Typ.
Max. Min. Typ.
Max.
Unit
t
CES
CE
Set-up
Time
400
200
ns
t
CEH
CE
Hold
Time
400
200
ns
t
CR
CE
Recovery
Time
62 62
s
f
SCLK
SCLK
Clock
Frequency
1.0
2.0
M
Hz
t
CKH
SCLK Clock High
Time
400
200
ns
t
CKL
SCLK Clock Low
Time
400
200
ns
t
CKS
SCLK
Set-up
Time
200
100
ns
t
RD
Data Output Delay
Time
300
150
ns
t
RZ
Data Output Floating
Time
300
150
ns
t
CEZ
Data Output Delay
Time After Falling of
CE
300
150
ns
t
DS
Input
Data
Set-up Time
200
100
ns
t
DH
Input
Data
Hold Time
200
100
ns
SCLK
t
CES
SI
CE
t
RD
t
CKL
t
CEZ
t
DS
t
DH
t
RD
t
CEH
t
CKH
t
CKS
t
CR
t
RZ
SO
*) For reading/writing timing, see "P.28. Adjustment of Oscillation frequency".
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Rev.2.01 - 6 -
Rx5C348A/B
PACKAGE DIMENSIONS
RS5C348A/B (SSOP10)
10 6
1
M
5
4.
4
0.2
6.
4
0.2
0.
5
0.2
0.9MAX
0.5
0
to 10
1.35
M
A
X
0.1
0.
1
0.1
0.1
0.2
0.1
0.15
+0.1
-0.05
3.5
0.2
1.15
0.1
unit: mm
RV5C348A/B (SSOP10G)
M
2.8
0.
2
0
to 10
2.9
-0.1
5
10
1
+0.3
0.15
0.127
-0.05
4.0
0.
3
0.1
0.2
0.1
+0.1
0.5
1.
1
0.
1
0.1
-
00
5
+0
1
6
0.55
0.2
unit: mm
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Rev.2.01 - 7 -
Rx5C348A/B
RT5C348B (TSSOP10G)
M
2.80
0.2
0
to 10
2.9
0.2
5
10
1
0.15
0.13
-0.05
4.0
0.
2
0.1
0.2
0.1
+0.1
0.5
(0.75)
0.1
-
00
5
+0
1
6
0.55
0.2
0.85
0.1
5
unit: mm
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Rev.2.01 - 8 -
Rx5C348A/B
GENERAL DESCRIPTION
Interface with CPU
The Rx5C348A/B is connected to the CPU by four signal lines CE (Chip Enable), SCLK (Serial Clock), SI (Serial
Input), and SO (Serial Output), through which it reads and writes data from and to the CPU. The CPU can be
accessed when the CE pin is held high. Access clock pulses have a maximum frequency of 1 MHz allowing
high-speed data transfer to the CPU.
Clock and Calendar Function
The Rx5C348A/B reads and writes time data from and to the CPU in units ranging from seconds to the last two
digits of the calendar year. The calendar year will automatically be identified as a leap year when its last two
digits are a multiple of 4. Consequently, leap years up to the year 2099 can automatically be identified as such.
*) The year 2000 is a leap year while the year 2100 is not a leap year.
Alarm Function
The Rx5C348A/B incorporates the alarm interrupt circuit configured to generate interrupt signals to the CPU at
preset times. The alarm interrupt circuit allows two types of alarm settings specified by the Alarm_W registers
and the Alarm_D registers. The Alarm_W registers allow week, hour, and minute alarm settings including
combinations of multiple day-of-week settings such as "Monday, Wednesday, and Friday" and "Saturday and
Sunday". The Alarm_D registers allow hour and minute alarm settings. The Alarm_W outputs from /INTR pin, and
the Alarm_D outputs also from /INTR pin. Each alarm function can be checked from the CPU by using a polling
function.
High-precision Oscillation Adjustment Function
The Rx5C348A/B has built-in oscillation stabilization capacitors (CG and CD), which can be connected to an
external crystal oscillator to configure an oscillation circuit. To correct deviations in the oscillator frequency of
the crystal, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss (up to
1.5ppm at 25
C) from the CPU. The maximum range is approximately
189ppm in increments of approximately
3ppm. Such oscillation frequency adjustment in each system has the following advantages:
* Allows timekeeping with much higher precision than conventional RTCs while using a crystal oscillator
with a wide range of precision variations.
* Corrects seasonal frequency deviations through seasonal oscillation adjustment.
* Allows timekeeping with higher precision particularly with a temperature sensing function out of RTC,
through oscillation adjustment in tune with temperature fluctuations.
Power-on Reset, Oscillation Halt Sensing Function and Supply Voltage Monitoring Function
The Rx5C348A/B incorporates an oscillation halt sensing circuit equipped with internal registers configured to
record any past oscillation halt.
Power on reset function reset the control resisters when the system is powered on from 0V. At the same time, the
fact is memorized to the resister as a flag, thereby identifying whether they are powered on from 0V or battery
backed-up.
The Rx5C348A/B also incorporates a supply voltage monitoring circuit equipped with internal registers
configured to record any drop in supply voltage below a certain threshold value. Supply voltage-monitoring
threshold settings can be selected between 2.1V and 1.6V through internal register settings. The sampling rate is
normally 1s.
The oscillation halt sensing circuit and the power-on reset flag are configured to confirm the established
invalidation of time data in contrast to the supply voltage monitoring circuit intended to confirm the potential
invalidation of time data. Further, the supply voltage monitoring circuit can be applied to battery supply voltage
monitoring.
Periodic Interrupt Function
The Rx5C348A/B incorporates the periodic interrupt circuit configured to generate periodic interrupt signals
aside from interrupt signals generated by the alarm interrupt circuit for output from the /INTR pin. Periodic
interrupt signals have five selectable frequency settings of 2 Hz (once per 0.5 seconds), 1 Hz (once per 1
second), 1/60 Hz (once per 1 minute), 1/3600 Hz (once per 1 hour), and monthly (the first day of every month).
Further, periodic interrupt signals also have two selectable waveforms, a normal pulse form (with a frequency of
2 Hz or 1 Hz) and special form adapted to interruption from the CPU in the level mode (with second, minute, hour,
and month interrupts). The condition of periodic interrupt signals can be monitored with using a polling function.
32kHz Clock Output
The Rx5C348A/B incorporates a 32-kHz clock circuit configured to generate clock pulses with the oscillation
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Rev.2.01 - 9 -
Rx5C348A/B
frequency of a 32.768kHz crystal oscillator for output from the 32KOUT pin. The 32-kHz clock output can be
disabled by certain register settings but cannot be disabled without manipulation of any two registers with
different addresses to prevent disabling in such events as the runaway of the CPU. The pin is N-channel open
drain output.
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Rev.2.01 - 10 -
Rx5C348A/B
Address Mapping
Address
Register Name
D a t a
A3A2A1A0
D7 D6 D5 D4 D3 D2
D1 D0
0 0
0
0
0 Second
Counter
-
*2)
S40 S20 S10 S8 S4 S2 S1
1 0
0
0
1 Minute
Counter
-
M40 M20 M10 M8 M4 M2 M1
2 0
0
1
0
Hour
Counter - - H20
P
/A
H10 H8 H4 H2 H1
3 0
0
1
1
Day-of-week
Counter
- - - - - W4
W2
W1
4 0
1
0
0 Day-of-month
Counter
- - D20
D10
D8
D4
D2
D1
5 0
1
0
1
Month Counter and
Century Bit
/19
20
-
-
MO10
MO8 MO4
MO2 MO1
6 0
1
1
0 Year
Counter
Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1
7 0
1
1
1 Oscillation
Adjustment
Register *3)
(0)
*4)
F6 F5 F4 F3 F2
F1 F0
8 1
0
0
0 Alarm_W
(Minute Register)
- WM40
WM20
WM10
WM8
WM4
WM2
WM1
9 1
0
0
1 Alarm_W
(Hour Register)
- -
WH20
WP
/ A
WH10
WH8 WH4
WH2 WH1
A 1
0
1
0 Alarm_W
(Day-of-week
Register)
-
WW6 WW5 WW4 WW3
WW2
WW1 WW0
B 1
0
1
1 Alarm_D
(Minute Register)
-
DM40
DM20 DM10
DM8 DM4
DM2 DM1
C 1
1
0
0 Alarm_D
(Hour Register)
- - DH20
DP
/A
DH10
DH8 DH4
DH2 DH1
D 1
1
0
1
- - - - - -
- -
E 1
1
1
0 Control Register 1
*3)
WALE
DALE
/12
24 /CLEN2
*5)
TEST CT2 CT1 CT0
F 1
1
1
1 Control Register 2
*3)
VDSL
VDET
SCRA
TCH1
XSTP /CLEN1
*5)
CTFG WAFG DAFG
Notes:
* 1) All the data listed above accept both reading and writing.
* 2) The data marked with "-" is invalid for writing and reset to 0 for reading.
* 3) When the XSTP bit is set to 1 in Control Register 2, all the bits are reset to 0 in Oscillation Adjustment
Register, Control Register 1 and Control Register 2 excluding the XSTP bit.
* 4) Writing to the Oscillation Adjustment Register requires filling the (0) bit.
* 5) These bit names apply to the Rx5C348A. For the Rx5C348B the bit names are SCRATCH2 and
SCRATCH3.
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Rev.2.01 - 11 -
Rx5C348A/B
Register Settings
Control Register 1 (ADDRESS Eh)
D7 D6 D5 D4 D3 D2 D1 D0
WALE DALE /12
24
/CLEN2
*2)
TEST
CT2 CT1 CT0 (For
Writing)
WALE DALE /12
24
/CLEN2
*2)
TEST
CT2 CT1 CT0 (For
Reading)
0 0 0 0 0 0 0 0 Default
Settings
*1)
*1) Default settings: Default value means read / written values when the XSTP bit is set to "1" due to
VDD
power-on from 0v or oscillation stopping
*2) This bit name applies to the Rx5C348A only. For the Rx5C348B the bit name is SCRATCH3..
(1) WALE, DALE Alarm_W Enable Bit, Alarm_D Enable Bit
WALE,DALE Description
0
Disabling the alarm interrupt circuit (under the control of the settings
of the Alarm_W registers and the Alarm_D registers).
(Default)
1
Enabling the alarm interrupt circuit (under the control of the settings
of the Alarm_W registers and the Alarm_D registers)
(2) /12
24
/12-24-hour Mode Selection Bit
/12
24
Description
0
Selecting the 12-hour mode with a.m. and p.m. indications.
(Default)
1
Selecting the 24-hour mode
Setting the /12
24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively.
24-hour mode
12-hour mode
24-hour mode
12-hour mode
00
12 (AM12)
12
32 (PM12)
01
01 (AM 1)
13
21 (PM 1)
02
02 (AM 2)
14
22 (PM 2)
03
03 (AM 3)
15
23 (PM 3)
04
04 (AM 4)
16
24 (PM 4)
05
05 (AM 5)
17
25 (PM 5)
06
06 (AM 6)
18
26 (PM 6)
07
07 (AM 7)
19
27 (PM 7)
08
08 (AM 8)
20
28 (PM 8)
09
09 (AM 9)
21
29 (PM 9)
10
10 (AM10)
22
30 (PM10)
11
11 (AM11)
23
31 (PM11)
Setting the /12
24 bit should precede writing time data
(3) /CLEN2 (Rx5C348A)
32kHz Clock Output Bit 2
/CLEN2 Description
0
Enabling the 32-kHz clock circuit
(Default)
1
Disabling the 32-kHz clock circuit
Setting the /CLEN2 bit or the /CLEN1 bit (D3 in the control register 2) to 0, specifies generating clock pulses
with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin.
Conversely, setting both the /CLEN1 and /CLEN2 bit to 1 disabling ("H") such output.
SCRATCH3 (Rx5C348B)
Scratch Bit 3
SCRATCH3 Description
0
(Default)
1
For the Rx5C348B, this bit is intended for scratching and accepts the reading and writing of 0 and 1. The
SCRATCH3 bit will be set to 0 when the XSTP bit is set to 1 in Control Register 2.
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Rev.2.01 - 12 -
Rx5C348A/B
(4) TEST
Test Bit
TEST Description
0
Normal operation mode.
(Default)
1 Test
mode.
The TEST bit is used only for testing in the factory and should normally be set to 0.
(5) CT2, CT1, and CT0
Periodic Interrupt Selection Bits
Description
CT2 CT1 CT0
Wave form
mode
Interrupt Cycle and Falling Timing
0 0 0 -
OFF(H)
(Default)
0 0 1 -
Fixed
at
"L"
0 1 0 Pulse
Mode
*1)
2Hz (Duty50%)
0 1 1 Pulse
Mode
*1)
1Hz (Duty50%)
1 0 0 Level
Mode
*2)
Once per 1 second (Synchronized with
second counter increment)
1 0 1 Level
Mode
*2)
Once per 1 minute (at 00 seconds of
every minute)
1 1 0 Level
Mode
*2)
Once per hour (at 00 minutes and 00
seconds of every hour)
1 1 1 Level
Mode
*2)
Once per month (at 00 hours, 00
minutes,
and 00 seconds of first day of every
month)
* 1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the
second counter as illustrated in the timing chart below.
/INTR Pin
Rewriting of the second counter
CTFG Bit
Approx. 92
s
(Increment of second counter)
In the pulse mode, the increment of the second counter is delayed by approximately 92
s from the
falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock
pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second.
Rewriting the second counter will reset the other time counters of less than 1 second, driving the
/INTR pin low.
* 2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1
minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling
edge of periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle
setting of 1 second are output in synchronization with the increment of the second counter as
illustrated in the timing chart below.
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Rev.2.01 - 13 -
Rx5C348A/B
Setting CTFG bit to 0
CTFG Bit
/INTR Pin
(Increment of
second counter)
(Increment of
second counter)
(Increment of
second counter)
Setting CTFG bit to 0
*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. or
60sec. as follows:
Pulse Mode: The "L" period of output pulses will increment or decrement by a maximum of
3.784 ms. For
example, 1-Hz clock pulses will have a duty cycle of 50
0.3784%.
Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of
3.784 ms.
Control Register 2 (Address Fh)
D7 D6 D5 D4 D3 D2 D1 D0
VDSL VDET SCRA
TCH1
XSTP /CLEN1 CTFG WAFG DAFG (For
Writing)
VDSL VDET SCRA
TCH1
XSTP /CLEN1 CTFG WAFG DAFG (For
Reading)
0 0 0
1 0 0 0 0 Default
Settings
*)
*) Default settings: Default value means read / written values when the XSTP bit is set to "1" due to VDD
power-on from 0v or oscillation stopping
(1) VDSL
VDD Supply Voltage Monitoring Threshold Selection Bit
VDSL Description
0
Selecting the VDD supply voltage monitoring threshold setting of
2.1v.
(Default)
1
Selecting the VDD supply voltage monitoring threshold setting of
1.6v.
The VDSL bit is intended to select the VDD supply voltage monitoring threshold settings.
(2) VDET
Supply Voltage Monitoring Result Indication Bit
VDET Description
0
Indicating supply voltage above the supply voltage monitoring
threshold settings.
(Default)
1
Indicating supply voltage below the supply voltage monitoring
threshold settings.
Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will
hold the setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage
monitoring circuit. Conversely, setting the VDET bit to 1 causes no event.
(3) SCRATCH1
Scratch Bit 1
SCRATCH1 Description
0
(Default)
1
This bit is intended for scratching and accepts the reading and writing of 0 and 1. The SCRATCH1 bit will
be set to 0 when the XSTP bit is set to 1 in Control Register 2.
(4) XSTP
Oscillation Halt Sensing Bit
XSTP Description
0
Sensing a normal condition of oscillation
1
Sensing a halt of oscillation
(Default)
The XSTP bit is for sensing a halt in the oscillation of the crystal oscillator. Oscillation Halt sensing circuit
operates only when CE pin is Low.
* The XSTP bit will be set to 1 once a halt in the oscillation of the crystal oscillator is caused by such events
as power-on from 0 volts and a drop in supply voltage. The XSTP bit will hold the setting of 1 even after the
12345
Rev.2.01 - 14 -
Rx5C348A/B
restart of oscillation. As such, the XSTP bit can be applied to judge the validity of clock and calendar data
after power-on or a drop in supply voltage.
* When the XSTP bit is set to 1, all bits will be reset to 0 in the Oscillation Adjustment Register, Control
Register 1, and Control Register 2, stopping the output from /INTR pin and starting the output of 32.768-kHz
clock pulses from the 32KOUT pin.
* The XSTP bit accepts only the writing of 0, which restarts the oscillation halt sensing circuit. Conversely,
setting the XSTP bit to 1 causes no event.
* It is recommendable to frequently check the XSTP bit for setting errors or data garbles, which may
seriously affect the operation of the Rx5C348A/B.
12345
Rev.2.01 - 15 -
Rx5C348A/B
(5) /CLEN1
32kHz Clock Output Bit 1 (Rx5C348A)
/CLEN1 Description
0
Enabling the 32-kHz clock circuit
(Default)
1
Disabling the 32-kHz clock circuit
Setting the /CLEN1 bit or the /CLEN2 bit (D4 in the control register 1) to 0, specifies generating clock pulses
with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin.
Conversely, setting both the /CLEN1 and /CLEN2 bit to 1 disabling ("H") such output.
SCRATCH2 (Rx5C348B)
Scratch Bit 2
SCRATCH2 Description
0
(Default)
1
For the Rx5C348B, this bit is intended for scratching and accepts the reading and writing of 0 and 1. The
SCRATCH3 bit will be set to 0 when the XSTP bit is set to 1 in Control Register 2.
(6) CTFG
Periodic Interrupt Flag Bit
CTFG Description
0
Periodic interrupt output = "H"
(Default)
1
Periodic interrupt output = "L"
The CTFG bit is set to 1 when the periodic interrupt signals are output from the /INTR pin ("L"). The CTFG
bit accepts only the writing of 0 in the level mode, which disables ("H") the /INTR pin until it is enabled ("L")
again in the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event.
(7) WAFG,DAFG
Alarm_W Flag Bit and Alarm_D Flag Bit
WAFG,DAFG Description
0
Indicating a mismatch between current time and preset alarm time
(Default)
1
Indicating a match between current time and preset alarm time
The WAFG and DAFG bits are valid only when the WALE and DALE have the setting of 1, which is caused
approximately 61
s after any match between current time and preset alarm time specified by the Alarm_W
registers and the Alarm_D registers. The WAFG (DAFG) bit accepts only the writing of 0. /INTR pin
outputs off ("H") when this bit is set to 0. And /INTR pin outputs "L" again at the next preset alarm time.
Conversely, setting the WAFG and DAFG bits to 1 causes no event. The WAFG and DAFG bits will have
the reading of 0 when the alarm interrupt circuit is disabled with the WALE and DALE bits set to 0. The
settings of the WAFG and DAFG bits are synchronized with the output of the /INTR pin as shown in the
timing chart below.
/INTR Pin
Writing of 0 to
WAFG(DAFG) bit
WAFG(DAFG) Bit
(Match between
current time and
preset alarm time)
Approx. 61
s
Approx. 61
s
Writing of 0 to
WAFG(DAFG) bit
(Match between
current time and
preset alarm time)
(Match between
current time and
preset alarm time)
12345
Rev.2.01 - 16 -
Rx5C348A/B
Time Counter (Address 0-2h)
Second Counter (Address 0h)
D7 D6 D5 D4 D3 D2 D1 D0
- S40 S20 S10 S8 S4 S2 S1 (For
Writing)
0 S40 S20 S10 S8 S4 S2 S1 (For
Reading)
0
Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite
Default Settings *)
Minute Counter (Address 1h)
D7 D6 D5 D4 D3 D2 D1 D0
- M40 M20 M10 M8 M4 M2 M1 (For
Writing)
0 M40 M20 M10 M8 M4 M2 M1 (For
Reading)
0
Indefinite Indefinite Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Default Settings *)
Hour Counter (Address 2h)
D7 D6 D5 D4 D3 D2 D1 D0
- - P
/A
or H20
H10 H8 H4 H2 H1 (For
Writing)
0 0 P
/A
or H20
H10 H8 H4 H2 H1 (For
Reading)
0 0
Indefinite Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Default Settings *)
*) Default settings: Default value means read / written values when the XSTP bit is set to "1" due to VDD
power-on from 0v or oscillation stopping
*
Time digit display (BCD format) as follows:
The second digits range from 00 to 59 and are carried to the minute digit in transition from 59 to 00.
The minute digits range from 00 to 59 and are carried to the hour digits in transition from 59 to 00.
The hour digits range as shown in "P12 Control Register 1 (ADDRESS Eh) (2) /12
24: /12-24-hour
Mode Selection Bit" and are carried to the day-of-month and day-of-week digits in transition from
PM11 to AM12 or from 23 to 00.
*
Any writing to the second counter resets divider units of less than 1 second.
*
Any carry from lower digits with the writing of non-existent time may cause the time counters to
malfunction. Therefore, such incorrect writing should be replaced with the writing of existent time
data.
Day-of-week Counter (Address 3h)
D7 D6 D5 D4 D3 D2 D1 D0
- - - - - W4
W2
W1
(For
Writing)
0 0 0 0 0 W4
W2
W1
(For
Reading)
0 0 0 0 0
Indefinite
Indefinite
Indefinite
Default Settings *)
*) Default settings: Default value means read / written values when the XSTP bit is set to "1" due to VDD
power-on from 0v or oscillation stopping
*
The day-of-week counter is incremented by 1 when the day-of-week digits are carried to the
day-of-month digits.
*
Day-of-week display (incremented in septimal notation):
(W4, W2, W1) = (0, 0, 0)
(0, 0, 1)
...
(1, 1, 0)
(0, 0, 0)
*
Correspondences between days of the week and the day-of-week digits are user-definable
(e.g. Sunday = 0, 0, 0)
*
The writing of (1, 1, 1) to (W4, W2, W1) is prohibited except when days of the week are unused.
12345
Rev.2.01 - 17 -
Rx5C348A/B
Calendar Counter (Address 4-6h)
Day-of-month Counter (Address 4h)
D7 D6 D5 D4 D3 D2 D1 D0
- - D20 D10 D8 D4 D2 D1 (For
Writing)
0 0 D20 D10 D8 D4 D2 D1 (For
Reading)
0 0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Default Settings *)
Month Counter + Century Bit (Address 5h)
D7 D6 D5 D4 D3 D2 D1 D0
/19
20
-
-
MO10 MO8 MO4 MO2 MO1 (For
Writing)
/19
20
0
0
MO10 MO8 MO4 MO2 MO1 (For
Reading)
Indefinite
0 0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Default Settings *)
Year Counter (Address 6h)
D7 D6 D5 D4 D3 D2 D1 D0
Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 (For
Writing)
Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 (For
Reading)
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Default Settings *)
*) Default settings: Default value means read / written values when the XSTP bit is set to "1" due to VDD
power-on from 0v or oscillation stopping
*
The calendar counters are configured to display the calendar digits in BCD format by using the
automatic calendar function as follows:
The day-of-month digits (D20 to D1) range from 1 to 31 for January, March, May, July, August,
October, and December; from 1 to 30 for April, June, September, and November; from 1 to 29 for
February in leap years; from 1 to 28 for February in ordinary years. The day-of-month digits are
carried to the month digits in reversion from the last day of the month to 1. The month digits (MO10
to MO1) range from 1 to 12 and are carried to the year digits in reversion from 12 to 1.
The year digits (Y80 to Y1) range from 00 to 99 (00, 04, 08,
...
, 92, and 96 in leap years) and are
carried to the /19
20 digits in reversion from 99 to 00.
The /19
20 digits cycle between 0 and 1 in reversion from 99 to 00 in the year digits.
*
Any carry from lower digits with the writing of non-existent calendar data may cause the calendar
counters to malfunction. Therefore, such incorrect writing should be replaced with the writing of
existent calendar data.
Oscillation Adjustment Register (Address 7h)
D7 D6 D5 D4 D3 D2 D1 D0
(0) F6 F5 F4 F3 F2 F1 F0 (For
Writing)
(0) F6 F5 F4 F3 F2 F1 F0 (For
Reading)
0 0 0 0 0 0 0 0 Default
Settings
*)
*) Default settings: Default value means read / written values when the XSTP bit is set to "1" due to VDD
power-on from 0v or oscillation stopping
(0) bit
The (0) bit should be set to 0 to allow writing to the Oscillation Adjustment Register. The (0) bit will be set
to 0 when the XSTP bit is set to 1 in the Control Register 2.
F6 to F0 bits
The Oscillation Adjustment Circuit is configured to change time counts of 1 second on the basis of the
settings of the Oscillation Adjustment Register when the second digits read 00, 20, or 40 seconds.
Normally, the Second Counter is incremented once per 32768 32.768-kHz clock pulses generated by the
crystal oscillator. Writing to the F6 to F0 bits activates the oscillation adjustment circuit.
* The Oscillation Adjustment Circuit will not operate with the same timing (00, 20, or 40 seconds) as the
timing of writing to the Oscillation Adjustment Register.
* The F6 bit setting of 0 causes an increment of time counts by ((F5, F4, F3, F2, F1, F0) - 1) x 2.
The F6 bit setting of 1 causes a decrement of time counts by ((/F5, /F4, /F3, /F2, /F1, /F0) + 1) x 2.
The settings of "*, 0, 0, 0, 0, 0, *" ("*" representing either "0" or "1") in the F6, F5, F4, F3, F2, F1, and F0 bits
12345
Rev.2.01 - 18 -
Rx5C348A/B
cause neither an increment nor decrement of time counts.
Example:
When the second digits read 00, 20, or 40, the settings of "0, 0, 0, 0, 1, 1, 1" in the F6, F5, F4, F3, F2, F1,
and F0 bits cause an increment of the current time counts of 32768 by (7 - 1) x 2 to 32780 (a current time
count loss). When the second digits read 00, 20, or 40, the settings of "0, 0, 0, 0, 0, 0, 1" in the F6, F5, F4,
F3, F2, F1, and F0 bits cause neither an increment nor a decrement of the current time counts of 32768.
When the second digits read 00, 20, or 40, the settings of "1, 1, 1, 1, 1, 1, 0" in the F6, F5, F4, F3, F2, F1,
and F0 bits cause a decrement of the current time counts of 32768 by (- 2) x 2 to 32764 (a current time
count gain).
An increase of two clock pulses once per 20 seconds causes a time count loss of approximately 3 ppm (2 /
(32768 x 20 = 3.051 ppm). Conversely, a decrease of two clock pulses once per 20 seconds causes a time
count gain of 3 ppm. Consequently, deviations in time counts can be corrected with a precision of
1.5
ppm. Note that the oscillation adjustment circuit is configured to correct deviations in time counts and not
the oscillation frequency of the 32.768-kHz clock pulses. For further details, see "P.30 Oscillation
Adjustment Circuit".
Alarm_W Registers (Address 8-Ah)
Alarm_W Minute Register (Address 8h)
D7 D6 D5 D4 D3 D2 D1 D0
-
WM40 WM20 WM10 WM8 WM4 WM2 WM1 (For
Writing)
0
WM40 WM20 WM10 WM8 WM4 WM2 WM1 (For
Reading)
0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Default Settings *)
Alarm_W Hour Register (Address 9h)
D7 D6 D5 D4 D3 D2 D1 D0
- -
WH20
WP
/A
WH10 WH8 WH4 WH2 WH1 (For
Writing)
0 0
WH20
WP
/A
WH10 WH8 WH4 WH2 WH1 (For
Reading)
0 0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Default Settings *)
Alarm_W Day-of-week Register (Address Ah)
D7 D6 D5 D4 D3 D2 D1 D0
-
WW6 WW5 WW4 WW3 WW2 WW1 WW0 (For
Writing)
0
WW6 WW5 WW4 WW3 WW2 WW1 WW0 (For
Reading)
0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Default Settings *)
*) Default settings: Default value means read / written values when the XSTP bit is set to "1" due to VDD
power-on from 0v or oscillation stopping
*
The D5 bit of the Alarm_W Hour Register represents WP/A when the 12-hour mode is selected (0 for
a.m. and 1 for p.m.) and WH20 when the 24-hour mode is selected (tens in the hour digits).
*
The Alarm_W Registers should not have any non-existent alarm time settings.
(Note that any mismatch between current time and preset alarm time specified by the Alarm_W registers
may disable the alarm interrupt circuit.)
*
When the 12-hour mode is selected, the hour digits read 12 and 32 for 0 a.m. and 0 p.m., respectively.
(See "P12 Control Register 1 (ADDRESS Eh) (2) /12
24: 12-/24-hour Mode Selection Bit")
*
WW0 to WW6 correspond to W4, W2, and W1 of the day-of-week counter with settings ranging from
(0, 0, 0) to (1, 1, 0).
*
WW0 to WW6 with respective settings of 0 disable the outputs of the Alarm_W Registers.
12345
Rev.2.01 - 19 -
Rx5C348A/B
Example of Alarm Time Setting
Alarm
Day-of-week
12-hour mode
24-hour mode
Preset alarm time
Sun.
Mon. Tue.
Wed. Th.
Fri.
Sat.
10
hr.
1
hr.
10
min.
1
min.
10
hr.
1
hr.
10
min.
1
min.
WW0 WW1 WW2
WW3
WW4
WW5
WW6
00:00
a.m.
on
all
days 1 1 1 1 1 1 1 1
2
0
0
0
0
0
0
01:30
a.m.
on
all
days 1 1 1 1 1 1 1 0
1
3
0
0
1
3
0
11:59
a.m.
on
all
days 1 1 1 1 1 1 1 1
1
5
9
1
1
5
9
00:00
p.m.
on
Mon.
to
Fri.
0 1 1 1 1 1 0 3
2
0
0
1
2
0
0
01:30
p.m.
on
Sun.
1 0 0 0 0 0 0 2
1
3
0
1
3
3
0
11:59 p.m.
on Mon. ,Wed., and Fri.
0 1 0 1 0 1 0 3
1
5
9
2
3
5
9
Note that the correspondence between WW0 to WW6 and the days of the week shown in the above table is
only an example and not mandatory.
Alarm_D Register (Address B-Ch)
Alarm_D Minute Register (Address Bh)
D7 D6 D5 D4 D3 D2 D1 D0
-
DM40 DM20 DM10 DM8 DM4 DM2 DM1 (For
Writing)
0
DM40 DM20 DM10 DM8 DM4 DM2 DM1 (For
Reading)
0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Default Settings *)
Alarm_D Hour Register (Address Ch)
D7 D6 D5 D4 D3 D2 D1 D0
- - DH20
DP
/A
DH10 DH8 DH4 DH2 DH1 (For
Writing)
0 0 DH20
DP
/A
DH10 DH8 DH4 DH2 DH1 (For
Reading)
0 0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Default Settings *)
*) Default settings: Default value means read / written values when the XSTP bit is set to "1" due to VDD
power-on from 0v or oscillation stopping
*
The D5 bit represents DP/A when the 12-hour mode is selected (0 for a.m. and 1 for p.m.) and DH20
when the 24-hour mode is selected (tens in the hour digits).
*
The Alarm_D registers should not have any non-existent alarm time settings.
(Note that any mismatch between current time and preset alarm time specified by the Alarm_D registers
may disable the alarm interrupt circuit.)
*
When the 12-hour mode is selected, the hour digits read 12 and 32 for 0a.m. and 0p.m., respectively.
(See "P12 Control Register 1 (ADDRESS Eh) (2) /12
24: 12-/24-hour Mode Selection Bit")
12345
Rev.2.01 - 20 -
Rx5C348A/B
Interfacing with the CPU
DATA TRANSFER FORMATS
(1) Timing Between CE Pin Transition and Data Input / Output
The Rx5C348A/B adopts a 4-wire serial interface by which they use the CE (Chip Enable), SCLK (Serial Clock),
SI (Serial Input), and SO (Serial Output) pins to receive and send data to and from the CPU. The 4-wire serial
interface provides two types of input/output timings with which the SO pin output and the SI pin input are
synchronized with the rising or falling edges of the SCLK pin input, respectively, and vice versa. The
Rx5C348A/B is configured to select either one of two different input/output timings depending on the level of the
SCLK pin in the low to high transition of the CE pin. Namely, when the SCLK pin is held low in the low to high
transition of the CE pin, the models will select the timing with which the SO pin output is synchronized with the
rising edge of the SCLK pin input, and the SI pin input is synchronized with the falling edge of the SCLK pin input,
as illustrated in the timing chart below.
SCLK
SO
t
DS
SI
CE
t
CES
t
DH
t
RD
Conversely, when the SCLK pin is held high in the low to high transition of the CE pin, the models will select the
timing with which the SO pin output is synchronized with the falling edge of the SCLK pin input, and the SI pin
input is synchronized with the rising edge of the SCLK pin input, as illustrated in the timing chart below.
SCLK
SO
t
DS
SI
CE
t
CES
t
DH
t
RD
(2) Data Transfer Formats
Data transfer is commenced in the low to high transition of the CE pin input and completed in its high to low
transition. Data transfer is conducted serially in multiple units of 1 byte (8 bits). The former 4 bits are used to
specify in the Address Pointer a head address with which data transfer is to be commenced from the host. The
latter 4 bits are used to select either reading data transfer or writing data transfer, and to set the Transfer Format
Register to specify an appropriate data transfer format. All data transfer formats are designed to transfer the
most significant bit (MSB) first.
A2
CE
SCLK
SO
6
A1 A0 C3
C2
C1
C0
D7
D6
D3 D2 D1
D0
A3
7
5
8
2
3
1
2
3
1 4
D7
D6
D3 D2 D1
D0
Reading data transfer
Setting
the Address Pointer
Writing data transfer
Setting the Transfer
Format Register
SI
Two types of data transfer formats are available for reading data transfer and writing data transfer each.
12345
Rev.2.01 - 21 -
Rx5C348A/B
Writing Data Transfer Formats
(1) 1-byte Writing Data Transfer Format
The first type of writing data transfer format is designed to transfer 1-byte data at a time and can be selected by
specifying in the address pointer a head address with which writing data transfer is to be commenced and then
writing the setting of 8h to the transfer format register. This 1-byte writing data transfer can be completed by
driving the CE pin low or continued by specifying a new head address in the address pointer and setting the data
transfer format.
1
1
Data
Data
Example of 1-byte Writing Data Transfer (For Writing Data to Addresses Fh and 7h)
Data transfer from the host
CE
Data transfer from the RTCs
SO
Specifying 7h
in the
Address
Pointer
0
1
0 0
1
1
Setting 8h in
the Transfer
Format
Register
Writing data to
address Fh
Writing data to
address 7h
0
1
1
0 0 0
1 1
Specifying Fh
in the
Address
Pointer
Setting 8h in
the Transfer
Format
Register
SI
(2) Burst Writing Data Transfer Format
The second type of writing data transfer format is designed to transfer a sequence of data serially and can be
selected by specifying in the address pointer a head address with which writing data transfer is to be
commenced and then writing the setting of 0h to the transfer format register. The address pointer is
incremented for each transfer of 1-byte data and cycled from Fh to 0h. This burst writing data transfer can be
completed by driving the CE pin low.
1
0
Data
Data
Example of Burst Writing Data Transfer (For Writing Data to Addresses Eh, Fh, and 0h)
CE
SO
0
0
0 0
1
1
SI
Data
Data transfer from the host
Data transfer from the RTCs
Writing data to
address Eh
Specifying Eh
in the
Address
Pointer
Setting 0h in
the Transfer
Format
Register
Writing data to
address Fh
Writing data to
address 0h
12345
Rev.2.01 - 22 -
Rx5C348A/B
Reading Data Transfer Formats
(1) 1-byte Reading Data Transfer Format
The first type of reading data transfer format is designed to transfer 1-byte data at a time and can be selected by
specifying in the Address Pointer a head address with which reading data transfer is to be commenced and then
the setting of writing Ch to the Transfer Format Register. This 1-byte reading data transfer can be completed by
driving the CE pin low or continued by specifying a new head address in the Address Pointer and selecting this
type of reading data Transfer Format.
1
0
Data
Data
Example of 1-byte Reading Data Transfer (For Reading Data from Addresses Eh and 2h)
CE
SO
1
1
0 0
1
1
0
1
0
1 0 0
0 1
SI
Data transfer from the host
Data transfer from the RTCs
Specifying 2h
in the
Address
Pointer
Setting Ch in
the Transfer
Format
Register
Reading data from
address Eh
Reading data from
address 2h
Specifying Eh
in the
Address
Pointer
Setting Ch in
the Transfer
Format
Register
(2) Burst Reading Data Transfer Format
The second type of reading data transfer format is designed to transfer a sequence of data serially and can be
selected by specifying in the address pointer a head address with which reading data transfer is to be
commenced and then writing the setting of 4h to the transfer format register. The address pointer is
incremented for each transfer of 1-byte data and cycled from Fh to 0h. This burst reading data transfer can be
completed by driving the CE pin low.
1
1
DATA
DATA
Example of Burst Reading Data Transfer (For Reading Data from Addresses Fh, 0h, and 1h)
CE
SO
1
0
0 0
1
1
DATA
SI
Data transfer from the host
Data transfer from the RTCs
Reading data from
address Fh
Specifying Fh
in the
Address
Pointer
Setting 4h in
the Transfer
Format
Register
Reading data from
address 0h
Reading data from
address 1h
12345
Rev.2.01 - 23 -
Rx5C348A/B
(3) Combination of 1-byte Reading and writing Data Transfer Formats
The 1-byte reading and writing data transfer formats can be combined together and further followed by any other
data transfer format.
1
1
DATA
Example of Reading Modify Writing Data Transfer
(For Reading and Writing Data from and to Address Fh)
CE
SO
1
1
0 0
1
1
1
1
1
0 0 0
1 1
DATA
SI
Data transfer from the host
Data transfer from the RTCs
Writing data to
address Fh
Specifying Fh
in the
Address
Pointer
Setting 8h in
the Transfer
Format
Register
Specifying Fh
in the
Address
Pointer
Setting Ch in
the Transfer
Format
Register
Reading data from
address Fh
The reading and writing data transfer formats correspond to the settings in the transfer format register as shown
in the table below.
1
Byte
Burst
Writing data
transfer
8h
(1,0,0,0)
0h
(0,0,0,0)
Reading data
transfer
Ch
(1,1,0,0)
4h
(0,1,0,0)
12345
Rev.2.01 - 24 -
Rx5C348A/B
Considerations in Reading and Writing Time Data under special condition
Any carry to the second digits in the process of reading or writing time data may cause reading or writing
erroneous time data. For example, suppose a carry out of 13:59:59 into 14:00:00 occurs in the process of
reading time data in the middle of shifting from the minute digits to the hour digits. At this moment, the second
digits, the minute digits, and the hour digits read 59 seconds, 59 minutes, and 14 hours, respectively (indicating
14:59:59) to cause the reading of time data deviating from actual time virtually 1 hour. A similar error also
occurs in writing time data. To prevent such errors in reading and writing time data, the Rx5C348A/B has the
function of temporarily locking any carry to the second digits during the high interval of the CE pin and unlocking
such a carry in its high to low transition. Note that a carry to the second digits can be locked for only 1 second,
during which time the CE pin should be driven low.
CE
Time counts
within RTC
14:00:01
Actual time
13:59:59
Max.62
s
14:00:00
13:59:59 14:00:00 14:00:01
The effective use of this function requires the following considerations in reading and writing time data:
(1) Hold the CE pin high in each session of reading or writing time data.
(2) Ensure that the high interval of the CE pin lasts within 1 second. Should there be any possibility of the host
going down in the process of reading or writing time data, make arrangements in the peripheral circuitry as to
drive the CE pin low or open at the moment that the host actually goes down.
(3) Leave a time span of 31
s or more from the low to high transition of the CE pin to the start of access to
addresses 0h to 6h in order that any ongoing carry of the time digits may be completed within this time span.
(4) Leave a time span of 62
s or more from the high to low transition of the CE pin to its low to high transition in
order that any ongoing carry of the time digits during the high interval of the CE pin may be adjusted within this
time span.
The considerations listed in (1), (3), and (4) above are not required when the process of reading or writing time
data is obviously free from any carry of the time digits.
(e.g. reading or writing time data in synchronization with the periodic interrupt function in the level mode or the
alarm interrupt function).
Good and bad examples of reading and writing time data are illustrated on the next page.
12345
Rev.2.01 - 25 -
Rx5C348A/B
SO
0Ch
Data
Data
Bad Example (1)
(Where the CE pin is once driven low in the process of reading time data)
Less than 62
s
SO
F0h
CE
Time span of less than 31
s
Writing to
Address 0h
(sec.)
0Ch
CE
Bad Example (3)
(Where a time span of less than 61
s is left between the adjacent processes of reading time data)
Good Example
SO
DATA
F4h
DATA
DATA
CE
Address Pointer
= 1h
Transfer Format
Register = 4h
Time span of 31
s or more
Reading from
Address 1h
(min.)
DATA
SO
0Ch
Data
Data
31
s or more
Reading from
Address 1h
(min.)
Data
14h
31
s or more
CE
Data transfer from RTCs
0Ch
Data
Data transfer from the host
Bad Example (2)
(Where a time span of less than 31
s is left until the start of the process of writing time data)
Any address other than addresses 0h to 6h
permits of immediate reading or writing without
requiring a time span of 31
s.
SI
SI
SI
SI
Data
Data
Data
Data
Reading from
Address Fh
(control2)
Reading from
Address 0h
(sec.)
Reading from
Address 2h
(hr.)
Address Pointer
= Fh
Transfer Format
Register = 4h
Address Pointer
= Fh
Transfer Format
Register = 0h
Reading from
Address 0h
(sec.)
Reading from
Address 2h
(hr.)
Address Pointer
= 0h
Transfer Format
Register = Ch
Writing to
Address 1h
(min.)
Writing to
Address 2h
(hr.)
Writing to
Address Fh
(contorl2)
Address Pointer
= 0h
Transfer Format
Register = Ch
Reading from
Address 0h
(sec.)
Reading from
Address 0h
(sec.)
Address Pointer
= 0h
Transfer Format
Register = Ch
12345
Rev.2.01 - 26 -
Rx5C348A/B
Configuration of Oscillation Circuit and Correction of Time Count Deviations
Configuration of Oscillation Circuit
OSCIN
OSCOUT
VDD
VDD
32kHz
RD
RF
CG
CD
A
Typical externally-equipped element
X'tal : 32.768kHz
(R1=30k
typ)
(CL=6pF
to
8pF)
Standard values of internal elements
RF
15M
typ
RD
120k
typ
CG,CD 12pF typ
The oscillation circuit is driven at a constant voltage of approximately 1.2v relative to the level of the VSS pin
input. As such, it is configured to generate an oscillating waveform with a peak-to-peak voltage on the order of
1.2v on the positive side of the VSS pin input.
< Considerations in Handling Crystal Oscillators >
Generally, crystal oscillators have basic characteristics including an equivalent series resistance (R1) indicating
the ease of their oscillation and a load capacitance (CL) indicating the degree of their center frequency.
Particularly, crystal oscillators intended for use in the Rx5C348A/B are recommended to have a typical R1 value
of 30k
and a typical CL value of 6 to 8pF. To confirm these recommended values, contact the manufacturers
of crystal oscillators intended for use in these particular models.
< Considerations in Installing Components around the Oscillation Circuit >
1) Install the crystal oscillator in the closest possible vicinity to the real-time clock ICs.
2) Avoid laying any signal lines or power lines in the vicinity of the oscillation circuit (particularly in the area
marked "A" in the above figure).
3) Apply the highest possible insulation resistance between the OSCIN and OSCOUT pins and the printed circuit
board.
4) Avoid using any long parallel lines to wire the OSCIN and OSCOUT pins.
5) Take extreme care not to cause condensation, which leads to various problems such as oscillation halt.
< Other Relevant Considerations >
1) For external input of 32.768-kHz clock pulses to the OSCIN pin:
DC coupling: Prohibited due to an input level mismatch.
AC coupling: Permissible except that the oscillation halt sensing circuit does not guarantee perfect operation
because it may cause sensing errors due to such factors as noise.
2) To maintain stable characteristics of the crystal oscillator, avoid driving any other IC through 32.768-kHz clock
pulses output from the OSCOUT pin.
12345
Rev.2.01 - 27 -
Rx5C348A/B
Measurement of Oscillation Frequency
Frequency
Counter
OSCIN
OSCOUT
32KOUT
VSS
32768Hz
VDD
* 1)
The Rx5C348A/B is configured to generate 32.768-kHz clock pulses for output from the 32KOUT pin.
* 2) A frequency counter with 6 (more preferably 7) or more digits on the order of 1ppm is recommended
for use in the measurement of the oscillation frequency of the oscillation circuit.
Adjustment of Oscillation frequency
The oscillation frequency of the oscillation circuit can be adjusted by varying procedures depending on the usage
of Model Rx5C348A/B in the system into which they are to be built and on the allowable degree of time count
errors. The flow chart below serves as a guide to selecting an optimum oscillation frequency adjustment
procedure for the relevant system.
Start
Course (B)
Use 32-kHz clock output without regard
to its frequency precision
NO
YES
Use 32-kHz
clock output?
YES
NO
Course (C)
Course (A)
Course (D)
YES
YES
NO
NO
Allowable time count precision on order of oscillation
frequency variations of crystal oscillator (*1) plus
frequency variations of RTC (*2)? (*3)
Allowable time count precision on order of oscillation
frequency variations of crystal oscillator (*1) plus
frequency variations of RTC (*2)? (*3)
* 1) Generally, crystal oscillators for commercial use are classified in terms of their center frequency
depending on their load capacitance (CL) and further divided into ranks on the order of
10,
20, and
50ppm depending on the degree of their oscillation frequency variations.
* 2) Basically, Model Rx5C348A/B is configured to cause frequency variations on the order of
5 to
10ppm at 25
C.
* 3) Time count precision as referred to in the above flow chart is applicable to normal temperature and
actually affected by the temperature characteristics and other properties of crystal oscillators.
12345
Rev.2.01 - 28 -
Rx5C348A/B
Course (A)
When the time count precision of each RTC is not to be adjusted, the crystal oscillator intended for use in that
RTC may have any CL value requiring no presetting. The crystal oscillator may be subject to frequency
variations which are selectable within the allowable range of time count precision. Several crystal oscillators
and RTCs should be used to find the center frequency of the crystal oscillators by the method described in "P.28
Adjustment of Oscillation frequency" and then calculate an appropriate oscillation adjustment value by the
method described in "P.30 Oscillation Adjustment Circuit" for writing this value to the Rx5C348A/B.
Course (B)
When the time count precision of each RTC is to be adjusted within the oscillation frequency variations of the
crystal oscillator plus the frequency variations of the real-time clock ICs, it becomes necessary to correct
deviations in the time count of each RTC by the method described in " P.30 Oscillation Adjustment Circuit".
Such oscillation adjustment provides crystal oscillators with a wider range of allowable settings of their oscillation
frequency variations and their CL values. The real-time clock IC and the crystal oscillator intended for use in
that real-time clock IC should be used to find the center frequency of the crystal oscillator by the method
described in " P28 Measurement of Oscillation Frequency " and then confirm the center frequency thus
found to fall within the range adjustable by the oscillation adjustment circuit before adjusting the oscillation
frequency of the oscillation circuit. At normal temperature, the oscillation frequency of the oscillator circuit can
be adjusted by up to approximately
0.5ppm.
Course (C)
Course (C) together with Course (D) requires adjusting the time count precision of each RTC as well as the
frequency of 32.768-kHz clock pulses output from the 32KOUT pin. Normally, the oscillation frequency of the
crystal oscillator intended for use in the RTCs should be adjusted by adjusting the oscillation stabilizing
capacitors CG and CD connected to both ends of the crystal oscillator. The Rx5C348A/B, which incorporate the
CG and the CD, require adjusting the oscillation frequency of the crystal oscillator through its CL value.
Generally, the relationship between the CL value and the CG and CD values can be represented by the following
equation:
CL = (CG
CD)/(CG + CD) + CS where "CS" represents the floating capacity of the printed circuit board.
The crystal oscillator intended for use in the Rx5C348A/B is recommended to have the CL value on the order of
6 to 9pF. Its oscillation frequency should be measured by the method described in " P.28 Measurement of
Oscillation Frequency ". Any crystal oscillator found to have an excessively high or low oscillation frequency
(causing a time count gain or loss, respectively) should be replaced with another one having a smaller and
greater CL value, respectively until another one having an optimum CL value is selected. In this case, the bit
settings disabling the oscillation adjustment circuit (see " P.30 Oscillation Adjustment Circuit") should be
written to the oscillation adjustment register.
Incidentally, the high oscillation frequency of the crystal oscillator can also be adjusted by adding an external
oscillation stabilization capacitor CGOUT as illustrated in the diagram below.
32kHz
RD
CG
CD
OSCIN
OSCOUT
CGOUT
Oscillator
Circuit
*1) The CGOUT should have a capacitance ranging
from 0 to 15 pF.
Course (D)
It is necessary to select the crystal oscillator in the same manner as in Course (C) as well as correct errors in the
time count of each RTC in the same manner as in Course (B) by the method described in " P.30 Oscillation
Adjustment Circuit ".
12345
Rev.2.01 - 29 -
Rx5C348A/B
Oscillation Adjustment Circuit
The oscillation adjustment circuit can be used to correct a time count gain or loss with high precision by varying
the number of 1-second clock pulses once per 20 seconds. The oscillation adjustment circuit can be disabled
by writing the settings of "*, 0, 0, 0, 0, 0, *" ("*" representing "0" or "1") to the F6, F5, F4, F3, F2, F1, and F0 bits
in the oscillation adjustment circuit. Conversely, when such oscillation adjustment is to be made, an appropriate
oscillation adjustment value can be calculated by the equation below for writing to the oscillation adjustment
circuit.
(1) When Oscillation Frequency (* 1) Is Higher Than Target Frequency (* 2) (Causing Time Count Gain)
Oscillation adjustment value (*3) = (Oscillation frequency - Target Frequency + 0.1)
Oscillation frequency
3.051
10
-6
(Oscillation Frequency Target Frequency)
10 + 1
* 1)
Oscillation frequency:
Frequency of clock pulse output from the 32KOUT pin at normal temperature in the manner described
in " P.28 Measurement of Oscillation Frequency ".
* 2)
Target frequency:
Desired frequency to be set. Generally, a 32.768-kHz crystal oscillator has such temperature
characteristics as to have the highest oscillation frequency at normal temperature. Consequently,
the crystal oscillator is recommended to have target frequency settings on the order of 32.768 to
32.76810 kHz (+3.05ppm relative to 32.768 kHz). Note that the target frequency differs depending
on the environment or location where the equipment incorporating the RTC is expected to be
operated.
* 3)
Oscillation adjustment value:
Value that is to be finally written to the F0 to F6 bits in the Oscillation Adjustment Register and is
represented in 7-bit coded decimal notation.
(2) When Oscillation Frequency Is Equal To Target Frequency (Causing Time Count neither Gain nor Loss)
Oscillation adjustment value = 0, +1, -64, or 63
(3) When Oscillation Frequency Is Lower Than Target Frequency (Causing Time Count Loss)
Oscillation adjustment value = (Oscillation frequency - Target Frequency)
Oscillation frequency
3.051
10
-6
(Oscillation Frequency Target Frequency)
10
Oscillation adjustment value calculations are exemplified below
(A) For an oscillation frequency = 32768.85Hz and a target frequency = 32768.05Hz
Oscillation adjustment value = (32768.85 - 32768.05 + 0.1) / (32768.85
3.051
10
-6
)
(32768.85 - 32768.05)
10 + 1
= 9.001
9
In this instance, write the settings ((0),F6,F5,F4,F3,F2,F1,F0)=(0,0,0,0,1,0,0,1) in the oscillation adjustment
register. Thus, an appropriate oscillation adjustment value in the presence of any time count gain represents a
distance from 01h.
(B) For an oscillation frequency = 32762.22Hz and a target frequency = 32768.05Hz
Oscillation adjustment value = (32762.22 - 32768.05) / (32762.22
3.051
10
-6
)
(32762.22 - 32768.05)
10
= -58.325
-58
To represent an oscillation adjustment value of - 58 in 7-bit coded decimal notation, subtract 58 (3Ah) from 128
(80h) to obtain 46h. In this instance, write the settings of ((0),F6,F5,F4,F3,F2,F1,F0) = (0,1,0,0,0,1,1,0) in the
oscillation adjustment register. Thus, an appropriate oscillation adjustment value in the presence of any time
count loss represents a distance from 80h.
12345
Rev.2.01 - 30 -
Rx5C348A/B
Notes:
1)
Oscillation adjustment does not affect the frequency of 32.768-kHz clock pulses output from the
32KOUT pin.
2)
If following 3 conditions are completed, actual clock adjustment value could be different from target
adjustment value that set by oscillator adjustment function.
1. Using oscillator adjustment function
2. Access to Rx5C348A/B at random, or synchronized with external clock that has no relation to
Rx5C348A/B, or synchronized with periodic interrupt in pulse mode.
3. Access to Rx5C348A/B more than 2 times per each second on average.
For more details, please contact to Ricoh.
How to evaluate the clock gain or loss
The oscillator adjustment circuit is configured to change time counts of 1 second on the basis of the settings of
the oscillation adjustment register once in 20 seconds or 60 seconds. The oscillation adjustment circuit does
not effect the frequency of 32768Hz-clock pulse output from the 32KOUT pin. Therefore, after writing the
oscillation adjustment register, we cannot measure the clock error with probing 32KOUT clock pulses. The way
to measure the clock error as follows:
(1) Output a 1Hz clock pulse of Pulse Mode with interrupt pin
Set (0,0,x,x,0,0,1,1) to Control Register 1 at address Eh.
(2) After setting the oscillation adjustment register, 1Hz clock period changes every 20seconds ( or every 60
seconds) like next page figure.
1Hz clock pulse
T0 T0
T0
T1
1 time
19 times
Measure the interval of T0 and T1 with frequency counter. A frequency counter with 7 or more digits is
recommended for the measurement.
(3) Calculate the typical period from T0 and T1
T = (19
T0+1
T1)/20
Calculate the time error from T.
12345
Rev.2.01 - 31 -
Rx5C348A/B
Oscillation Halt Sensing, and Supply Voltage Monitoring
XSTP and VDET
The oscillation halt sensing circuit is configured to record a halt on oscillation by 32.768-kHz clock pulses. The
supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold voltage of 2.1
or 1.6v.
Each function has a monitor bit. I.e. XSTP bit is for the oscillation halt sensing circuit, and VDET is for the
supply voltage monitoring circuit. XSTP and VDET bits are activated to "H". The XSTP and VDET accept only
the writing of 0. The XSTP bit is set to 1, when VDD power-up from 0V, but VDET is set to 0.
The functions of these two monitor bits are shown in the table below.
Oscillation Halt Sensing Circuit operates only when CE pin is Low. Sensing result is maintained after CE pin
changes from "L" to "H".
XSTP
VDET
Conditions of supply voltage and oscillation
0
0
No drop in supply voltage below threshold voltage and no halt in oscillation
0
1
Drop in supply voltage below threshold voltage and no halt in oscillation
1
*
Halt on oscillation
32768Hz Oscillation
Oscillation halt
sensing flag (XSTP)
Threshold voltage (2.1v or 1.6v)
VDD
Supply voltage
monitor flag (VDET)
Internal initialization
period (1 to 2 sec.)
VDET
0
XSTP
0
VDET
0
VDET
0
XSTP
0
Internal initialization
period (1 to 2 sec.)
When the XSTP bit is set to 1 in the control register 2, the (0), F6 to F0, WALE, DALE, /12
24, /CLEN2, TEST,
CT2, CT1, CT0, VDSL, VDET, /CLEN1, CTFG, WAFG, DAFG, SCRATCH1/2/3 bits are reset to 0 in the oscillation
adjustment register, the control register 1, and the control register 2.
< Considerations in Using Oscillation Halt Sensing Circuit >
Be sure to prevent the oscillation halt sensing circuit from malfunctioning by preventing the following:
1) Instantaneous power-down on the VDD
2) Condensation on the crystal oscillator
3) On-board noise to the crystal oscillator
4) Applying to individual pins voltage exceeding their respective maximum ratings
In particular, note that the XSTP bit may fail to be set to 0 in the presence of any applied supply voltage as
illustrated below in such events as backup battery installation. Further, give special considerations to prevent
excessive chattering in the oscillation halt sensing circuit.
VDD
12345
Rev.2.01 - 32 -
Rx5C348A/B
Voltage Monitoring Circuit
The supply monitoring circuit is configured to conduct a sampling operation during an interval of 7.8ms per
second to check for a drop in supply voltage below a threshold voltage of 2.1 or 1.6v for the VDSL bit setting of 0
(the default setting) or 1, respectively, in the Control Register 2, thus minimizing supply current requirements as
illustrated in the timing chart below. This circuit suspends a sampling operation once the VDET bit is set to 1 in
the Control Register 2. The supply voltage monitor is useful for back-up battery checking.
VDET
(D6 in Address Fh)
XSTP
VDD
2.1v or 1.6v
1s
VDET
0
7.8ms
Sampling timing for
VDD supply voltage
Internal
initialization
period
(1 to 2sec.)
XSTP
0
VDET
0
12345
Rev.2.01 - 33 -
Rx5C348A/B
Alarm and Periodic Interrupt
The Rx5C348A/B incorporates the alarm interrupt circuit and the periodic interrupt circuit that are configured to
generate alarm signals and periodic interrupt signals for output from the /INTR pin as described below.
(1) Alarm Interrupt Circuit
The alarm interrupt circuit is configured to generate alarm signals for output from the /INTR, which is driven low
(enabled) upon the occurrence of a match between current time read by the time counters (the day-of-week,
hour, and minute counters) and alarm time preset by the alarm registers (the Alarm_W registers intended for the
day-of-week, hour, and minute digit settings and the Alarm_D registers intended for the hour and minute digit
settings).
(2) Periodic Interrupt Circuit
The periodic interrupt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals in
the level mode for output from the /INTR pin depending on the CT2, CT1, and CT0 bit settings in the control
register 1.
The above two types of interrupt signals are monitored by the flag bits (i.e. the WAFG, DAFG, and CTFG bits in
the Control Register 2) and enabled or disabled by the enable bits (i.e. the WALE, DALE, CT2, CT1, and CT0
bits in the Control Register 1) as listed in the table below.
Flag bits
Enable bits
Alarm_W WAFG
(D1 at Address Fh)
WALE
(D7 at Address Eh)
Alarm_D DAFG
(D0 at Address Fh)
DALE
(D6 at Address Eh)
Peridic interrupt
CTFG
(D2 at Address Fh)
CT2=CT1=CT0=0
(These bit setting of "0" disable the Periodic Interrupt)
(D2 to D0 at Address Eh)
* At power-on, when the WALE, DALE, CT2, CT1, and CT0 bits are set to 0 in the Control Register 1,
the /INTR pin is driven high (disabled).
* When two types of interrupt signals are output simultaneously from the /INTR pin, the output from the
/INTR pin becomes an OR waveform of their negative logic.
Example: Combined Output to /INTR Pin Under Control of
/ALARM_D and Periodic Interrupt
Periodic Interrupt
/INTR
/Alarm_D
In this event, which type of interrupt signal is output from the /INTR pin can be confirmed by reading the
DAFG, and CTFG bit settings in the Control Register 2.
Alarm Interrupt
The alarm interrupt circuit is controlled by the enable bits (i.e. the WALE and DALE bits in the Control Register 1)
and the flag bits (i.e. the WAFG and DAFG bits in the Control Register 2). The enable bits can be used to
enable this circuit when set to 1 and to disable it when set to 0. When intended for reading, the flag bits can be
used to monitor alarm interrupt signals. When intended for writing, the flag bits will cause no event when set to
1 and will drive high (disable) the alarm interrupt circuit when set to 0.
The enable bits will not be affected even when the flag bits are set to 0. In this event, therefore, the alarm
interrupt circuit will continue to function until it is driven low (enabled) upon the next occurrence of a match
between current time and preset alarm time.
12345
Rev.2.01 - 34 -
Rx5C348A/B
The alarm function can be set by presetting desired alarm time in the alarm registers (the Alarm_W Registers for
the day-of-week digit settings and both the Alarm_W Registers and the Alarm_D Registers for the hour and
minute digit settings) with the WALE and DALE bits once set to 0 and then to 1 in the Control Register 1. Note
that the WALE and DALE bits should be once set to 0 in order to disable the alarm interrupts circuit upon the
coincidental occurrence of a match between current time and preset alarm time in the process of setting the
alarm function.
current time =
preset alarm time
WALE
1
(DALE)
Interval (1min.) during which a match
between current time and preset alarm time
occurs
current time =
preset alarm time
WAFG
0
(DAFG)
/INTR
WALE
1
(DALE)
WALE
1
(DALE)
current time =
preset alarm time
WALE
0
(DALE)
current time =
preset alarm time
/INTR
After setting WALE(DALW) to 0, Alarm registers is set to current time, and WALE(DALE) is set to 1, /INTR will be
not driven to "L" immediately, /INTR will be driven to "L" at next alarm setting time.
Periodic Interrupt
Setting of the periodic selection bits (CT2 to CT0) enables periodic interrupt to the CPU. There are two waveform
modes: pulse mode and level mode. In the pulse mode, the output has a waveform duty cycle of around 50%.
In the level mode, the output is cyclically driven low and, when the CTFG bit is set to 0, the output is return to
High (OFF).
Description
CT2 CT1 CT0
Wave form mode
Interrupt Cycle and Falling Timing
0 0 0 -
OFF(H)
(Default)
0 0 1 -
Fixed
at
"L"
0 1 0 Pulse
Mode
*1) 2Hz(Duty50%)
0 1 1 Pulse
Mode
*1) 1Hz(Duty50%)
1
0
0
Level Mode *2)
Once per 1 second (Synchronized with
Second counter increment)
1
0
1
Level Mode *2)
Once per 1 minute (at 00 seconds of every
Minute)
1
1
0
Level Mode *2)
Once per hour (at 00 minutes and 00
Seconds of every hour)
1
1
1
Level Mode *2)
Once per month (at 00 hours, 00 minutes,
and 00 seconds of first day of every month)
*1) Pulse Mode:
2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter as
illustrated in the timing chart below.
/INTR Pin
Rewriting of the second counter
CTFG Bit
Approx. 92
s
(Increment of second counter)
12345
Rev.2.01 - 35 -
Rx5C348A/B
In the pulse mode, the increment of the second counter is delayed by approximately 92
s from the
falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock
pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second.
Rewriting the second counter will reset the other time counters of less than 1 second, driving the
/INTR pin low.
*2) Level Mode:
Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1
hour, and 1 month. The increment of the second counter is synchronized with the falling edge of
periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1
second are output in synchronization with the increment of the second counter as illustrated in the
timing chart below.
Setting CTFG bit to 0
CTFG Bit
/INTR Pin
(Increment of
second counter)
(Increment of
second counter)
(Increment of
second counter)
Setting CTFG bit to 0
*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. as
follows:
Pulse Mode: The "L" period of output pulses will increment or decrement by a maximum of
3.784ms. For
example, 1-Hz clock pulses will have a duty cycle of 50
0.3784%.
Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of
3.784 ms.
32-kHz CLOCK OUTPUT
For the Rx5C348A, 32.768-kHz clock pulses are output from the 32KOUT pin when either the /CLEN1 bit in
the Control Register 2 or the /CLEN2 bit in the Control Register 1 is set to 0. When both the /CLEN1 and
/CLEN2 bits are set to 0, the 32KOUT pin output is driven high (off).
/CLEN1
(D3 at Address Fh)
/CLEN2
(D4 at Address Eh)
32KOUT PIN
(N-channel Open Drain)
1 1 OFF(H)
0(Default) *
* 0(Default)
Clock pulses
The 32KOUT pin output is synchronized with the /CLEN1 and /CLEN2 bit settings as illustrated in the timing
chart below.
32KOUT PIN
Max.62.0
s
/CLEN1or2
For the Rx5C348B, 32.768-kHz clock pulses are output from the 32KOUT pin regardless of such internal
register settings.
12345
Rev.2.01 - 36 -
Rx5C348A/B
Typical Applications
Typical Power Circuit Configurations
Sample circuit configuration 1
VDD
OSCIN
OSCOUT
VSS
32768Hz
System power supply
*1)
*1) Install bypass capacitors for high-frequency
and low-frequency applications in parallel in
close vicinity to the Rx5C348A/B.
Sample circuit configuration 2
*1)
OSCIN
OSCOUT
VSS
32768Hz
System power supply
VDD
Primary
Battery
*1) When using an OR diode as a power supply for
the Rx5C348A/B ensure that voltage
exceeding the absolute maximum rating of
VDD+0.3v is not applied the 32KOUT pin.
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Rev.2.01 - 37 -
*1)
OSCIN
OSCOUT
VSS
32768Hz
System power supply
VDD
Secondary
Battery
Rx5C348A/B
Connection of /INTR and 32KOUT Pin
The /INTR pin follows the N-channel open drain output logic and contains no protective diode on the power
supply side. As such, it can be connected to a pull-up resistor of up to 5.5v regardless of supply voltage.
The 32KOUT pin follows the N-channel open drain output logic, too. However, it contains protective diode on the
power supply side. As such, it cannot be connected to a pull-up resistor over VDD+0.3v. Such connection
involves considerations for the supply current requirements of a pull-up resistor, which can be roughly calculated
by the following equation:
I = 0.5
(VDD or VCC) / Rp
VSB
OSCIN
OSCOUT
/INTR or 32KOUT
*1)
32768Hz
B
A
Backup power supply
(VCC)
System power supply
(VDD)
VSS
*1) Depending on whether the /INTR or 32KOUT
pins are to be used during battery backup, it
should be connected to a pull-up resistor at
the following different positions:
(1) Position A in the left diagram when it is not to
be used during battery backup.
(2) Position B in the left diagram when it is to be
used during battery backup.
Connection of CE Pin
Connection of the CE pin requires the following considerations:
1) The CE pin is configured to enable the oscillation halt sensing circuit only when driven low. As such, it
should be driven low or open at power-on from 0v.
2) The CE pin should also be driven low or open immediately upon the host going down (see "P.25
Considerations in Reading and Writing Time Data under special condition").
I/O
CONTROL
SO
SCLK
CE
SI
CE
Min.0
s
VDD
Lower limit operating
voltage for the CPU
Min.0
s
Min.0
s
0.2
VDD
Backup power supply
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Rev.2.01 - 38 -
Rx5C348A/B
Connection With 3-Wire Serial Interface Bus
To connect the Rx5C348A/B with 3-wire serial interface bus, shorten the SI and SO pins and connect them to the
data line as shown in the figure below.
CE
The other
Peripheral IC
CE1
SCLK
DATA
Host
SCLK
SIO
SO
CE0
CE
SCLK
SI
Rx5C348A/B
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Rev.2.01 - 39 -
Rx5C348A/B
Typical Characteristics
Test circuit
Frequency
Counter
VDD
OSCIN
OSCOUT
32KOUT
VSS
32768Hz
X'tal : 32.768kHz
(R1=30k
typ)
(CL=6pF to 8pF)
Topt : 25
C
Output pins : Open
Timekeeping Current vs. Supply voltage Timekeeping Current vs. Supply voltage
(with no 32-kHz clock output) (with 32-kHz clock output)
(CE=Open, Output=Open, Topt=25
C,Rx5C348A) (CE=Open, Output=Open,Topt=25
C)
0
0.2
0.4
0.6
0.8
1
0
1
2
3
4
5
6
Supply Voltage VDD(v)
T
i
mekeeping Current IDD (uA)
0
0.5
1
1.5
2
0
1
2
3
4
5
6
Supply Voltage VDD(v)
T
i
mekeeping Current IDD(uA)
Rx5C348A
Rx5C348B
CPU Access Current vs. SCLK Clock Frequency Timekeeping Current vs. Operating Temperature
(Output=Open, Topt=25
C) (with no 32-kHz clock output)
(CE=Open, Output=Open)
0
10
20
30
40
50
0
500
1000
1500
2000
SCLK Clock Frequency (kHz)
CPU Access Current IDD(uA)
0
0.5
1
1.5
2
-60 -40 -20 0
20 40 60 80 100
Operating Temperature Topt(
C)
T
i
mekeeping Current IDD(uA)
VDD=5v
VDD=3v
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Rev.2.01 - 40 -
Rx5C348A/B
Oscillation Frequency Deviation vs. External CG Oscillation Frequency Deviation vs. Supply Voltage
(VDD=3v,Topt=25
C, (Topt=25
C,VDD=3v as standard)
External CG=0pF as standard)
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
0
5
10
15
20
External CG (pF)
O
scillat
i
on F
r
equency Devit
a
t
i
on
(ppm)
-5
-4
-3
-2
-1
0
1
2
3
4
5
0
1
2
3
4
5
6
Supply Voltage VDD(v)
Oscillation Frequency
Devitation (ppm)
Oscillation Frequency Deviation vs. Operating Temperature
Oscillation Start Time vs. Supply Voltage
(VDD=3v, Topt=25
C external CG=0pF as standard) (Topt=25
C)
-140
-120
-100
-80
-60
-40
-20
0
20
-60 -40 -20 0 20 40 60 80 10
0
Operating Temperature Topt(
C)
Oscillation Frequency
Devitation (ppm)
0
100
200
300
400
500
0
1
2
3
4
5
6
Supply Voltage VDD(v)
Oscillation Start Time (ms)
VOL vs. IOL VOL vs. IOL
(32KOUT Pin of the Rx5C348A and /INTR Pin) (32KOUT Pin of the Rx5C348B)
(Topt=25
C) (Topt=25
C)
0
5
10
15
20
25
30
0
0.2
0.4
0.6
0.8
1
VOL (v)
IOL (mA)
0
2
4
6
8
10
0
0.2
0.4
0.6
0.8
1
VOL (v)
IOL (mA)
VDD=5v
VDD=5v
VDD=3v
VDD=3v
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Rev.2.01 - 41 -
Rx5C348A/B
Typical Software-based Operations
Initialization at Power-on
Start
*1)
Yes
No
VDET=0?
Warning Back-up
Battery Run-down
Set Oscillation Adjustment
Register and Control
Register 1 and 2, etc.
Power-on
*2)
*4)
*3)
XSTP=1?
Yes
No
*1)
After power-on from 0 volt, the start of oscillation and the process of internal initialization require a
time span on 1to 2seconds, so that access should be done after the lapse of this time span or more.
*2)
The XSTP bit setting of 0 in the Control Register 1 indicates power-on from backup battery and not
from 0v. For further details, see "P.32 XSTP and VDET".
*3)
This step is not required when the supply voltage monitoring circuit is not used.
*4)
This step involves ordinary initialization including the Oscillation Adjustment Register and interrupt
cycle settings, etc.
Writing of Time and Calendar Data
Write to Time Counter and
Calendar Counter
*2)
CE
L
*3)
CE
H
*1)
*1) When writing to clock and calendar counters, do not drive CE to "L" until
all times from second to year have been written to prevent error in writing
time. (Detailed in "P.24
Considerations in Reading and Writing
Time Data under special condition
".
*2) Any writing to the second counter will reset divider units lower than the
second digits.
*3) Take care so that process from CE driving to "H" to driving to "L" will be
complete within 1.0sec. (Detailed in "P.24
Adjustment of Oscillation
frequency
".
The Rx5C348A/B may also be initialized not at power-on but in the
process of writing time and calendar data.
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Rev.2.01 - 42 -
Rx5C348A/B
Reading Time and Calendar Data
(1) Ordinary Process of Reading Time and Calendar Data
Read from Time Counter
and Calendar Counter
*2)
CE
L
CE
H
*1)
*1) When writing to clock and calendar counters, do not insert Stop Condition
until all times from second to year have been written to prevent error in
writing time. (Detailed "P.24
Considerations in Reading and Writing
Time Data under special condition
".
*2) Take care so that process from Start Condition to Stop Condition will be
complete within 0.5sec. (Detailed in "P.24
Considerations in
Reading and Writing Time Data under special condition
".
(2) Basic Process of Reading Time and Calendar Data with Periodic Interrupt Function
*1) This step is intended to select the level mode as a
waveform mode for the periodic interrupt function.
*2) This step must be completed within 1.0 second.
*3) This step is intended to set the CTFG bit to 0 in the
Control Register 2 to cancel an interrupt to the CPU.
*2)
Other Interrupt
Processes
Set Periodic Interrupt
Cycle Selection Bits
CTFG=1?
Read from Time Counter
and Calendar Counter
Yes
No
Control Register 2
(X1X1X011)
Generate Interrupt in CPU
*1)
*3)
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Rev.2.01 - 43 -
Rx5C348A/B
(3) Applied Process of Reading Time and Calendar Data with Periodic Interrupt Function
Time data need not be read from all the time counters when used for such ordinary purposes as time count
indication. This applied process can be used to read time and calendar data with substantial reductions in the
load involved in such reading.
For Time Indication in "Day-of-Month, Day-of-week, Hour, Minute, and Second" Format:
*2)
Other interrupts
Processes
Sec.=00?
Yes
No
Generate interrupt to CPU
*1)
*3)
CTFG=1?
Control Register 2
(X1X1X011)
Yes
Read Min.,Hr.,Day,
and Day-of-week
*4)
No
Control Register 1
(XXXX0100)
Control Register 2
(X1X1X011)
Use previous Min.,Hr.,
Day, and Day-of-week data
*1) This step is intended to select the level
mode as a waveform mode for the
periodic interrupt function.
*2) This step must be completed within 1.0
sec.
*3) This step is intended to read time data
from all the time counters only in the
first session of reading time data after
writing time data.
*4) This step is intended to set the CTFG
bit to 0 in the Control Register 2 to
cancel an interrupt to the CPU.
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Rev.2.01 - 44 -
Rx5C348A/B
Interrupt Process
(1) Periodic Interrupt
*2)
Other Interrupt
Processes
Set Periodic Interrupt
Cycle Selection Bits
CTFG=1?
Conduct
Periodic Interrupt
Yes
No
Control Register 2
(X1X1X011)
Generate Interrupt to CPU
*1)
*1) This step is intended to select the level mode as a
waveform mode for the periodic interrupt function.
*2) This step is intended to set the CTFG bit to 0 in
the Control Register 2 to cancel an interrupt to the
CPU.
(2) Alarm Interrupt
*3)
Other Interrupt
Processes
Set Alarm Min., Hr., and
Day-of-week Registers
WAFG or DAFG=1?
Conduct Alarm Interrupt
Yes
No
Control Register 2
(X1X1X101)
Generate Interrupt to CPU
*1)
WALE or DALE
0
*2)
WALE or DALE
1
*1) This step is intended to once disable the alarm
interrupt circuit by setting the WALE or DALE bits to 0
in anticipation of the coincidental occurrence of a
match between current time and preset alarm time in
the process of setting the alarm interrupt function.
*2) This step is intended to enable the alarm interrupt
function after completion of all alarm interrupt
settings.
*3) This step is intended to once cancel the alarm
interrupt function by writing the settings of "X,1,X,
1,X,1,0,1" and "X,1,X,1,X,1,1,0" to the Alarm_W
Registers and the Alarm_D Registers, respectively.
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Rev.2.01 - 45 -
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