1
Multimedia ICs
SYNC separator IC with AFC
BA7062F
The BA7062F separates the synchronization signals from a video signal and outputs the horizontal and vertical syn-
chronization signals (H
D
and V
D
), and the composite synchronization signal (Sync-out).
The H
D
and V
D
pulse widths are different.
Applications
TVs and VCRs
Features
1) Built-in AFC circuit.
2) Low power dissipation (approx. 21mW).
3) Low external parts count.
4) SOP 8-pin package.
5) Horizontal free-run frequency does not require adjust-
ment.
1
2
3
4
8
7
6
5
PHASE
COMP
H.OSC
SYNC
SEPA
V.SEPA
Block diagram
Absolute maximum ratings (Ta = 25C)
Parameter
Symbol
Limits
Unit
8.0
V
350
mW
C
C
V
CC Max.
Pd
Topr
Tstg
20 ~ + 75
55 ~ + 125
Power supply voltage
Power dissipation
Operating temperature
Storage temperature
When mounted on a 50mm
50mm PCB, reduced by 3.5mW for each increase in Ta of 1
C over 25
C.
Recommended operating conditions (Ta = 25C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
V
CC
4.5
--
5.5
V
Operating power supply voltage
2
Multimedia ICs
BA7062F
V
CC
1pin
1k
12k
100
A
Fig. 1
2pin
V
CC
200
5k
Fig. 2
3pin
200
Fig. 3
V
CC
4pin
200
10k
Fig. 4
V
CC
6pin
100
10
A
Fig. 5
V
CC
8pin
1k
3k
3k
3k
3k
3k
3k
Fig. 6
Input / output circuits
Pin descriptions
Pin No.
1
2
H
D
3
4
V
D
5
6
7
8
Horizontal oscillator resistor
H
D
output
SYNC output (open collector)
V
D
output
GND
Video input
Power supply
Phase comparator output
Function
3
Multimedia ICs
BA7062F
Electrical characteristics (unless otherwise noted, Ta = 25C and V
CC
= 5V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
I
Q
2.0
4.1
6.2
mA
V
syn-Min.
--
0.08
0.15
V
P-P
V
P-L
--
0.1
0.3
V
V
P-H
4.7
4.9
--
V
f
H-O
13.9
15.7
17.5
kHz
2.1
2.9
--
--
kHz
T
HPH
1.0
0
+ 1.0
s
T
HD
10.5
11.5
12.5
s
T
VD
200
260
320
s
f
CAP
Quiescent current
Minimum SYNC separation level
Pulse voltage, Low
Pulse voltage, High
Capture range
Lock-in phase
H
D
pulse width
V
D
pulse width
Conditions
2pin
4pin
2pin
6pin
Pin 3 open
Pin 6 terminated with 75
resistor
2, 4 pin
2, 4 pin
No input signal, I
1
= open
Not designed for radiation resistance.
(Horizontal)
free-running frequency
Measurement circuit
8
7
6
5
1
2
3
4
I
I
100p
130k
V
T
V
T
V
T
1
1
1
75
Video In
+
+
+
A
47
0.022
39k
V
CC
2200p
470k
10k
V
CC
Fig. 7
Circuit operation
(1) Synchronization separation circuit
Detects the charging current to a externally-connected
capacitor, and performs synchronization separation.
(2) Horizontal oscillation circuit
When a video signal is input, it is synchronized with
Hsync by the PLL. The horizontal free-running frequen-
cy is determined by external resistor R
1
.
(3) Vertical synchronization separation circuit
When a video signal is input, synchronization signal
separation is done over the vertical synchronization
pulse interval.
f
H-O
= [kHz]
2.05E6
R
1
4
Multimedia ICs
BA7062F
NTSC signal
Odd-number field
(IN)
(OUT)
Vertical synchronizing pulse interval
V
D
1 / 2H
NTSC signal
Even field (IN)
H
D
Odd field (OUT)
H
D
Even field (OUT)
(1) The rise and fall positions for V
D
are basically the same for both odd and even fields.
(2) H
D
shifts by 1 / 2H during the odd and even field interval.
Fig. 8
V
IN
, H
D
, and V
D
timing charts
5
Multimedia ICs
BA7062F
Application example
(1) Connect pin 1 to GND via a 120k
(approx.) resistor. Leave pins 2, 4 and 8 open.
(2) SYNC output polarity (pin 3) is positive.
(3) The delay time for rising edge of the SYNC output (pin 3) with respect to the falling edge of Sync for the Vsig
input signal (pin 6) is 850ns (reference value).
(4) The delay time for falling edge of the SYNC output (pin 3) with respect to the rising edge of Sync for the Vsig
input signal (pin 6) is 450ns (reference value).
Attached components
Resistor R
1
should have a tolerance of 2%, and a temperature coefficient of 100ppm or lower.
When SYNC SEPA output only is used. H
D
and V
D
unused.
Fig. 9
100p
C
4
R
1
R
2
470k
130k
10k
V
D
SYNC
H
D
H.OSC
PHASE
COMP
SYNC
SEPA
8
7
6
1
2
3
4
C
3
10k
1
R
3
C
2
+
2200p
C
5
C
6
47
0.022
+
C
7
C
1
R
4
330
1
R
5
470k
+
+
+
5
V.SEPA
V
sig
V
CC
= 5V
V
CC
= 5V
470k
R
2
R
3
10k
8
C
2
C
3-2
0.47
C
3-1
0.47
2200p
1
000p
V
CC
By configuring the circuit enclosed in the dotted line to that in the
diagram on the right, you can decrease the lock-in time and increase
the capture range.
R
1
120k
10k
V
D
SYNC
H
D
H.OSC
PHASE
COMP
SYNC
SEPA
8
7
6
1
2
3
4
C
5
C
6
47
0.022
+
C
7
C
1
R
4
330
1
R
5
470k
+
5
V.SEPA
V
sig
V
CC
= 5V
V
CC
= 5V
Fig. 10
1000p
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