K4C89093AF
REV. 0.2 Aug. 2003
- 2 -
Target
Revision History
Version 0.0 (Nov. 2002)
- First Release
Version 0.1 (Apr. 2003)
- Added 800Mbps(400Mhz) product
- Changed operating temperature from Ta to Tc.
- Changed capacitance of ADDR/CMD/CLK
- Changed tDSS(DS input Falling Edge to Clock Setup Time)
- Added CL7 for 800Mbps
- Deleted TSOP package outline
Version 0.11 (Apr. 2003)
- Corrected typo in page 3.(Deleted bi-directional strobe)
- Corrected min. Vref to VDDQ/2x95% in page 7
Version 0.2 (Jul. 2003)
- Changed ballout
- Added physical package dimension
- Extracted 800Mbps(G7) binning from target spec ( G7 will be added in the future)
- Changed DC test condition
- Changed low frequency spec like below
- Changed AC test load picture
From
To
Min
Max
Min
Max
Addr/CMD/CLK
1.5
2.5
1.5
3.0
From
To
F6
FB
F5
G7
F6
FB
F5
CL4
0.9
0.9
1.0
0.75
0.75
0.8
1.0
CL5
0.9
0.9
1.0
0.75
0.75
0.8
1.0
CL6
0.9
0.9
1.0
0.75
0.75
0.8
1.0
CL7
-
-
-
0.75
-
-
-
From
To
Changed point
IDD1S,IDD2N,IDD2P,IDD5,IDD6
IDD1S,IDD2N,IDD2P,IDD5B,IDD6
Changed condition
-
IDD4W, IDD4R
newly inserted
From
To
Unit : ns
F6
FB
F5
F6
FB
F5
tCK max@CL=4
7.5
7.5
7.5
6.0
6.0
6.0
tCK max@CL=5
7.5
7.5
7.5
6.0
6.0
6.0
tCK max@CL=6
7.5
7.5
7.5
6.0
6.0
6.0
K4C89093AF
REV. 0.2 Aug. 2003
- 3 -
Target
8,388,608-WORDS x 4 BANKS x 9-BITS DOUBLE DATA RATE Network-DRAM
DESCRIPTION
K4C89093AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells. K4C89093AF is organized as
8,388,608-words x 4 banks x9 bits. K4C89093AF feature a fully synchronous operation referenced to clock edge whereby all operations
are synchronized at a clock input which enables high performance and simple user interface coexistence. K4C89093AF can operate
fast core cycle compared with regular DDR SDRAM.
K4C89093AF is suitable for Server, Network and other applications where large memory density and low power consumption are
required. The Output Driver for Network-DRAM is capable of high quality fast data transfer under light loading condition.
FEATURES
Fully Synchronous Operation
- Double Data Rate (DDR)
- Data input/output are synchronized with both edges of DS / QS.
- Differential Clock (CLK and CLK) inputs
- CS, FN and all address input signals are sampled on the positive edge of CLK.
- Output data (DQs and QS) is aligned to the crossings of CLK and CLK.
Fast clock cycle time of 3.0 ns minimum
- Clock : 333 MHz maximum
- Data : 666 Mbps/pin maximum
Quad Independent Banks operation
Fast cycle and Short Latency
Uni-directional data Strobe
Distributed Auto-Refresh cycle in 3.9us
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency = CAS Latency-1
Programable CAS Latency and Burst Length
- CAS Laatency = 4, 5, 6
- Burst Length = 2,4
Organization : 8,388,608 words x 4 banks x 9 bits
Power Supply Voltage V
DD
: 2.5V
0.125V
V
DDQ
: 1.4V
1.9V
1.8V CMOS I/O comply with SSTL - 1.8 (half strength driver) and HSTL
Package : 60Ball BGA, 1mm x 1mm Ball pitch
Notice : Network-DRAM is trademark of Samsung Electronics., Co LTD
Parameter
K4C89093AF
F6
FB
F5
t
CK
Clock Cycle Time (min)
CL = 4
4.0 ns
4.5 ns
5.0 ns
CL = 5
3.33 ns
3.75 ns
4.5 ns
CL = 6
3.0ns
3.33 ns
4.0 ns
t
RC
Random Read/Write Cycle Time (min)
20.0 ns
22.5 ns
25 ns
t
RAC
Random Access Time (min)
20.0 ns
22.5 ns
25 ns
I
DD1S
Operating Current (single bank) (max)
TBD
TBD
TBD
I
DD2S
Power Down Current (max)
TBD
TBD
TBD
I
DD3S
Self-Refresh Current (max)
TBD
TBD
TBD
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