Revision 0.0
CMOS SRAM
April 2005
K6F2016R4G Family
- 1 -
Preliminary
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2Mb(128K x 16 bit) Low Power SRAM
Revision 0.0
CMOS SRAM
April 2005
K6F2016R4G Family
- 2 -
Preliminary
Document Title
128K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No.
0.0
Remark
Preliminary
History
Initial draft
Draft Date
April 25, 2005
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 0.0
CMOS SRAM
April 2005
K6F2016R4G Family
- 3 -
Preliminary
128K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
48-FBGA: Top View (Ball Down)
LB
OE
A0
A1
A2
DNU
I/O9
UB
A3
A4
CS
I/O1
I/O10
I/O11
A5
A6
I/O2
I/O3
Vss
I/O12
DNU
A7
I/O4
Vcc
Vcc
I/O13
DNU
A16
I/O5
Vss
I/O15
I/O14
A14
A15
I/O6
I/O7
I/O16
DNU
A12
A13
WE
I/O8
DNU
A8
A9
A10
A11
DNU
1
2
3
4
5
6
A
B
C
D
E
F
G
H
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice
.
Name
Function
Name
Function
CS
Chip Select Input
Vcc
Power
OE
Output Enable Input
Vss
Ground
WE
Write Enable Input
UB
Upper Byte(I/O
9
~
16
)
A
0
~A
16
Address Inputs
LB
Lower Byte(I/O
1
~
8
)
I/O
1
~I/O
16
Data Inputs/Outputs
DNU
Do Not Use
Precharge circuit.
Memory
Cell
Array
I/O Circuit
Column select
Clk gen.
Row
select
WE
OE
UB
CS
I/O
1
~I/O
8
Data
cont
Data
cont
Data
cont
LB
I/O
9
~I/O
16
Vcc
Vss
Row
Addresses
Control Logic
Column Addresses
PRODUCT FAMILY
1. The parameter is measured with 30pF test load.
2. Typical values are measured at V
CC
=1.8V, T
A
=25
C and not 100% tested.
Product Family
Operating Temperature
Vcc Range
Speed
Power Dissipation
PKG Type
Standby
(I
SB1
, Typ.)
Operating
(I
CC1
, Max)
K6F2016R4G-F
Industrial(-40~85
C)
1.65~1.95V
70
1)
/85ns
0.5
A
2)
2mA
48-FBGA-6.00x7.00
GENERAL DESCRIPTION
The K6F2016R4G families are fabricated by SAMSUNG
s
advanced full CMOS process technology. The families support
industrial temperature range and 48 ball Chip Scale Package
for user flexibility of system design. The family also supports
low data retention voltage for battery back-up operation with
low data retention current.
FEATURES
Process Technology: Full CMOS
Organization: 128K x16 bit
Power Supply Voltage: 1.65~1.95V
Low Data Retention Voltage: 1.0V(Min)
Three State Outputs
Package Type: 48-FBGA-6.00x7.00
Revision 0.0
CMOS SRAM
April 2005
K6F2016R4G Family
- 4 -
Preliminary
FUNCTIONAL DESCRIPTION
1. X means don
t care. (Must be low or high state)
CS
OE
WE
LB
UB
I/O
1~8
I/O
9~16
Mode
Power
H
X
1)
X
1)
X
1)
X
1)
High-Z
High-Z
Deselected
Standby
X
1)
X
1)
X
1)
H
H
High-Z
High-Z
Deselected
Standby
L
H
H
L
X
1)
High-Z
High-Z
Output Disabled
Active
L
H
H
X
1)
L
High-Z
High-Z
Output Disabled
Active
L
L
H
L
H
Dout
High-Z
Lower Byte Read
Active
L
L
H
H
L
High-Z
Dout
Upper Byte Read
Active
L
L
H
L
L
Dout
Dout
Word Read
Active
L
X
1)
L
L
H
Din
High-Z
Lower Byte Write
Active
L
X
1)
L
H
L
High-Z
Din
Upper Byte Write
Active
L
X
1)
L
L
L
Din
Din
Word Write
Active
PRODUCT LIST
1. LF : Lead Free Product
Industrial Temperature Products(-40~85
C)
Part Name
Function
K6F2016R4G-FF70
K6F2016R4G-XF70
K6F2016R4G-FF85
K6F2016R4G-XF85
48-FBGA, 70ns, 1.8V
48-FBGA, 70ns, 1.8V, LF
1)
48-FBGA, 85ns, 1.8V
48-FBGA, 85ns, 1.8V, LF
1)
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Ratings
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-0.2 to V
CC
+0.3V(Max. 2.6V)
V
Voltage on Vcc supply relative to Vss
V
CC
-0.2 to 2.6
V
Power Dissipation
P
D
1.0
W
Storage temperature
T
STG
-65 to 150
C
Operating Temperature
T
A
-40 to 85
C
Revision 0.0
CMOS SRAM
April 2005
K6F2016R4G Family
- 5 -
Preliminary
RECOMMENDED DC OPERATING CONDITIONS
1)
Note:
1. Industrial Product: T
A
=-40 to 85
C, otherwise specified.
2. Overshoot: Vcc+1.0V in case of pulse width
20ns.
3. Undershoot: -1.0V in case of pulse width
20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
1.65
1.8
1.95
V
Ground
Vss
0
0
0
V
Input high voltage
V
IH
1.4
-
Vcc+0.2
2)
V
Input low voltage
V
IL
-0.2
3)
-
0.4
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
DC AND OPERATING CHARACTERISTICS
1. Typical value are measured at V
CC
=1.8V, T
A
=25
C and not 100% tested.
Item
Symbol
Test Conditions
Min
Typ
1)
Max
Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS=V
IH
or OE=V
IH
or WE=V
IL
or LB=UB=V
IH
,
V
IO
=Vss to Vcc
-1
-
1
A
Average operating current
I
CC1
Cycle time=1
s, 100%duty, I
IO
=0mA, CS
0.2V,
LB
0.2V or/and UB
0.2V, V
IN
0.2V or V
IN
V
CC
-0.2V
-
-
2
mA
I
CC2
Cycle time=Min, I
IO
=0mA, 100% duty, CS=V
IL
,
LB=V
IL
or/and UB=V
IL
, V
IN
=V
IL
or V
IH
85ns
-
-
12
mA
70ns
-
-
15
Output low voltage
V
OL
I
OL
= 0.1mA
-
-
0.2
V
Output high voltage
V
OH
I
OH
= -0.1mA
1.4
-
-
V
Standby Current (CMOS)
I
SB1
Other input =0~Vcc
1) CS
Vcc-0.2V(CS controlled) or
2) LB=UB
Vcc-0.2V, CS
0.2V(LB/UB controlled)
-
0.5
8
A
Revision 0.0
CMOS SRAM
April 2005
K6F2016R4G Family
- 6 -
Preliminary
AC CHARACTERISTICS
( T
A
=-40 to 85
C, Vcc=1.65~1.95V )
Parameter List
Symbol
Speed Bins
Units
70ns
85ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
70
-
85
-
ns
Address access time
t
AA
-
70
-
85
ns
Chip select to output
t
CO
-
70
-
85
ns
Output enable to valid output
t
OE
-
35
-
40
ns
UB, LB Access Time
t
BA
-
70
-
85
ns
Chip select to low-Z output
t
LZ
10
-
10
-
ns
UB, LB enable to low-Z output
t
BLZ
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
ns
Chip disable to high-Z output
t
HZ
0
25
0
25
ns
UB, LB disable to high-Z output
t
BHZ
0
25
0
25
ns
Output disable to high-Z output
t
OHZ
0
25
0
25
ns
Output hold from address change
t
OH
10
-
10
-
ns
Write
Write cycle time
t
WC
70
-
85
-
ns
Chip select to end of write
t
CW
60
-
70
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
60
-
70
-
ns
UB, LB Valid to End of Write
t
BW
60
-
70
-
ns
Write pulse width
t
WP
50
-
60
-
ns
Write recovery time
t
WR
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
20
0
25
ns
Data to write time overlap
t
DW
30
-
35
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to V
CC
-0.2V
Input rising and falling time: 5ns
Input and output reference voltage:0.9V
Output load (See right): C
L
= 30pF+1TTL
C
L
1)
1. Including scope and jig capacitance
R
2
2)
R
1
2)
V
TM
3)
2. R
1
=3070
,
R
2
=3150
3. V
TM
=1.8V
DATA RETENTION CHARACTERISTICS
1.
1) CS
Vcc-0.2V(CS controlled) or
2) LB=UB
Vcc-0.2V, CS
0.2V(LB/UB controlled)
2. Typical value are measured at T
A
=25
C and not 100% tested.
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
VDR
CS
Vcc-0.2V
1)
, V
IN
0V
1.0
-
1.95
V
Data retention current
IDR
Vcc=1.2V, CS
Vcc-0.2V
1)
, V
IN
0V
-
0.5
2)
3
A
Data retention set-up time
tSDR
See data retention waveform
0
-
-
ns
Recovery time
tRDR
tRC
-
-
Revision 0.0
CMOS SRAM
April 2005
K6F2016R4G Family
- 7 -
Preliminary
Address
Data Out
Previous Data Valid
Data Valid
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
, UB or/and LB=V
IL
)
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
t
RC
CS
Address
UB, LB
OE
Data out
t
AA
t
RC
t
OH
t
OH
t
AA
t
CO
t
BA
t
OE
t
OLZ
t
BLZ
t
LZ
t
OHZ
t
BHZ
t
HZ
NOTES (READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
Revision 0.0
CMOS SRAM
April 2005
K6F2016R4G Family
- 8 -
Preliminary
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS Controlled)
Address
CS
Data Valid
UB, LB
WE
Data in
Data out
High-Z
High-Z
t
WC
t
CW(2)
t
AW
t
BW
t
WP(1)
t
DH
t
DW
t
WR(4)
t
AS(3)
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
Address
CS
Data Undefined
UB, LB
WE
Data in
Data out
t
WC
t
CW(2)
t
WR(4)
t
AW
t
BW
t
WP(1)
t
AS(3)
t
DH
t
DW
t
WHZ
t
OW
High-Z
High-Z
Data Valid
Revision 0.0
CMOS SRAM
April 2005
K6F2016R4G Family
- 9 -
Preliminary
Address
CS
Data Valid
UB, LB
WE
Data in
Data out
High-Z
High-Z
TIMING WAVEFORM OF WRITE CYCLE(3)
(UB, LB Controlled)
NOTES
(WRITE CYCLE)
1. A wri
t
e occurs during the overlap(t
WP
) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition
when CS goes high and WE goes high. The
t
WP
is measured from the beginning of write to the end of write.
2.
t
CW
is measured from the CS going low to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4.
t
WR
is measured from the end of write to the address change.
t
WR
applied in case a write ends as CS or WE going high.
t
WC
t
CW(2)
t
BW
t
WP(1)
t
DH
t
DW
t
WR(4)
t
AW
t
AS(3)
DATA RETENTION WAVE FORM
CS or LB/UB controlled
V
CC
1.65V
1.4V
V
DR
CS or LB/UB
GND
Data Retention Mode
CS
V
CC
-0.2V or LB=UB
Vcc-0.2V
t
SDR
t
RDR
Revision 0.0
CMOS SRAM
April 2005
K6F2016R4G Family
- 10 -
Preliminary
C1/2
PACKAGE DIMENSION
6
5
4
3
2
1
A
B
C
D
E
F
G
H
C
B/2
B
C1
B
C
Bottom View
Top View
Side View
0.5
8
/T
yp
.
0
.
32/T
y
p.
A
Y
Detail A
B1
#A1
Notes.
1. Bump counts: 48(8 row x 6 column)
2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
4. Typ: Typical
5. Y is coplanarity: 0.10(Max)
Unit: millimeters
48 TAPE BALL GRID ARRAY(0.75mm ball pitch)
D
E1
E
C
Min
Typ
Max
A
-
0.75
-
B
5.90
6.00
6.10
B1
-
3.75
-
C
6.90
7.00
7.10
C1
-
5.25
-
D
0.40
0.45
0.50
E
-
1.00
E1
0.25
Y
-
-
0.10
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