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ELECTRONICS

MULTIMEDIA VIDEO

S5D2650 Data Sheet

PAGE 1 OF 95

7/18/03

MULTISTANDARD VIDEO DECODER/SCALER

The S5D2650 converts analog NTSC, PAL or SECAM
video in composite, S-video, or component format to
digitized component video. Output data can be selected for
CCIR 601 or square pixel sample rates in either YCbCr or
RGB formats. The digital video can be scaled down in both
the horizontal and vertical directions. The S5D2650 also
decodes Intercast, Teletext, Closed Caption, and SMPTE
data with a built-in bit data slicer. Digitized CVBS data can
be output directly during VBI for external processing.

FEATURES

· Accepts NTSC-M/N/4.43, PAL-M/N/B/G/H/I/D/K/L and

SECAM formats with auto detection

· 6 analog inputs: 2 S-video, 4 composite, or 2 3-wire

YPbPr component video

· YPbPr Progressive input support(720x480p)

· 3-line luma and chroma comb filters including

adaptive luma comb for NTSC

· Programmable luma bandwidth, contrast,

brightness, and edge enhancement

· Programmable chroma bandwidth, hue, and

saturation

· High quality horizontal and vertical down scaler

· Intercast, Teletext and Closed Caption decoding with

built-in bit slicer

· Direct output of digitized CVBS during VBI for

Intercast application

· Analog square pixel or CCIR 601 sample rates

· Output in 4:4:4, 4:2:2, or 4:1:1 YCbCr component, or

24-bit or 16-bit RGB formats with dithering

· YCbCr 4:2:2 output can be 8 or 16 bits wide with

embedded timing reference code support for 8-bit
mode

· Simultaneous scaled and non-scaled digital output

ports outputs for 8-bit mode.

· Direct access to scaler via bi-directional digital port.

· Programmable Gamma correction table

· Programmable timing signals

· Industry standard IIC interface

100 PQFP

ORDERING INFORMATION

Device

Package

Temperature Range

S5D2650

100 PQFP

0°~+70°C

APPLICATIONS

· Multimedia

· Digital Video

· Video Capture/Editing

· LCD-TV

· Surveillance system

RELATED PRODUCTS

· KS0123 MULTISTANDARD VIDEO ENCODER

· KS0125 MULTISTANDARD VIDEO ENCODER

· KS0127B VIDEO DECODER

ELECTRONICS

S5D2650 Data Sheet

MULTIMEDIA VIDEO

PAGE 2 OF 95

7/18/03

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ELECTRONICS

S5D2650 Data Sheet

MULTIMEDIA VIDEO

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7/18/03

PIN ASSIGNMENT - 100 PQFP

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ELECTRONICS

S5D2650 Data Sheet

MULTIMEDIA VIDEO

PAGE 4 OF 95

7/18/03

PIN DESCRIPTI O N

Pin Name

Pin #

Type

Description

ANALOG PINS, Reference CLOCK and RESET

AY0

1 of 4 CVBS or 1of 2 S-video Y inputs or 1of 2 component Y inputs.

AY1

1 of 4 CVBS or 1of 2 S-video Y inputs or 1of 2 component Y inputs.

ACR0

1 of 4 CVBS input or 1 of 2 component Pr input

ACR1

1 of 4 CVBS input or 1 of 2 component Pr input

ACB0

1 of 2 S-video C inputs or 1 of 2 component Pb input

ACB1

1 of 2 S-video C inputs or 1 of 2 component Pb input

COMP2

Internal 1.3 V reference (requires an external 0.1

F capacitor

connected to VSS).

FILT

Loop filter output for PLL

XTALI

Crystal or TTL clock input.(24.576MHz or 26.8MHz)

XTALO

Crystal output.

RSTB

Chip reset. Active low signal.(5V tolerant Input Pin)

INPUT, OUTPUT and Bi-Directional Pins (All output pins can be selectively tri-stated)

Y0 - Y7, C0 - C7 45-48,53-56,33-

39,44

Y[7:0] : Y outputs for CCIR601 or Green out for 24 Bit RGB mode.
C[7:0] : Cb/Cr outputs for CCIR601 or Blue out for 24 Bit RGB mode.

EXV0 - EXV7

16,27,28,61-63,
68,71

I/O

Expanded digital video I/O port. Red data out for 24 Bit RGB mode
or 8 Bit input of CCIR 656 input mode.

HS1

I/O

Programmable horizontal sync signal. When the EXV port is
configured as an input, this pin can be programmed as an input.
(default : Output)

HS2

Programmable horizontal sync signal. (Same as HS1)

I/O

Programmable vertical sync signal. When the EXV port is configured
as an input, this pin can be programmed as an input.
(default : Output)

HAV

Programmable horizontal active video signal.

VAV

Programmable vertical active video signal.

EHAV

Valid pixel data flag for horizontal scale down. Active when output
video data is valid.

EVAV

Valid line data flag for vertical scale down. Active when output video
line is valid.

ODD

Odd field flag. Polarity is programmable.

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S5D2650 Data Sheet

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7/18/03

PID

PAL ID flag. Pahse Alternate Line flag

OEN

Output data, timing and clock 3-state output control.
(Default : tied to VDD)

I/O

System clock. (Default : 27MHz output. When the EXV port is used
as an input, this can be programmed as an input system clock.)

CK2

Pixel rate output clock (Default : 13.5 MHz)

CCDAT

Sliced VBI data output. Data can be from Closed Caption, Teletext,
Intercast, or WSS type encoded data.

CCEN

When high, this pin indicates that valid VBI data is being clocked out
at the CCDAT pin or at the digital video output.

MULTI-PURPOSE I/O PORTS

PORTA

I/O

Multi-purpose I/O portA.

PORTB(SCH)

I/O

Multi-purpose I/O portB.

HOST INTERFACE

SCLK

Serial clock for IIC host interface. (5V tolerant schmitt trigger pin)

SDAT

I/O

Serial data for IIC host interface.(5V tolerant schmitt triggered open
drain Pins)

AEX0 - AEX1

69 - 70

Device ID selection for IIC host interface.

POWER AND GROUND

VDD3

9,20,59

3.3V

Digital power supply for input, output buffers.

VDD1

11,12,42,43,66,
67

1.8V

Digital power supply for core logic.

VDDA

85,89,93

3.3V

Analog power supply for ADC, AGC and reference circuits.

VDDP

3.3V

Analog power supply for clock generation circuit(PLL).

VSS

1,2,6,13,14,19,
40,41,49-52,60,
64,65,77-80,
81-83,87,91,95,
96

GND Common ground.

VSSP

100

GND Common ground for PLL.

PIN DESCRIPTION (Continued)

Pin Name

Pin #

Type

Description

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S5D2650 Data Sheet

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PAGE 6 OF 95

7/18/03

TEST

TEST0

Test pin 0. For normal use, this pin should be connected to VSS.

TEST1

Test pin 1. For normal use, this pin should be connected to VSS.

TEST2

Test pin 2. For normal use, this pin should be connected to VSS.

SCANEN

SCAN Mode Test pin.For normal use, this pin should be connected
to VSS.

CKE

For Test TBC function. For normal use, this pin should be connected
to VSS.

PIN DESCRIPTION (Continued)

Pin Name

Pin #

Type

Description

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S5D2650 Data Sheet

MULTIMEDIA VIDEO

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7/18/03

PIN CROSS REFERENCE: NUMERICAL ORDER BY PIN NUMBER

Pin #

Pin Name

Pin #

Pin Name

Pin #

Pin Name

Pin #

Pin Name

VSS

HS1

VSS

HS2

VSS

EXV1

VSS

VAV

EXV2

VSS

EVAV

TEST0

VSS

EHAV

TEST1

VSS

SCANEN

VSS

XTALI

CKE

TEST2

VSS

XTALO

PORTA

VSS

VDD3

AY0

RST

VSS

VDDA

VDD1

EXV3

AY1

VDD1

EXV4

VSS

EXV5

ACR0

VSS

VDDA

OEN

VSS

ACR1

EXV0

VSS

VDD1

VSS

PID

VDD1

ACB0

VDD1

EXV6

VDDA

VSS

AEX0

ACB1

VDD3

AEX1

VSS

CK2

EXV7

VSS

ODD

SDAT

COMP2

CCDAT

VDDP

PORTB(SCH)

VSS

CCEN

FILT

HAV

VSS

SCLK

100

VSSP

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S5D2650 Data Sheet

MULTIMEDIA VIDEO

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1. FUNCTIONAL DESCRIPTION

1.1. VIDEO INPUT

The S5D2650 supports complete video decoding of many analog video standards. In addition, the chip can support
direct 8-bit YCbCr input for high quality video scaling and other processing.

1.1.1. Analog Video Input

Figure 1 shows the detailed block diagram of the analog front end. Up to four composite video sources, two
S-video sources, two 3-wire YPbPr component video source, or any combination can be selected. The allowed
inputs are selected using the INSEL[2:0] bits in the CMDB register. Table 1 lists all possible input selections. The
front end has three paths each containing an analog gain control, a clamping control, and an 8-bit ADC. Composite
video input uses only the luma path. The ADC digital data is used to calculate the correct gain and clamp values.
The data is

feedback to the analog clamping and gain control. This architecture eliminates any offset and gain

mismatch in the analog front end.

Figure 1. Analog Front End

The analog inputs must be AC coupled through an external 0.1 mF capacitor clamp. Due to the high sampling rate
of the ADC's inside the S5D2650, most video sources will not require a low-pass filter for alias reduction. For those
video sources with harmonics above 13 MHz, a simple single order pole at 6 MHz will provide sufficient high

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ELECTRONICS

S5D2650 Data Sheet

MULTIMEDIA VIDEO

PAGE 9 OF 95

7/18/03

frequency signal reduction. This can be implemented with a 400 pF capacitor in parallel with the 75

load.

Figure 2. Typical Analog Video Input

1.1.2. Digital AGC Control

The AGC normally references to the ADC code difference between sync tip and back porch. Two sets of sync
tip-back porch ADC values are available for different AGC gain requirements: if AGCGN = 0, the sync tip locks to
code 2, and the back porch locks to code 70; when AGCGN = 1, the sync tip locks to 16, and the back porch locks
to code 70. Video signal with abnormal sync tip or very bright saturated colors may cause the ADC to limit the
maximum value. This situation can be corrected by enabling the AGCOVF bit in the CMDB register to force the
gain tracking loop to reduce AGC when maximum limiting conditions occur. The AGC may also be programmed to
freeze the AGC at the current value by setting the AGCFRZ bit in the CMDB register. Once the AGC is frozen, the
gain can be manually adjusted with the AGC register. The tracking time constant for the AGC can be controlled
with the AGC_LPG[1:0] bits in the TRACKB register. In addition, the AGC tracking time constant can be
configured as 2X faster during acquisition via the AGC_LKG.

1.1.3. Digital Video Input

The high quality digital video down scaler in the S5D2650 can be directly accessed via the EXV bi-directional port.
The S5D2650 accepts CCIR 656 compliant 8-bit YCbCr digital video input with embedded or external HS, VS
timing. Video timing may also be generated by the S5D2650. Data path for 8-bit YCbCr input is shown in Figure 3.
Selection of analog video input or digital CCIR 656 data is with the INPSL[1:0] register bits.

Table 1: Analog Video Input selections

INSEL[2:0](hex)

Selected Input(s)

Video Type

AY0

Composite

AY1

Composite

ACR0

Composite

ACR1

Composite

AY0,ACB0

S-Video

AY1,ACB1

S-Video

AY0,ACB0,ACR0

YPbPr component video

AY1,ACB1,ACR1

YPbPr component video

0.1

Analog
Video

S5D2650

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S5D2650 Data Sheet

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7/18/03

1.1.4. Pixel Clock and Timing Mode Selection for Digital Video Input

Pixel clock and synchronization timing can be individually selected to either come from an external generator or be
generated internally. In addition, if synchronization is provided by an external source, the S5D2650 supports
embedded syncs as defined in CCIR 656, or TTL HS and VS inputs. Selection of pixel clock is via CKDIR bit in
CMDD register. Timing selection is through either SYNDIR or EAV bit.

Figure 3. 8-bit YCbCr Input Data Path

By using an external pixel clock, the reference clock input at XTALI is no longer required. Additional register bits
have to be programmed for different selections of pixel clock and timing, which are detailed in Table 2. The
following register/bit-settings are required for digital video input:

INSEL[2:0] = 6,7 TSTCGN = 1. DMCTL[1:0] = 2 or 3. UGAIN = 238.
BRT = 34. SAT = 229. RGBH = UNIT = PED = 1.

Table 2: Digital Video Input Pixel Clock and Timing Selection

Pixel Clock TTL Timing

Embedded

Timing

Additional Register Programming

CKDIR

SYNDIR

EAV

VMEN

TSTGPH TSTGEN TSTGFR

PIXSEL

MNFMT

IFMT

0 if input
data is at
square
pixel
rate.
1 if input
is at
CCIR
601 rate.

0 if input
is 50 Hz
video.
1 if input
is 60 Hz
video.

: CKDIR = 0 - CK is output and is internally generated. CKDIR = 1 - CK is input from an external source.

: SYNDIR = 0 - HS1 and VS are output. SYNDIR = 1 - HS1 and VS are inputs from external sources.

: EAV = 0 - chip will not sync to embedded timing. EAV = 1 - chip will sync to embedded timing.

HS1
VS

EXV[7:0]

Timing
Control

Data
Demux

Luma
Processing

Chroma
Processing

From Luma ADC

From Cb/Cr ADC

To Luma Scaler

To Chroma Scaler

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When in digital input mode, all programmable timing registers (such as HAVB,HAVE, HS2B etc.) are still functional.
If HS1 and VS are programmed as inputs, the associated output timing controls such as HS1B,E will have no
effect. An example of horizontal timing for digital input is shown in Figure 4.

Figure 4. Horizontal Timing for EXV Port as Digital Input

1.1.5. Additional Information for Analog Component Video Input

For the S5D2650 to correctly set the V component phase in PAL mode analog component video input mode,
PORTA (pin 58) need to be connected VSS. PORTA has to be configured as input (DIRA = 0) and connected to the
internal CBG signal (DATAA[2:0] = 3). Also S5D2650 supports progressive analog component input.

The following registers are required for analog component video input:

INSEL[2:0] = 6,7 PROG = 0(interlace), 1(progressive).
DATAA[2:0] = 3. CKILL[1:0] = 2. CDMLPF = 1.
SAT[7:0] = 79.
MNYCMB = 1. YCMBCO[2:0] = 4.
TSTCGN = 1. UOFFST[5:4] = VOFFST[5:4] = 3.
UOFFST[3:0] = C. VOFFST[3:0] = 2. VGAIN[7:0] = 1D. DMCTL[1:0] = 2 or 3

80 10 80 10 80 10 U

HAV

CK2

HS1

80 10 80 10 80 10 U

Programmable, when an

Fully programmable HAVB location

HAV -- fully programmable,
Defines location of first, last pixel
and defines Cb,Y,Cr data location

Data group delay through chip --

EXV[7:0]

output - Any input phase
is acceptable

Constant to internal counter reference

based on internal counter

Fully programmable

HAVE location

The CK2 output clock phasing
is aligned to the HAV leading
edge

CK can be input or output

This HS1 location can also come
From a 656 SAV code

Y[7:0]

Y output for OFMT=2 is
shown, any 8 or 16 bit
output format is allowed.

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1.2. VIDEO TRACKING AND TIMING GENERATION

When the S5D2650 is configured for analog video input, the chip tracks the video input and generates a sampling
clock that is line locked to the input video. The S5D2650 requires an external reference clock for video tracking.
This reference can be supplied via a crystal using the on chip crystal interface or any TTL compatible source.
These configurations are shown in Figure 5

1.2.1. Clock Input Timing Reference

The S5D2650 can use either a 24.576 MHz or a 26.8 MHz reference. However, it is recommended that the 24.576
MHz reference be used for CCIR 601 operation, and the 26.8 MHz reference be used for square pixel or dual mode
operation. Other specifications for the crystal are:

· Fundamental or third overtone

· Load capacitance of ~20 pF

· Series resistance of 40

or less

· Frequency deviation of 50 ppm or less over operating temperature range

Figure 5. Standard Clock Configurations

1.2.2. The Sampling Clock

The sampling clock is generated by multiplying the line rate by N. This ensures that samples are aligned
horizontally, vertically and in time. The required N factor for the S5D2650 is based upon the field rate (60 Hz or 50
Hz) and the desired sampling rates (CCIR 601 or square pixel). Field rate can be automatically detected and can
be monitored with the FFRDET bit in the STAT register. Manual control of the field rate can be controlled with the
MNFMT and IFMT bits. The PIXSEL bit in register CMDA

selects CCIR 601 or square pixel. Table 3 shows the

constants for the various combinations of input formats and output pixel rates.

Using a Crystal

S5D2650

Using a Clock

24.576 MHz
TTL Clock

24.576 MHz

22 pF

N. C.

XTALI

XTALO

S5D2650

XTALI

XTALO

391 pF

5.7

Optional for 3rd
harmonic crystal

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S5D2650 Data Sheet

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The time constants for the pixel clock tracking loop can be adjusted with the HFSEL[1:0] bits.

In addition to providing the pixel clock, the S5D2650 also outputs various timing signals to indicate the beginning of
a line, a field, and for field and frame identification. All the timing and clock pins may be optionally put into high
impedance state. Tri-state of these pins are software controlled and initial state of these pins at power up is
controlled via two configuration pins: 3 and 4.

The S5D2650 can generate all the video timing without video input. This enables the S5D2650 to be used as a
video timing generator for a system that contains both the S5D2650 for live video input and a MPEG decoder
which requires a video timing generator.

1.2.3. Horizontal Timing

The S5D2650 creates many internal timing signals aligned to the horizontal sync tip (mid-way of the falling edge of
horizontal sync, typically ADC code 36). These include locations of color burst (CBG, CBGW) used in chrominance
processing, back porch (BPG), and sync tip timing signals (SLICE, FS_PULSE) used for AGC and clamp functions.
SLICE is low whenever the input is below half way level of horizontal sync (typically ADC code 36). FS_PULSE is
a single clock pulse coincide with the start of SLICE. One of these internal signals can be made available at the
PORTA or PORTB pin at any time.

The chip outputs two horizontal synchronization signals: HS1 and HS2. The start and stop locations for these
signals are fully programmable. Offset programmed to HSxB, HSxE, and HSxBE0 are added to the default edge
locations as shown in Table 4. Note that there are different modulo numbers for different input video standards and
output pixel rates

Table 3: Timing for Different Pixel Rates

CCIR 601 Data Rates

Square Pixel Data Rates

Units

N,B,G,H,I,D,K,K1,L

Field Rate

Pixels/Line (N)

858

864

780

944

Pixels

Active Pixels/Line

720

640

768

Pixels

Active Lines/Frame

480

580

480

580

Lines

Pixel Rate

13.5

12.27

14.75

MHz

ADC Sampling Rate

24.54

29.5

MHz

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An additional signal, HAV, is provided for horizontal video cropping. This signal has programmable polarity, start
and stop locations. Two 11-bit registers, HAVB and HAVE, are used to define the first and last pixel locations of the
horizontal portion of the cropped video. Numbers programmed into these registers are used as offset to the default
locations as shown in Table 4. Note that even though HAVB and HAVE have 1-CK resolution, the difference
between them should be maintained at multiple of 4 CKs for correct output.

Table 4 shows the default edge locations relative to the midway of the falling edge of the analog horizontal sync.
Note the numbers shown are in multiple of CK clocks. Figure 6 shows the approximate locations for the horizontal
timing signals.

Table 4: Horizontal Timing Signal Edge Locations (in # of CK)

Description

Signal

60 Hz

50 Hz

CCIR 601

(modulo 1716)

Square Pixel

(modulo 1560)

CCIR 601

(modulo 1728)

Square Pixel

(modulo 1888)

Chip delay

120

Sync gate (1-CK pulse)

SYG

Back porch gate

BPG

[157 232]

[139 214]

[164 244]

[178 264]

Color burst gate (1-CK pulse)

CBG

222

204

234

254

Wide color burst gate

CBGW

[159 254]

[147 233]

[173 254]

[186 277]

Two pulses per line (1-CK each
pulse)

FH2

40, 900

42, 822

42, 906

42, 986

Chrominance offset duration

COFF

[72 232]

[72 214]

[72 244]

[72 264]

Default horizontal sync(int.)

HS1

[24 222]

[24 204]

[24 234]

[24 254]

Default horizontal active(int.)

HAV

[293 17]

[276 0]

[321 33]

[357 1]

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Figure 6. Approximate Locations for the Horizontal Timing Signals

1.2.4. Vertical Timing

The vertical timing signals include VS, VAV, ODD, SCH, and PID.The VS is used for identifying the first line of video
in the vertical position. The VS leading edge can be programmed to either track the incoming video's serration
pulses or to be aligned to the beginning of the video line or half way, as shown in Figure 36 and Figure 37. If
VALIGN = 0, the VS leading edge is based on the output of an internal low pass filter, and its location is dependent
on the noise conditions of the video input. The trailing edge of VS is locked to either the beginning of the video line
or half way. The half way location relative to the beginning of the video line changes depending on current input
standard and output format. If VALIGN = 1, the leading edge of the VS is aligned to the beginning of the video line
or half way. The trailing edge is always aligned to the beginning of the video line. The VSE bit in the CMDA register
can be programmed to shorten the VS falling edge by one horizontal line.The VAV signal is used for vertical
cropping. The start and stop lines for VAV are programmable through the VAVB and VAVE registers,
respectively.The ODD signal signifies the current field number. When ODD is active, the current field is 1 or 3 (or 5
or 7 if in PAL mode). The leading and trailing edges of ODD can be aligned to either the leading edge of VS
(VALIGN = 1) or the trailing edge of VS (VALIGN = 0). The signal may be used in conjunction with SCH and PID to
exactly identify the current field. To distinguish between fields 1, 2 verse fields 3, 4 (or fields 1, 2, 3, 4 verse fields 5,
6, 7, 8 for PAL) the phase of the color burst relative to the sync tip must be measured. That information is provided
by the PORTB(SCH) pin. The S5D2650 provides the output of a comparator that measures whether the current
color burst phase relative to the falling edge of the sync is greater or less than a predetermined constant. This
constant is controlled with SCHCMP[3:0]. The polarity of the SCH output pin depends on the current

Digital video output

HS1,2

HAV

Blank

Active video

Analog video input

Chip delay

FS_PULSE

SLICE

SYG

BPG

CBG

CBGW

FH2

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SCHCMP[3:0] value. The SCH signal changes every video line. The SCH for line 260 is held for the entire vertical
blanking period. By using the SCH signal for the same line from each field, proper field identification can be
determined. Figure 8 shows field identification values for SCHCMP[3:0]=0. It is important to note that the SCH
value is only valid for video signals that have a constant sync tip to color burst relationship. This is not the case with
consumer VCRs.

Figure 7. Short Term Vertical Timing

HS1

ODD

VAV

EVAV

(default)

ODD FIELD and VALIGN = 0

60 Hz - CCIR 601 = 885, Square = 708

50 Hz - CCIR 601 = 891, Square = 971

0, except 60 Hz Square = 2

EVEN FIELD or VALIGN = 1

27, except 60 Hz Square = 28

0, except 60 Hz Square = 2

ODD

Note: Numbers shown are in CK. Active high polarities are used. Timing shown for VAV and EVAV are with qualifier off.

15, except 60 Hz Square = 14

60 Hz - 261

50 Hz - CCIR 601 = 273, Square = 341

HAV

default width for each input standard and output mode

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Figure 8. NTSC Vertical Timing Signals

The PID pin is used to identify whether the current V-axis is inverted in PAL mode. This signal changes at the color
burst. By noting this value at the same line of each field, a determination of whether a field is from {1-4} or {5-8} can
be made. As with the SCH pin, the S5D2650 is designed to hold the line 260 PID measurement for the entire
vertical blank period. This allows easy sampling of the PID or current field identification.

The ODD, SCH and PID signals change at different times and more than once within the video fields. Proper data
for field identification is determined by latching all three signals at the trailing edge of VS. Figure 9 shows the VS,
ODD, SCH, and PID signals and their latched values for each of the 8 possible fields. Figure 10 is the line to line
timing diagram for these signals in PAL mode.

Figure 9. PAL Vertical Timing Signals

ODD

SCH

FIELD

ODD

SCH

Truth Table

Note:
ODD and SCH are
measured at the trailing
edge of VS.

ODD

SCH

FIELD

ODD

SCH

Truth Table

Note:
ODD, SCH and PID are
measured at the trailing
edge of VS (VALIGN = 0).

PID

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Figure 10. Line to Line VS, SCH and PID Timing (PAL input)

1.3. HORIZONTAL LUMA PROCESSING

A simplified block diagram for the luma path is shown in Figure 11.

Figure 11. Horizontal Luma Processing Unit

1.3.1. Luminance DC Gain

The S5D2650 can accommodate CCIR 624 M/N/H/G standards, which fall into categories of -40 or -43 sync tip and
inclusion or exclusion of 7.5 setup. The S5D2650 can produce correct CCIR 601 luminance output levels by
controlling the gain and offset in the luminance path via PED. This register should be set for the appropriate input
standard. The programmable CONT and BRT registers provide the user with additional flexibility to create
non-standard luminance gain and offset values.

ODD

PID

SCH

Decimation
Filter

Chroma
Trap

HYBWR

CTRAP

HYPK

CONT

BRT

FROM ADC

Horizontal

Peaking

Contrast
Control

Brightness
Control

Programmable
Low Pass Filter

HYLPF

HYBWI

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Figure 12. Luminance Signal

Luminance levels produced by the S5D2650 for different broadcast standards (assuming AGCGN=0, CONT=0 and
BRT=0) are summarized in Table 5.

When digital component output is desired in RGB mode, the RGBH register can be programmed to increase the
0-100% values from standard CCIR 601 levels to full range levels.The gain variations are shown in Table 6.

Table 5: Luminance Digital Level Code

M/N PED=1

M/N PED=0

B/G/H PED=1

Signal

Level

(IRE)

ADC

(CVBS)

Y[7:0]

Level

(IRE)

ADC

(CVBS)

Y[7:0]

Level

(IRE)

ADC

(CVBS)

Y[7:0]

Max Input

109

255

109

255

117

255

Peak White

100

240

235

100

240

235

100

229

235

Black

7.5

Blank

Sync

-40

-43

S5D2650 Data
Path Equation

Table 6: RGB Output Range

RGB normal gain (RGBH=0)

RGB high gain (RGBH=1)

Signal

RGB (U,V=0)

Peak White

235

255

Black

Peak W hite

B lack Level

B lanking Level

S ync Tip

M ax Input

1.37 CV BS 100

{

SPTZZAN@K YV

{

SPUYAN@K ZR

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For CCIR 601 digital video input (INPSL[1:0] = 1), register UNIT must be set to 1 to produce unit gain.

1.3.2. Horizontal Luma Frequency Shaping

The luma path contains many programmable filters for different purposes. The combination of these filters will give
different frequency characteristics.

The over sampled video data from the ADC pass through a decimation filter. The decimation filter has user
programmable bandwidth. Three registers are used to control the decimation filter characteristics and each is
designed for certain purposes. The HYBWI, when set to "1", provides extra bandwidth for very high quality video
source. The HYBWR, when set to "1", reduces the bandwidth so high frequency noise can be eliminated. The 3-bit
register HYLPF[2:0] provides the necessary bandwidth reduction for horizontal scaling. When all three registers
are programmed to "0", the decimation filter has the bandwidth of the normal video. The S5D2650 provides the
option of bypassing the decimation filter. This option should be used only when the input video is band limited and
with low high frequency noise.

For composite video input, the notch filter can be enabled (CTRAP set to "1") to extract the luminance. The notch
filter has different center frequencies for different input video format. User selectable peaking function is included
for edge enhancement. The notch filter should be bypassed for S-video and component video input, or if luma
comb filter is enabled.

The luminance filter characteristics have been designed to be very similar for all combinations of 60/50 Hz video
and CCIR 601/square pixel sampling rates. Figure 13 and Figure 14 show the output characteristics of the
luminance path with different filter combinations for the supported input standards and output pixel rates.

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1.4. HORIZONTAL CHROMA PROCESSING

A simplified block diagram for the horizontal chroma processing unit is shown in Figure 17.

Figure 17. Horizontal Chroma Processing Unit

The S5D2650 supports chroma input in NTSC, PAL, SECAM and component formats. The color standard is
automatically detected and the various chroma processing blocks are enabled as required for the given chroma
standard. Details of the various chroma processing blocks follow.

1.4.1. IF Compensation

For improved chroma demodulation when the input video is from a mis-tuned IF source, an IF compensation filter
is included that has variable gain for the upper chroma side band. This is controlled by the CIFCMP[1:0] bits at
location CDEM. The frequency response is shown in Figure 18. For convenience, all plots are normalized to the
NTSC modulation frequency.

Gain

Tracking

Frequency

Tracking

COS

SIN

CBW,FSEC

CKILL

CGTC

SAT

CORE

HUE, TSTCFR

CFTC

Color
Killer

CKILL

Low
Pass

FROM ADC

Saturation

Control

SECAM
Frequency
Differentiator

UGAIN
VGAIN

Coring

Control

UOFFST

Offset
Control

VOFFST

Gain / PAL

Control

Auto

Detect

RTCO

RTC_PID

RTC_DTO

Control

TSTCGN

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Figure 18. Chroma IF Compensation Frequency Response

1.4.2. Demodulation Gain

The demodulation gain block is controlled by feedback from the gain tracking block. For NTSC and PAL type
inputs, the gain constant is derived from a programmable reference compared against the U component of the
input video. This reference is controlled by the SAT register. The default value "0" is the correct gain (saturation for
nominal output). For SECAM type input, the feedback is calculated such that proper frequency demodulation is
obtained. When external calibration is desired, the gain feed back loop can be "opened" by setting TSTCGN=1.
The SAT then controls bits 8 through 1 of a 10 bit multiplier.

For standard auto tracking applications, it is recommended that the SAT register be used as an end user saturation
control. This register is 2's complement.

1.4.3. Demodulation Low Pass Filter

The demodulation circuit also contains a programmable low pass filter and a coring function for noise reduction.
The chroma low pass filter frequency response for the demodulation circuit for the various video standards are
shown in Figure 19

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Figure 21. De-emphasis Filter Frequency Response

1.4.5. Additional Chroma Functions

S5D2650 has many built in auto detection circuits. These allow S5D2650 to track any type of video standard input
automatically.

For analog component video input, the demodulation function is not enabled. The low pass filter provides a group
delay for Cb and Cr alignment. This enables the two components to be sampled by one ADC.

An RTCO serial output is provided that encodes the current chroma and pixel frequency of the decoder. This
information can be used by an Encoder running off of the decoder clock to produce proper color output. The
horizontal position of the serial signal is controlled by the HS2 location. The phasing of the DTO and the Encoder
can be reset using the RTC_DTO bit. For PAL mode, the PID polarity can be controlled with the RTC_PID bit.

1.5. COMB FILTER

Comb filters provide superior Y/C separation for composite NTSC and PAL than simple chroma trap filter. The
S5D2650 contains on-chip separate 2-line stored luma and chroma comb filters. An internal signal COMB controls
for what lines the comb function is enabled. This signal is available through the PORTB pin. Combing is part of the
vertical processing which also includes vertical scaling, which is discussed in Section 1.6. A block diagram for the
vertical processing section is shown in Figure 22.

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Figure 22. Vertical Processing

1.5.1. Luma Comb Filter

The luma comb filter reduces high frequency chroma leakage into the luminance path. The S5D2650 uses 2-line
stored luma data for combing. Filter coefficients for different video input standards are provided and can be
selected automatically based on the video input. Filter coefficients may also be set manually.

An optional active comb is employed for NTSC video. Selection of luma comb coefficients is based on line-to-line
chroma correlation.

Provision is made to disable luma comb for S-video, component, or digital video input. This is achieved by
programming the luma comb control register MNYCMB to "1", and by choosing the value 3 or 4 for YCMBCO[2:0].
This will result either a 1-line or 2-line luma delay. Care must be exercised when disabling the luma comb so that
luma line delay matches the chroma path line delay.

Special filtering is applied to ensure that high vertical bandwidth is retained for the luma path.

1.5.2. Chroma Comb Filter

The chroma comb filter provides further color separation from the composite video. Filter coefficients can be
automatically selected based on the input video standard or manually set using NMCCMB and CCMBCO[2:0].

Luma

Chroma

Horizontal
Scaler

Luma
Adaptive
Comb

Chroma
Comb

Luma
Vertical
Scaler

Chroma
Vertical
Scaler

Vertical
BW
Retention

Sum

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1.6. SCALING

The S5D2650 includes a high quality down scaler. The video images can be down scaled in both horizontal and
vertical direction to an arbitrary size.

1.6.1. Horizontal Scaler

The horizontal scaler uses a 5-tap 32-phase interpolation filter for luma, and a 3-tap 8-phase interpolation filter for
chroma. Scaled pixel data are stored in an on-chip FIFO so they can be sent out in a continuous stream.

Horizontal scaling ratio is programmed via the 15-bit register HSCL. The timing signal EHAV is used to indicate
when scaled pixel data is available at the video output port. EHAV can be programmed so that it is active for every
line regardless of vertical cropping and scaling. Or it can be programmed to be active only for valid video lines. For
example, Figure 23 shows the timing for CIF output assuming HAV is programmed to be active for 720 pixels. The
HSCL register is programmed with the value 4000 (hex). The trailing edge of EHAV is either aligned with the
trailing edge of HAV if the total number of scaled pixels is even, or is one pixel clock earlier if the number is odd.

Figure 23. Horizontal Scaler Timing for CIF Output (CCIR 601 Pixel Rate)

Frequency response and group delay for the luma scaler are shown in Figure 24 and Figure 25, respectively. The
luma interpolation filter is designed to achieve relatively flat frequency response and minimal group delay up to the
normal video bandwidth. A flat full data path frequency response may be obtained with the help of the luma
peaking control register HYPK[1:0]. The high quality filter ensures minimal artifacts for any scaling ratio.

CK2

HAV

EHAV

720

360

Y[7:0]

357

358

359

C[7:0]

356

358

356

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Figure 24. Horizontal Luma Scaler Interpolation Filter Frequency Response

Figure 25. Horizontal Luma Scaler Interpolation Filter Group Delay

Because of the limited bandwidth of the chroma data, a simpler interpolation filter is used for the horizontal chroma
scaler. The frequency response and group delay for this filter are shown in Figure 26 and Figure 27, respectively.

1.5

2.5

oup de

l
a

(

.
5

l
oc

)

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1.6.2. Luma Vertical Scaler

Vertical luma scaling uses either a 3-tap or 5-tap 8-phase interpolation filter depending on the horizontal scaling
ratio.

Vertical scaling ratio is programmed via the 14-bit register VSCL. A valid scaled line is indicated by the timing
signal EVAV being active. The EVAV can be programmed to be internally gated by the VAV signal so it can only be
valid within the vertically cropped region.

Luma horizontal scaling can use either a 3-tap or a 5-tap interpolation filter depending on the horizontal scaling
ration. If the scaled horizontal line has less than or equal to 384 pixels, the 5-tap luma interpolation filter can be
turned on by programming the VRT2X bit to a "1". Otherwise, the VRT2X bit should be set to "0" and the 3-tap filter
be used.

The VYBW bit provides additional vertical bandwidth control for vertical scaling. Typically, when the vertical scaling
ratio is less than 1/2, this bit should be set to "1" to eliminate any aliasing effect.

Luma vertical scaler interpolation filter frequency response is shown in Figure 28.

Figure 28. Luma Vertical Scaler Interpolation Filter Frequency Response

In vertical scaling, the start of signal VAV controls the phase of the vertical scaler interpolation filter. If VAVB, VAVE,
VAVOD0, VAVEV0, and VSCL are programmed such that the vertical interpolation filter has the same phase and
scaling ratio as that of a memory controller (most memory controller has simple line dropping vertical scaling), it is
possible to interface the S5D2650 to the memory controller without using EVAV.

1.6.3. Chroma Vertical Scaling

Chroma vertical scaling uses different algorithms depending on video input standard and horizontal scaling ratio. If
horizontal scaling results in line with less than or equal to 384 pixels, and the VRT2X is set to a "1", a 5-tap
interpolation filter will be used for all video inputs. Otherwise, for NTSC, a 3-tap interpolation filter will be used for

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1.7. VBI DATA PROCESSING

The S5D2650 VBI data processing is very flexible in that it supports VBI data formats of:

· Closed Caption Line 21 Data Service (EIA-608)

· 525 line / 60Hz Teletext systems B,C,D (ITU-R BT.653-2)

· 625 line / 50Hz Teletext systems A,B,C,D (ITU-R BT.653-2)

· Copy Generation Management System (EIA/IS-702)

· Wide Screen Signalling (WSS ETS 300 294).

Note that the SMPTE data slicing is removed for the S5D2650 and replaced with the WSS / CGMS processing.
This data can be accessed from the part via four different methods:

· Enabling the "Raw un-processed 27MHz" Y ADC samples to be output for the appropriate lines in place of the

normal YUV data.

· Slicing the data (creating a clock and comparing the data to a threshold at the clock) and bursting this data out

on Y output.

· Reading the sliced data from two internal registers via the IIC bus.

· Via 2 external pins that output the sliced VBI data(CCDAT) and the time at which the slice is valid(CCEN).

A simplified block diagram for the VBI section is shown in Figure 30.

Figure 30. VBI Decoder Block Diagram

MODE

CCEN

CLOCK

ODD
ODDEN
EVENEN
ODDOS
VBIL

CTRL
LOGIC

SLICER

From Y ADC

GENERATOR

PIXSEL
IFMT
SECAM

FRAME
ALIGNMENT

FIFO

Y[7:0]

Normal
Decoded Y Data

CCDATA

MUX /
VBI
Format

VYFMT
VBINSRT

TTFRAM

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Table 7 lists all the video standards that the VBI data slicer supports. Some of these modes are auto detected
based on the current video input standard,

Configuring the VBI processing consists of many different steps which are individually explained below.

1.7.1. Enabling the VBI Processor

The VBI processor can be enabled independently for the ODD or EVEN fields with the ODDEN and EVENEN bits.
Some VBI data is only present on line in 1 of the 2 fields, These independent field enables allow control of the total
VBI data output from the chip. These controls apply to all VBI Lines, Thus it is not possible to enable Closed
caption line 21 for the Even field and line 19 Teletext for both the odd and even field.

1.7.2. Selecting the Type of Output Data

As previously mentioned, there are 4 different ways the VBI data can be extracted. Three of these are selected as
shown in the table, the fourth method (CCEN and CCDAT pins) is always available if VBI processing is enabled.

Table 7: Video Standards Supported by VBI Decoder

Mode

Value of Chip

Detection Bits

Required Values of

Registers to enable

Standard

Characteristics of the

Standard

Format

SECAM

VBIL0-15 TT_SYS

Data Rate

(MHz)

Number of

Bits (bytes)

60Hz Teletext system C
(NTSC / Intercast)

5.727272

272 (34)

50Hz Teletext system B
(PAL)

6.9375

344 (43)

50Hz Teletext system A
(SECAM)

6.203125

304 (38)

60Hz Teletext system B

5.727272

280 (35)

50Hz Teletext system C

5.734375

272 (34)

50Hz Teletext system D

5.6457875

280 (35)

60Hz Teletext system D

5.727272

280 (35)

Closed Caption NTSC 601

N/A

0.5035

16 (2)

CGMS (NTSC 60Hz)

N/A

0.447443

20 (3)

WSS (PAL 50Hz)

N/A

5.0000

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The S5D2650 adds an additional output mode and flexibility to vary the modes from line to line. If VBCVBS=0 and
VBINSRT=1 S5D2650 will output sliced data on enabled lines. By setting VBIMID to 1, any line for which VBIL=3
will output raw ADC data instead of WSS or CGMS. This mode allows a mixture of sliced and raw data. This can be
used to output raw data from a teletext line and sliced data from a closed caption line.

1.7.3. Select Individual Lines Enabled for VBI Processing

The S5D2650 allows programmable selection of processing for the various video lines. For example
Teletext/Intercast data can be sliced for lines 14 - 17, and closed caption for line 21. Each 2-bit register VBIL0
through VBIL15 defines how a specific VBI line is processed. As can be seen in Figure 36 for 60 Hz and Figure 37
for 50 Hz video, the following alignments exist:

Table 8: VBI Data Output Mode (VBILn != 0)

VBCVBS

VBINSRT

Output Mode

The VBI data is available via the internal registers CCDAT1 and
CCDAT2. Only the last 2 extracted bytes are stored in these
registers. Thus, this mode is only useful for extraction of Closed
Caption data(Read the register value).

This mode enables output of the sliced VBI data(Y Port output).

This mode enables output of direct data from the ADC(ADC Data
bypass at 27Mhz sampling rate).

This mode is invalid.

Table 9: VBI Line(s) Selection

VBIL

number

Line Number That the VBIL Processing command applies

to (Assuming ODDOS=1)

Odd Field

60 Hz

Even Field

60 Hz

Odd Field

50 Hz

Even Field

50Hz

VBIL0

All Lines
Except 10-24

All Lines
Except
273-287

All lines
Except 7-21

All lines Except
320 - 334

VBIL1

9&10

272&273

6&7

319&320

VBIL2

274

321

VBIL3

275

322

VBIL4

276

323

VBIL5

277

324

VBIL6

278

325

VBIL7

279

326

VBIL8

280

327

VBIL9

281

328

VBIL10

282

329

VBIL11

283

330

VBIL12

284

331

VBIL13

285

332

VBIL14

286

333

VBIL15

24&25

287&288

21&22

334&335

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The ODDOS[1:0] bits allow offset between the odd and even fields. Thus VBIL9 can be lines 17,18 or 19 for ODD
fields while VBIL9 is still line 281 for EVEN fields. This extra controls account for variations of VBI data locations
from ODD and EVEN fields.

When Intercast or Teletext data is selected, an 8-bit user programmable register (TTFRAM) is provided for the
framing byte. The frame alignment processor uses this information to properly locate the first data bit on each line

1.7.4. Raw CVBS Data Output Format

When raw ADC data is selected as output in place of the normal YUV or RGB data. The following rules apply:

· For 656 type 8 bit outputs, The ADC data outputs with successive data points in place of the Cb, Y, Cr, Y data

stream.

· For 16 bit or 24 bit outputs, The ADC data is output on the Y[7:0] and C[7:0] output pins. At any CK2 clock 2

bytes of ADC data are output. The Y[7:0] bus represents data N while C[7:0] is data N+1.

· ADC data is only output during the region that HAV is active.

· All ADC outputs are limited to the range 1-254, thus a 0 or 255 value will not be output.

For the line selected mode described above using VBCVBS and VBIL, data is from the luma ADC only. If C ADC
data or the entire video line is required, configure OFMT bits.

1.7.5. Sliced Data Output Formats

While sliced data is available for many of the output formats, the target application is 656 output format. The
description of data format is limited to this mode. The S5D2650 allows this data to be output during active video.

Figure 31 shows the timing diagram for VYFMT[1:0]=3.

Figure 31. VBI Insertion Timing for VYFMT[1:0]=3

Digitized CVBS data can also be output on the video output port (except for output format 1, 5 and 7). CVBS is
always digitized at the CK clock rate. CVBS data is available when HAV is active. Raw CVBS data is output in a

Video input

HAV

23h

54h

10h

CCEN -VBINSRT=0

10h

84h

E4h

85h

2Dh

A4h

45h

10h

CCEN -VBINSRT=1

Y[7:0] -- VYFMT=3

Zoom In - Random data

VBINSRT=1

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similar fashion as decoded video. For 8-bit output format, data is output at CK rate using the same 8-bit port as the
decoded video. For 16-bit and 24-bit output format, data is output at CK2 rate using Y and C ports. The sequence
of data output is CVBS

on Y, and CVBS

2n+1

on C (note that EXV port is not used in 24-bit format for outputting

raw CVBS data).

For Closed Caption data, two read-only registers, CCDAT1 and CCDAT2, are provided so the Closed Caption data
can be read via the host interface. The VBIFLG bit can be polled to see if data captured in the two registers can be
safely read.

1.8. COLOR SPACE CONVERTER

The color space converter processes the video data as YCbCr 4:4:4 when converting to RGB. A programmable
limiter (YCRANG) can be imposed on the Y/C data to limit the ranges. One can choose to limit the Y/C to 1 - 254,
or Y to 16 - 235 and C to 16 - 240.

When selected, YCbCr 4:4:4 is converted to 24 bit RGB according to the following equations:

R = C

+ 1.375(C

-128)

G = C

- 0.703(C

-128) - 0.328(C

-128)

B = C

+ 1.734(C

-128)

For 16-bit RGB output, truncation with dithering is used to convert the data from 24 bit to 16 bit.

1.9. GAMMA CORRECTION

The S5D2650 programmable gamma tables allows the customer to apply many different type of corrections. These
corrections can be a standard 2.2 factor for NTSC or 2.8 for PAL. These factors can be applied in the RGB or YUV
domains.

A basic standard gamma equation of

when applied to the R, G, or B signals, generates the response shown as the upper curve below. It is the inverse of
the monitor response and thus compensates to produce a linear response.

626

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Figure 32. RGB Gamma Correction

1.9.1. Programming the S5D2650

The previous response is easily programmed into the S5D2650 loading the 0, 8, 16, 24 etc. values into the
GAMMA0,1,2,3 locations. Thus every 8th value is stored. The S5D2650 will use linear interpolation to generate the
values between every 8th points. This is shown in the following figure.

Figure 33. Gamma LUT Programming

TV tube characteristic

Gamma correction

Effective output

192 200 208 216 224 232 240

248

Input

GAMMA0

GAMMA1

GAMMA2

GAMMA3

GAMMA4

GAMMA5

GAMMA6

GAMMA7

GAMMAD0

GAMMAD1

GAMMAD2

Output

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For ease of design, the difference between adjacent points must also be loaded. The complete data values for the
previous gamma factor of 1/2.2 is shown in the table below.

The flexibility of this architecture is shown in the following example. Here it is assumed that the S5D2650 is
operating in a YUV output mode but some form of Gamma correction is required. By converting the RGB gamma
correction function back to the YUV color space, the following function can be applied to the U and V signals for
improved color performance. This flexibility can be extended in software to produce many type of customer defined
transfer functions.

Table 10: RGB Gamma LUT Values

Offset

GAMMA

program at index Offset+40h

GAMMAD

program at index Offset+60h

53 20

110

120

128

136

144

151

158

164

170

176

181

187

192

197

202

207

211

216

220

225

229

233

237

241

245

249

252

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1.10. DIGITAL VIDEO OUTPUT

The S5D2650 can output digital video data in various formats, which are tabulated in Table 11

All 8-bit output

Table 11: Digital Video Output Format

Clock

CK2

OFMT

2, 3

Type

YCbCr

4:2:2

YCbCr 4:1:1

YCbCr

4:4:4

RGB

565

RGB

888

RGB

888

YCbCr 4:2:2

Pin

Cb0

Cr0

Cb0

Cb1

Cr1

Cb1

Cb2

Cr2

Cb2

Cb3

Cr3

Cb3

Cb4

Cr4

Cr6

Cr4

Cr2

Cr0

Cb4

Cb5

Cr5

Cr7

Cr5

Cr3

Cr1

Cb5

Cb6

Cr6

Cb6

Cb4

Cb2

Cb0

Cb6

Cb7

Cr7

Cb7

Cb5

Cb3

Cb1

Cb7

Cb0

Cr0

Cb1

Cr1

Cb2

Cr2

Cb3

Cr3

Cb4

Cr4

Cb5

Cr5

Cb6

Cr6

Cb7

Cr7

EXV0

Cr0

EXV1

Cr1

EXV2

Cr2

EXV3

Cr3

EXV4

Cr4

EXV5

Cr5

EXV6

Cr6

EXV7

Cr7

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formats use CK as pixel clock; the other formats use CK2 as pixel clock. The first pixel is always aligned to the
leading edge of the HAV signal.

1.10.1. Validation Code Insertion

S5D2650 inserts validation codes during inactive video (HAV is inactive), and invalid video (HAV is active but
EHAV is inactive) to assist in recognition of scaled data and VBI data. Table 12 lists the available codes, when they
are inserted, and related programming registers.

An example timing diagram for some of the programmable modes is shown in Figure 35. In this diagram, The field
rate is 60 Hz, A CCIR 601 sampling rate has been selected thus giving 720 active pixels. The horizontal scaling
ratio has been selected for an output of 718 out of 720 pixels.

Table 12: Invalid and Unused Code Insertion

Code

Description

INVALY

This user programmed code is inserted in the Y or G output stream in scaling operation when
HAV is active while EHAV is inactive. Insertion of this code is independent of the output
format. Related register is INVALY.

INVALU

This user programmed code is inserted in the U or B output stream in scaling operation when
HAV is active while EHAV is inactive. Insertion of this code is independent of the output
format. Related register is INVALU.

INVALV

This user programmed code is inserted in the V or R output stream in scaling operation when
HAV is active while EHAV is inactive. Insertion of this code is independent of the output
format. Related register is INVALV.

UNUSEY

This user programmed code is inserted in the Y or G output stream when HAV is inactive and
no other reference code is inserted. Insertion of this code is independent of the output format.
Related register is UNUSEY.

UNUSEU

This user programmed code is inserted in the U or B output stream when HAV is inactive and
no other reference code is inserted. Insertion of this code is independent of the output format.
Related register is UNUSEU.

UNUSEV

This user programmed code is inserted in the V or R output stream when HAV is inactive and
no other reference code is inserted. Insertion of this code is independent of the output format.
Related register is UNUSEV.

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Figure 35. Horizontal Data Timing for Various Output Modes

1.10.2. 656 Op Codes

The S5D2650 supports timing synchronization through embedded (656) timing reference codes in the output video
data stream. This mode is available for output format 3 ( OFMT[3:0] = 3). The 656 Op Codes follow the CCIR 656
standard. An optional set of 656 Op Codes can be enabled to identify VBI data using the TASKB bit.

The (A,B,C,D) inserted codes for 656 output modes are explained below. Locations in the data stream are shown
in Figure 35. The D' data is substituted for the standard codes shown in column D if TASKB bit is set and the
current line is processing VBI data (sliced or raw ADC data format).

714

715

T714

Y715

714

715

714

EHAV

CK2

HAV

714

715

Legend

Luma Data with pixel number

Chroma (Cb) Data with pixel number

Chroma (Cr) Data with pixel number

Programmable INVALY data (index 0x32)

Programmable INVALU data (index 0x33)

Programmable INVALV data (index 0x34)

Programmable UNUSEY data (index 0x35)

Programmable UNUSEU data (index 0x36)

Programmable UNUSEV data (index 0x37)

OFMT=0 (16 bits @ 13.5 Mhz 4:2:2 - 601)

Invalid data (During
Active Video but Scaling
Has made picture smaller
and right justified)

Unused Data

OFMT=2 (8 bits @ 27 Mhz 656 data no SAV EAV)

Unused Data

If Horizontal Scaling is
disabled, EHAV will be the same
as HAV and there will be no
Invalid data. For this Example,
the last Data would be

719

OFMT= 3

SAV -- see Table

12 for details

EAV -- see table for details

Same Format as OFMT=2

OFMT=4 (24 bits @ 13.5 Mhz YUV 4:4:4)

Y[7:0]

C[7:0]

Y[7:0]

C[7:0]

EXV[7:0]

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Figure 36. Vertical Timing for 60 Hz Video

Fields
2,4

ODD

263

264

265

266

267

268

269

270

271

272

273

525

284

283

Fields
1,3

60 Hz EVEN FIELD

60 Hz ODD FIELD

VALIGN=0

ODD

VBIL[N]

656 SAV EAV Codes for VSE=0, VALIGN=1

Digital
Output

VALIGN=0

ODD

VALIGN=1

VALIGN=0

VALIGN=1

VBIL[N]

Y[0..7]

VALIGN=1

F1 EC F1 EC F1EC B6AB B6AB B6AB B6AB B6AB B6AB 9D80

9D80 9D80

9D80

VSE=1

VSE=0

VSE=1

VSE=0

VSE=1

VSE=0

VSE=1

VSE=0

VSE=1

Y[0..7]

B6AB B6AB F1 EC F1EC F1EC F1 EC F1 EC F1 EC F1 EC F1C7 DAC7 DAC7 DAC7

VSE=1

VSE=0

VSE=1

VSE=0

VSE=1

VSE=0

656 SAV EAV Codes for VSE=0, VALIGN=1

VALIGN=1

DAC7

9D80

Input

Analog

Digital
output

264

265

266

267

268

269

270

271

272

273

284

283

Analog
Input

285

SAV

EAV

SAV

EAV

TASK B VIP 656 SAV EAV Codes for VSE=0, VALIGN=1, VBIL12-VBIL1=1, TASKB=1

Y[0..7]

F1EC F1EC F1 EC B6AB B6AB B6AB B6AB B6AB B624 13 0E 13 0E 13 0E

13 80

DAC7

13 80 9D80 9D80

9D80

9D80 9D80

524

525

285

286

287

262

263

DAC7 DAC7 DAC7

9D80

DAC7

B6AB B6AB F1 EC F1 EC F1 EC F1EC F1EC F1 EC F1 62 7F 62

7F62

9D80

7FC7 DAC7 DAC7

9D80

Y[0..7]

TASK B VIP 656 SAV EAV Codes for VSE=0, VALIGN=1, VBIL12-VBIL1=1, TASKB=1

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Figure 37. Vertical Timing For 50 Hz Video

ODD

623

624

625

622

Fields
1,3

50 Hz ODD FIELD

VALIGN=0

ODD

Digital
Output

VALIGN=1

ODD

VALIGN=1

VBIL[N]

ODD

VALIGN=1

VSE=0

VSE=1

VSE=0

VSE=1

VSE=0

VALIGN=0

VSE=1

VSE=0

Y[0..7]

DAC7 F1EC F1EC

B6AB B6AB B6AB B6AB B6AB B6AB B6AB B6AB B6

656 SAV EAV Codes for VSE=0, VALIGN=1

Fields
2,4

310

311

312

313

314

315

316

317

318

319

320

50 Hz EVEN FIELD

VSE=0

VSE=1

VALIGN=0

VSE=1

VSE=0

VSE=1

VALIGN=0

VSE=1

VSE=-0

621

623

624

625

622

Analog
Input

AB 9D 80 9D 80 9D

DAC7

VSE=0, ALT656=0

VSE=0, ALT656=1

SAV

EAV

TASK B VIP 656 SAV EAV Codes for VSE=0, VALIGN=1, ALT656=1, VBIL15-VBIL1=1, TASKB=1

Y[0..7]

DAC7 DAC7 DAC7 F1EC F1EC B6AB B6AB B6AB B6AB B624

13 0E 13 0E 13 0E 130E 13 80 9D 80

DAC7

VBIL[N]

Y[0..7]

B6AB B6AB F1 EC F1EC F1EC F1EC F1EC F1EC F1EC F1EC F1EC F1EC F1EC F1

656 SAV EAV Codes for VSE=0, VALIGN=1

EC DAC7 DA C7 D

9D80

SAV

EAV

TASK B VIP 656 SAV EAV Codes for VSE=0, VALIGN=1, ALT656=1, VBIL15-VBIL1=1, TASKB=1

Y[0..7]

310

311

312

313

314

315

316

317

318

319

320

Digital
Output

Analog
Input

333

334

335

336

333

334

335

336

337

VSE=0, ALT656=0

VSE=0, ALT656=1

B6AB B6AB F1EC F1EC F1EC F1EC F1EC F1EC F162 54 49 54 49 54 49

54 49 54 49 54 C7 DA C7

9D80

B6AB B6AB

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1.10.3. 656 Op Code Vertical Transitions

The vertical transition locations of the various 656 Op Codes are shown in Figure 36 and Figure 37. Note that for
proper transition locations of the SAV and EAV Op Codes VSE=0 and VALIGN=1.

1.11. HOST INTERFACE

The S5D2650 supports the IIC serial interface for programming the chip registers.

1.11.1. IIC Interface

The two wire interface consists of the SCLK and SDAT signals. Data can be written to or read from the S5D2650.
For both read and write, each byte is transferred MSB first, and the data bit is valid when the SCLK is high.

To write to the slave device, the host initiates a transfer cycle with a START signal. The START signal is HIGH to
LOW transition on the SDAT while the SCLK is high. The host then sends a byte consisting of the 7-bit slave device
ID and a 0 in the R/W bit. The arrangement for the slave device ID and the R/W bit is depicted in Figure 38. AEX1
and AEX0 are configuration pins used to configure the S5D2650 to use one of the four addresses. Up to four
S5D2650's can be used in one system each with a unique address.

Figure 38. IIC Slave Device ID and R/W Byte

Table 13: 656 and TASKB 656 Op Codes

Condition

SAV / EAV Output Sequence --

Reference Output timing

pictures

656 FVH values

(low active)

Field

Vertical

Horizontal

(active)

(vbi)

Field 2

Vertical Blank

End Active Video

FFh

00h

F1h

7Fh

Field 2

Vertical Blank

Start Active Video

FFh

00h

ECh

62h

Field 2

Vertical Active

End Active Video

FFh

00h

DAh

54h

Field 2

Vertical Active

Start Active Video

FFh

00h

C7h

49h

Field 1

Vertical Blank

End Active Video

FFh

00h

B6h

38h

Field 1

Vertical Blank

Start Active Video

FFh

00h

ABh

24h

Field 1

Vertical Active

End Active Video

FFh

00h

9Dh

13h

Field 1

Vertical Active

Start Active Video

FFh

00h

80h

0Eh

AEX1

AEX0

R/W

msb

lsb

slave device ID

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The second byte the host sends is the base register index. The host then sends the data. The S5D2650
increments the index automatically after each byte of data is sent. Therefore, the host can write multiple bytes to
the slave if they are in sequential order. The host completes the transfer cycle with a STOP signal which is a LOW
to HIGH transition when the SCLK is high.

Each byte transfer consists of 9 clocks. When writing to the S5D2650, an acknowledge signal is asserted by the
salve device during the 9th clock.

Figure 39. IIC Data Write

A read cycle takes two START-STOP phases. The first phase is a write to the index register. The second phase is
the read from the data register.

The host initiates the first phase by sending the START signal. It then sends the slave device ID along with a 0 in
the R/W position. The index is then sent followed by the STOP signal.

The second phase also starts with the START signal. It then sends the slave device ID but with a 1 in the R/W
position to indicate data is to be read from the slave device. The host uses the SCLK to shift data out from the
S5D2650. A typical second phase in a read transaction is depicted in Figure 40. Auto index increment is supported
in Read mode.

Figure 40. IIC Data Read

SCLK

SDAT

device ID

index

data

START

STOP

ACK

SCLK

SDAT

device ID

index

START

STOP

ACK

SCLK

SDAT

device ID

data

START

STOP

NACK

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2. CONTROL REGISTER DESCRIPTION

This section contains information concerning the programmable control registers. Table 14 provides the default
power up values for each index, and a bit map for each register. The following pages describe each register in
detail and the possible programing values (an * indicates the power-on default). Gamma correction registers are
write only. When the index register points to any of the Gamma correction register, the Gamma look-up table is put
into a program mode. Normal operation resumes when the index is outside the range from 0x40 to 0xFF.

Table 14: Register Summary

Index Mnemonic Default

Bit Map

0x00

STAT

CHIPID

VBIFLG

NOVID

FFRDET

PALDET

CDET

HLOCK

CLOCK

0x01

CMDA

POWDN

VSE

HFSEL[1:0]

XT24

PIXSEL

MNFMT

IFMT

0x02

CMDB

AGCGN

VALIGN

AGCOVF

AGCFRZ COMP_PH

INSEL[2:0]

0x03

CMDC

VMEN

TSTGE1

TSTGPK

TSTGPH

TSTGFR[1:0]

TSTGEN

0x04

CMDD

EAV

CADC_PD

CKDIR

INPSL[1:0]

SYNDIR

PROG

GPPORT

0x05

HAVB

HAVB[7:0]

0x06

HAVE

HAVE[7:0]

0x07

HS1B

HS1B[8:1]

0x08

HS1E

HS1E[8:1]

0x09

HS2B

HS2B[8:1]

0x0A

HS2E

HS2E[8:1]

0x0B

AGC

AGC[7:0]

0x0C

HXTRA

HAVB[10:8]

HAVE[10:8]

HS1BE0

HS2BE0

0x0D

CDEM

OUTHIZ

FSEC

TBC_ON

CIFCMP[1:0]

0x0E

PORTAB

DIRB

DATAB[2:0]

DIRA

DATAA[2:0]

0x0F

LUMA

UNIT

RGBH

PED

HYBWR

CTRAP

HYPK[1:0]

0x10

CON

CONT[7:0]

0x11

BRT

BRT[7:0]

0x12

CHROMA

ACCFRZ

PALM

PALN

CBW

CORE[1:0]

CKILL[1:0]

0x13

CHROMB

CDLY[3:0]

SCHCMP[3:0]

0x14

DEMOD

FSCDET

SECDET

CDMLPF

CTRACK

MNFSC[1:0]

MNSECAM[1:0]

0x15

SAT

SAT[7:0]

0x16

HUE

HUE[7:0]

0x17

VERTIA

MNYCMB

YCMBCO[2:0]

VRT2X

VCTRL[2:0]

0x18

VERTIB

HYLPF[2:0]

HYBWI

HYDEC

VSCLEN[1:0]

0x19

VERTIC

MNCCMB

CCMBCO[2:0]

ACMBEN

VYBW

EVAVEV

EVAVOD

0x1A

HSCLL

HSCL[6:0]

CMBMOD

0x1B

HSCLH

HSCL[14:7]

0x1C

VSCLL

VSCL[5:0]

ACMBCO ACMBRE

0x1D

VSCLH

VSCL[13:6]

0x1E

OFMTA

GAMEN[1:0]

OENC[1:0]

OFMT[3:0]

0x1F

OFMTB

VSVAV

EVAND[1:0]

EVHS1

EVHAV

EVEHAV

EVAVG

EVANDL

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0x20

VBICTL

VBCVBS

VYFMT[1:0]

VBINSRT

ODDEN

EVENEN

ODDOS[1:0]

0x21

CCDAT1

0x22

CCDAT2

0x23

VBIL30

VBIL3

VBIL2

VBIL1

VBIL0

0x24

VBIL74

VBIL7

VBIL6

VBIL5

VBIL4

0x25

VBIL118

VBIL11

VBIL10

VBIL9

VBIL8

0x26

VBIL1512

VBIL15

VBIL14

VBIL13

VBIL12

0x27

TTFRAM

TTFRAM[7:0]

0x28

TESTA

0x29

UVOFFH

TSTCLC

TSTCGN

TSTCFR

UOFFST[5:4]

VOFFST[5:4]

0x2A

UVOFFL

UOFFST[3:0]

VOFFST[3:0]

0x2B

UGAIN

UGAIN[7:0]

0x2C

VGAIN

VGAIN[7:0]

0x2D

VAVB

VAVB[6:1]

VAVOD0

VAVEV0

0x2E

VAVE

VAVE[8:1]

0x2F

CTRACK

DMCTL[1:0]

CGTC[1:0]

CFTC[1:0]

0x30

POLCTL

EVAVPL

VSPL

ODDPL

HAVPL

EHAVPL

HS2PL

VAVPL

HS1PL

0x31

REFCOD

YCRANG

0x32

INVALY

INVALY[7:0]

0x33

INVALU

INVALU[7:0]

0x34

INVALV

INVALV[7:0]

0x35

UNUSEY

UNUSEY[7:0]

0x36

UNUSEU

UNUSEU[7:0]

0x37

UNUSEV

UNUSEV[7:0]

0x38

EXCTRL

PERMIN

ENINCST

SLEV[1:0]

OFFST_CONT[1:0]

CLEVEL

0x39

TRACKA

STCTRL

MAC_DET

VCR_DET

VCR_LEV[1:0]

ATCTRAP VCTRAP

AGCLSB

0x3A

VBICTLB

VBISWAP

TT_SYS[1:0]

VBIMID

NEW_CC CC_OVFL YOFFENB COFFENB

0x3B

TRACKB

ALT656

VBI_PH

VBI_FR

PH_CTRL VNOISCT

AGC_LPG[1:0]

AGC_LKG

0x3C

RTC

RTC_DTO RTC_PID SEC_POL

TDMOD

VCO_BIAS[1:0]

PUMP_BIAS[1:0]

0x3D

CMDE

ODFST

VSALG

HCORE[1:0]

CHIPREVID

0x3E

VSDEL

TR_MS

NOVIDC

VSDEC[5:0]

0x3F

CMDF

CTRAPFSC

VIPMODE

EVAVY

UVDLEN

UVDLSL

REGUD

TASKB

CBWI

0x40-5F

GAMMA

GAMMA0[7:0] - GAMMA31[7:0]

0x60-7F

GAMMAD

GAMMAD0[5:0] - GAMMAD31[5:0]

0xC0-DF

GAMUV

GAMUV0[7:0] - GAMUV31[7:0]

0xE0-FF

GAMUVD

GAMUVD0[5:0] - GAMUVD31[5:0]

Table 14: Register Summary

Index Mnemonic Default

Bit Map

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Read Only Status Bits

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

00h

STAT

CHIPID

VBIFLG

NOVID

FFRDET

PALDET

CDET

HLOCK

CLOCK

Status for color lock.

Not locked.

Color lock achieved.

HLOCK

Status for current line tracking mode.

Chip is in initial tracking mode.

Chip is in steady state tracking mode.

CDET

Status for detection of color.

No color signal is detected.

Color signal is detected.

PALDET

Status for current detected color format. Information contained in this bit is valid only if
CLOCK is 1.

NTSC color format.

PAL color format.

FFRDET

Status for current detected field frequency.

50 Hz field frequency, i.e. N,B,G,H,I,D,K,K1,L system.

60 Hz field frequency, i.e. M system.

NOVID

Video detect flag. This bit should not be used for detecting the presence of a TV channel
from the output of a TV tuner.

Sync has been detected for the last 32 lines.

No sync has been detected.

VBIFLG

Vertical blanking interval flag.

Video is in active region.

Video is in vertical blanking region.

CHIPID

Chip version ID. Please refer to the CHIPREVID bits for additional information

KS0127B.

S5D2650.

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Control Register A

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

01h

CMDA

POWDN

VSE

HFSEL[1:0]

XT24

PIXSEL

MNFMT

IFMT

Manual video input standard select. Standard selection can be controlled automatically if
MNFMT=0.

Chip is forced to assume input is 50 Hz.*

Chip is forced to assume input is 60 Hz.

MNFMT

Manual input format control override. When this bit is 1 the IFMT bit is enabled.

The chip determines the input video standard based on the detected field rate:*
NTSC if 60 Hz.
PAL/SECAM if 50 Hz.

Input video standard is selected with the IFMT bit.

PIXSEL

Select pixel sampling rate.

Output data is at square pixel rate.

Output data is at CCIR 601 rate.*

XT24

Select the external clock reference frequency.

External clock is 26.8 MHz.

External clock is 24.576 MHz.*

HFSEL[1:0]

Horizontal tracking loop frequency select.

Force loop to very fast.

Force loop to fast.

Force loop to VCR time constant.*

Force loop to TV time constant.

VSE

Change the vertical end location of the VS.

Line 10/10.5.*

Line 9/9.5.

POWDN

Power down mode.

Normal operation.*

All chip functions except microprocessor interface and CK/CK2 generation are
disabled. The output of the CK/CK2 pins retains the most recent frequency when
the power down mode is enabled.

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Control Register B

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

02h

CMDB

AGCGN

VALIGN

AGCOVF

AGCFRZ COMP_PH

INSEL[2:0]

Analog input channel select.

AY0 is composite input.*

AY1 is composite input.

ACR0 is composite input.

ACR1 is composite input.

AY0 is Luminance input, ACB0 is chrominance input.

AY1 is Luminance input, ACB1 is chrominance input.

AY0 is luminance input, ACB0 is Cb input, ACR0 is Cr input.

AY1 is luminance input, ACB1 is Cb input, ACR1 is Cr input.

COMP_PH

Cb & Cr phase inversion in case of Component input

Normal operation *

Phase inversion

AGCFRZ

Freeze the analog AGC for the Y and C paths at their current values.

AGC is running. Reading AGC register returns the current AGC gain.*

AGC is frozen. Gain can be changed or read with AGC register.

AGCOVF

AGC gain control mode.

AGC gain tracks to sync tip and back porch delta.

If ADC overflows, AGC gain will be reduced (this has higher priority over normal
sync tip - back porch tracking).*

VALIGN

VS edge alignment control.

VS leading edge occurs during serration pulses (typically within the first serration
pulse). VS trailing edge is aligned to half line or beginning of the line depending on
the field.*

VS leading edge is aligned to half line or beginning of the line depending on the
field. VS trailing edge is always aligned to beginning of the line.

AGCGN

AGC gain calculation.

Normal mode. AGC gain calculation is based on sync tip to back porch difference
equal to 68 ADC code.*

AGC gain calculation is base on sync tip to back porch difference equal to 54 ADC
code. This will reduce the AGC gain by a factor of 1/1.25 compare to normal mode.
When used in conjunction with PED and RGBH, this effectively increases the input
dynamic range.

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Control register C

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

03h

CMDC

VMEN

TSTGE1

TSTGPK

TSTGPH

TSTGFR[1:0]

TSTGEN

Enable manual control of horizontal phase and frequency tracking.

Auto phase and frequency tracking.*

Enable manual control of horizontal phase and frequency with TSTGFR[1:0] and
TSTGPH.

TSTGFR[1:0]

When TSTGEN == 1, these two bits control the horizontal frequency tracking.

Stop frequency tracking and freeze the frequency at the current value.*

Horizontal frequency tracks the input.

Horizontal frequency tracking ignores video input and runs at nominal value based
on the field rate and output pixel rate selected by IFMT and PIXEL bits.

TSTGPH

When TSTGEN == 1, this bit controls the horizontal phase tracking.

No phase tracking.*

Horizontal phase tracks the input video or HS1 input if in slave mode.

TSTGPK

If TSTGE1 == 1, this bit controls AGC.

AGC clamps to back porch and gain is set based on sync tip-back porch difference.*

AGC clamps to sync tip and gain is set based on peak-valley difference.

TSTGE1

Enables the function of TSTGPK.

Disables TSTGPK.*

Enables TSTGPK.

VMEN

Vertical master mode.

Normal vertical sync operation.*

Vertical sync ignores input and free runs at 50 Hz or 60 Hz. This mode can be used
to generate video timing for a slave device.

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Control Register D

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

04h

CMDD

EAV

CADC_PD

CKDIR

INPSL[1:0]

SYNDIR

PROG

GPPORT

General purpose port. This register is useful only if DATAA[2:0] == 7. If DIRA == 0, this bit is
read only and reflects the logic state at PORTA pin. If DIRA == 1, any value written to this bit will
appear at PORTA pin.

PROG

Progressive YPbPr Input Mode, ADC sampling clock = 54 MHz

Interlaced YPbPr Input Mode.(720x480i)

Progressive YPbPr Input Mode.(720x480p)

SYNDIR

HS1 and VS pin direction control.

HS1 and VS are output.*

HS1 and VS are input.

INPSL[1:0]

Video input and clock source select.

Video source is analog and connected to the chip's analog input. Clock is internally
generated.*

Video source is 8-bit digital CbYCr and connected to EXV0 through EXV7 pins.

Video source is 8-bit digitized CVBS and connected to EXV0 through EXV7 pins.

CKDIR

Clock select.

Clock is from internal clock generator. A reference clock at XTALI pin is required.*

Clock is from CK pin. When this is selected, the CK pin automatically becomes an
input.

CADC_PD

C-ADC's Power down mode.

All ADC's Power On.

C-ADC's Power Down, in case of CVBS input modes*.

EAV

In 8-bit digital CbYCr input mode, this bit selects the sync source.

Horizontal and vertical syncs are from HS1 and VS pins, respectively.*

Syncs are embedded in the 8-bit digital data stream (CCIR 656 compatible).

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HAV Start Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

05h

HAVB

HAVB[7:0]

0Ch

HXTRA

HAVB[10:8]

HAVE[10:8]

HS1BE0

HS2BE0

HAVB[10:0]

This 11-bit register is used to define the start location of the HAV signal relative to the sync tip
(for CVBS input, this is the composite video sync tip. For 8-bit CbYCr input, this is the leading
edge of the HS1 or EAV). The content of this register is a 2's complement number which is
used as an offset to the default. The resolution for this register is 1 CK clock.

HAV End Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

06h

HAVE

HAVE[7:0]

0Ch

HXTRA

HAVB[10:8]

HAVE[10:8]

HS1BE0

HS2BE0

HAVE[10:0]

This 11-bit register is used to define the end location of the HAV signal relative to the sync tip.
The content of this register is a 2's complement number which is used as an offset to the
default The resolution for this register is 1 CK clock.

HS1 Start Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

07h

HS1B

HS1B[8:1]

0Ch

HXTRA

HAVB[10:8]

HAVE[10:8]

HS1BE0

HS2BE0

HS1B[8:1] -
HS1BE0

If HS1 is programmed as an output, this 9-bit register defines the start location of the HS1
signal. The content of this register is a 2's complement number which is used as an offset to the
default. The resolution for this register is 1 CK clock.

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HS1 End Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

08h

HS1E

HS1E[8:1]

0Ch

HXTRA

HAVB[10:8]

HAVE[10:8]

HS1BE0

HS2BE0

HS1E[8:1] -
HS1BE0

If HS1 is programmed as an output, this 9-bit register defines the end location of the HS1
signal. The content of this register is a 2's complement number which is used as an offset to the
default. The resolution for this register is 1 CK clock.

HS2 Start Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

09h

HS2B

HS2B[8:1]

0Ch

HXTRA

HAVB[10:8]

HAVE[10:8]

HS1BE0

HS2BE0

HS2B[8:1] -
HS2BE0

This 9-bit register defines the start location of the HS2 signal. The content of this register is a
2's complement number which is used as an offset to the default HS2B location. The resolution
for this register is 1 CK clock.

HS2 End Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0Ah

HS2E

HS2E[8:1]

0Ch

HXTRA

HAVB[10:8]

HAVE[10:8]

HS1BE0

HS2BE0

HS2E[8:1] -
HS2BE0

This 9-bit register defines the end location of the HS2 signal. The content of this register is a 2's
complement number which is used as an offset to the default HS2E location. The resolution for
this register is 1 CK clock.

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AGC Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x0B

AGC

AGC[7:0]

This register is used to manually set AGC when AGCFRZ is set to "1". The content in the
register is unsigned.

Chroma Demodulation Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0Dh

CDEM

OUTHIZ

FSEC

TBC_ON

CIFCMP[1:0]

IF compensation for the chroma path.

No compensation.*

Upper chroma side band is 1 dB higher than lower side band.

Upper chroma side band is 3 dB higher than lower side band.

Upper chroma side band is 6 dB higher than lower side band.

TBC_ON

Time based correction Test Mode

Normal operation*

TBC Test mode.

FSEC

Chroma frequency demodulation filter select for SECAM video.

Select SECAM chroma frequency demodulation filter if SECAM video is detected.*

Always use SECAM chroma frequency demodulation filter.

OUTHIZ

This is the software output three-state control bit. If this bit is set to a "1", or the OEN pin is at a
logic LOW level, output pins can be selectively put in the high impedance state using the
additional software control bits OENC[1:0].

This is default setting.*

This will enable the output pins to be three-stated regardless the state of the OEN
pin.

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Port A and B Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0Eh

PORTAB

DIRB

DATAB[2:0]

DIRA

DATAA[2:0]

Port A data select. For internal gate signal locations.

Port A is disconnected from the internal signal path.*

Port A is connected to the BPG (back porch gate) signal.

Port A is connected to the SYG (sync tip gate) signal.

Port A is connected to the CBG (color burst gate) signal.

Port A is connected to the CBGW (color burst gate wide) signal. The CBGW is high
for the entire color burst period.

Port A is connected to the SLICE (mid way of the sync tip) signal.

Port A is connected to the VBI (vertical blanking interval) signal.

Port A is connect to the GPPORT bit.

DIRA

Port A direction control.

Port A is configured as input. The input is connected directly to the signal path
selected by DATAA[2:0]. The internally generated gate signal is disconnected from
the signal path.*

Port A is an output and is driven by the internally generated signal as selected by
DATAA[2:0].

DATAB[2:0]

Port B data select. For internal gate signal locations.

Port B is disconnected from the internal signal path.*

Port B is disconnected.

Port B is connected to the FH2 (twice per line pulses) signal.

Port B is connected to the FS_PULSE (falling edge of the sync tip) signal.

Port B is connected to the VBI_CVBS (VBI raw ADC) signal. This signal is high for
those lines that output data directly from the ADC (not YUV or RGB data).

Port B is connected to the VBI_PROC (VBI sliced) signal. This signal is high for
those video lines that output sliced VBI data.

Port B is connected to the COFF signal.

Port B is disconnected.

DIRB

Port B direction control.

Port B is configured as input. The input is connected directly to the signal path
selected by DATAB[2:0]. The internally generated gate signal is disconnected from
the signal path.*

Port B is an output and is driven by the internally generated signal as selected by
DATAB[2:0].

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Luma Control Register

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x0F

LUMA

UNIT

RGBH

PED

HYBWR

CTRAP

HYPK[1:0]

Luminance horizontal peaking control around 3 MHz.

Less than nominal peaking.* (0 dB)

Nominal peaking. (2 dB)

Increased peaking. (4 dB)

Maximum peaking. (8 dB)

CTRAP

Chroma trap (notch filter) in the luma path.

No chroma trap. This mode is recommended for S-video or component video input.*

Chroma trap is enabled.

HYBWR

Luminance horizontal bandwidth reduction control.

Full bandwidth.*

Reduced bandwidth.

PED

Enable gain correction for 7.5 blank-to-black setup (pedestal).

No pedestal. 0% = Y code 16. 100% = Y code 235.*

Gain adjusted for 7.5% blank-to-black setup (pedestal). 7.5% = Y code 16. 7.5% -
100% input produce Y code 16 - 235.

RGBH

High gain to produce full range Y for 0% (or 7.5% if PED = 1) to 100% input.

Black (0% or 7.5%) to peak white(100%) input produce Y code 16 to 235.*.

Black (0% or 7.5%) to peak white(100%) input produce Y code 0 to 255.

UNIT

When PED and RGBH are both set to a "1", setting this bit to a "1" produces a unit gain for
CCIR 601 digital input (INPSL[1:0] = 1).

Luma DC gain is controlled by PED and RGBH as described for each bit.*

Luma DC gain is unity for CCIR 601 digital input.

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Contrast Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x10

CON

CON[7:0]

This 8-bit register contains a 2's compliment number for contrast control.

Brightness Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x11

BRT

BRT[7:0]

Brightness control register. The number contained in the register is 2's compliment.

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Chroma Control Register A

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x12

CHROMA

ACCFRZ

PALM

PALN

CBW

CORE[1:0]

CKILL[1:0]

Color kill.

Auto detect mode. If color burst is too low or no color burst, chroma data is forced to
code 128.*

Chroma is always ON.

Chroma data is always forced to code 128.

CORE[1:0]

Chroma data coring.

No coring.

Chroma data within the range 128+/-1, inclusive, will be force to 128.

Chroma data within the range 128+/-3, inclusive, will be force to 128.*

Chroma data within the range 128+/-7, inclusive, will be force to 128.

CBW

Chroma bandwidth control.

Chroma 3 dB bandwidth is 850 kHz.*

Chroma 3 dB bandwidth is 550 kHz.

PALN

Select color tracking for PAL-N, or NTSC-N when input field rate is 50 Hz and Fsc is 3.58 MHz.

Select NTSC-N.*

Select PAL-N.

PALM

Select color tracking for PAL-M or NTSC-M when input field rate is 60 Hz.

Select color tracking for NTSC-M.*

Select color tracking for PAL-M.

ACCFRZ

Chroma gain tracking freeze control.

Chroma gain tracks the input. Color saturation can be adjusted with SAT.*

Chroma gain freezes at the current saturation level.

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Chroma Control Register B

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x13

CHROMB

CDLY[3:0]

SCHCMP[3:0]

Phase constant compare value for color burst phase relative to sync tip. Each step is 22.5
degrees with the value of 0 equal to 0 degree.

CDLY[3:0]

Chroma path group delay relative to the luma path (in unit of CK):

No delay.

-0.5

0.5

1.5

2.5

-4

-4.5

-3

-3.5

-2 *

-2.5

-1

-1.5

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Chroma Demodulation Control and Status

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x14

DEMOD

FSCDET

SECDET

CDMLPF CTRACK

MNFSC[1:0]

MNSECAM[1:0]

Enable manual SECAM input detection.

Detection of SECAM input is automatic.*

Force the chip to assume input is not SECAM.

Force the chip to assume input is SECAM.

MNFSC[1:0]

Enable manual Fsc detection.

Detection of Fsc frequency is automatic.*

Force chip to assume input Fsc is 4.43 MHz or 4.286 MHz.

Force chip to assume input Fsc is 3.58 MHz.

CTRACK

Chroma frequency tracking mode.

Chroma frequency tracking is based on the field rate and Fsc.*

Chroma frequency tracking is based on field rate only.

CDMLPF

Bypass the LPF in the chroma demodulator.

Chroma data pass through the LPF for color demodulation.*

Chroma data bypass the LPF. This setting is used for component video input.

SECDET

SECAM detection (read only).

Chip did not detect SECAM input.

Chip detected SECAM input.

FSCDET

Color subcarrier detection (read only).

Chip detected 4.43 MHz or 4.286 MHz Fsc.

Chip detected 3.58 MHz Fsc.

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Color Saturation Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x15

SAT

SAT[7:0]

Color saturation control register. Register content is in 2's complement if TSTCGN=0. 0 value
corresponds to nominal saturation.

Hue Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x16

HUE

HUE[7:0]

Hue control register. The register content is in 2's compliment format. It covers the range from
-180° to +178.59° degree. The resolution is 1.41°/LSB.

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Vertical Processing Control A

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x17

VERTIA

MNYCMB

YCMBCO[2:0]

VRT2X

VCTRL[2:0]

Luminance vertical filter control.

Scaler uses LPF path, comb uses HPF.*

Scaler uses full bandwidth, comb is disabled.

Scaler is disabled, comb uses full bandwidth.

Scaler uses LPF, comb is disabled.

Scaler is disabled, comb uses HPF.

VRT2X

3/5-tap vertical scaler filter select.

Select 3-tap vertical scaler filter.*

Select 5-tap vertical scaler filter. This option can be used only if horizontally cropped
line is less than or equal to 384 pixels.

YCMBCO[2:0]

Luma comb filter coefficients selection when the MNYCMB is set to "1".

[1/4 1/2 1/4].*

[3/8 1/2 1/8].

[1/2 1/2 0].

[1 0 0].

[0 1 0].

[1/2 0 1/2].

[0 1/2 1/2].

[1/8 1/2 3/8].

MNYCMB

Select between auto and manual luma comb filter coefficients.

Luma comb filter coefficients are automatically selected based on input video
standard.*

Luma comb filter coefficients are selected with YCMBCO[2:0].

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Vertical Processing Control B

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x18

VERTIB

HYLPF[2:0]

HYBWI

HYDEC

VSCLEN[1:0]

Vertical scaling enable.

Vertical scaling is enabled.*

Vertical scaling is disabled.

Vertical scaling is disabled. Video is 1-line delayed.

Vertical scaling is disabled. Video is 2-line delayed.

HYDEC

Luma path decimation filter enable.

Luma path decimation is enabled.*

Luma path decimation is disabled.

HYBWI

Luma path decimation filter bandwidth select.

Normal bandwidth.*

Bandwidth is 1 MHz higher.

HYLPF[2:0]

Horizontal luma LPF bandwidth control.

Full bandwidth.*

4.5 MHz bandwidth.

3.5 MHz bandwidth.

2.5 MHz bandwidth.

1.5 MHz bandwidth.

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Vertical Processing Control C

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x19

VERTIC

MNCCMB

CCMBCO[2:0]

ACMBEN

VYBW

EVAVEV

EVAVOD

Enable VAV signal output during ODD field.

VAV signal is disabled (always inactive) during ODD field.

VAV signal is enabled during ODD field.*

EVAVEV

Enable VAV signal output during EVEN field.

VAV signal is disabled (always inactive) during EVEN field.

VAV signal is enabled during EVEN field.*

VYBW

Luma vertical bandwidth control.

Full bandwidth.*

Reduced bandwidth.

ACMBEN

Enable luma active comb for NTSC.

Active comb is disabled.*

Active comb is enabled.

CCMBCO[2:0]

Manual chorma comb filter coefficients select.

Select the coefficient set [1/2 1/2 0] (if VRT2X = 0).*

Select the coefficient set [1/4 1/2 1/4] (if VRT2X = 0).

Select the coefficient set [0 1/2 1/2 0 0] (if VRT2X = 1).

Select the coefficient set [0 1/4 1/2 1/4 0] (if VRT2X = 1).

Select the coefficient set [1 0 0].

Select the coefficient set [0 1 0].

Select the coefficient set [0 0 1].

No output (disabled).

MNCCMB

Chroma comb filter coefficients are selected automatically or manually.

Filter coefficients are automatically selected based on the selected video input
standard. SECAM must use this value.*

Filter coefficients are selected manually with CCMBCO[2:0].

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Horizontal Scaling Ratio

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x1A

HSCLL

HSCL[6:0]

CMBMOD

0x1B

HSCLH

HSCL[14:7]

CMBMOD

This bit controls when comb is enabled internally.

Comb is enabled by the internal signal COMB_EN.*

Comb is enabled when VAV is active.

HSCL[14:0]

The 15-bit register defines a horizontal scaling ratio of HSCL[14:0]/2

. Any change to this

value will become effective during the next vertical sync.

Vertical Scaling Ratio

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x1C

VSCLL

VSCL[5:0]

ACMBCO ACMBRE

0x1D

VSCLH

VSCL[13:6]

ACMBRE

Active comb filter threshold select.

High threshold.*

Low threshold.

ACMBCO

Active comb filter coefficient set select.

Use the set of coefficients for 100% comb.*

Use the set of coefficients for 75% comb.

VSCL[13:0]

The 14-bit register defines a vertical scaling ratio of VSCL[13:0]/2

. Any change to this value

will become effective during the next vertical sync.

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Output Control A

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x1E

OFMTA

GAMEN[1:0]

OENC[1:0]

OFMT[3:0]

Digital video output format select. 16 and 24 bit data are output at CK2 clock rate. 8 bit data are
output at CK clock rate.

16-bit YCbCr 4:2:2 output on the Y and C output ports.*

12-bit YCbCr 4:1:1 output on the Y and C output ports.

8-bit YCbCr 4:2:2 without embedded timing reference codes.

8-bit YCbCr 4:2:2 with embedded timing reference codes.

24-bit YCbCr 4:4:4.

16-bit RGB 565.

24-bit RGB 888 with linear bit ordering.

24-bit RGB 888, bit ordering is an extension of the 16-bit RGB 565 format.

Same as mode 2 with the additional of 8-bit YCbCr 4:2:2 data output on the EXV
port. While the Y port can be scaled down, the EXV port will always be a full size
picture.

Same as 8 with the addition of SAV and EAV codes.

output Y ADC data all the time (including syncs) on the Y port, C port is non-scaled
656 data with no timing codes.

Output Y ADC data all the time (including syncs) on the Y port,
Output Cb ADC data all the time (including syncs) on the C port,
Output Cr ADC data all the time (including syncs) on the EXV port,

OENC[1:0]

When either the OEN pin is low or the OUTHIZ is a "1", these two bits will determine which
output pins are three-stated.

All video data pins are input(EXV) and Hi-Z(Y,C)

All pins are input(I/O Pins) and Hi-Z(All output pins) except CK, CK2 pins.

All pins listed above, plus CK and CK2 are input(CK), Hi-Z(CK2)

Always output data.

GAMEN[1:0]

Gamma correction enable.

No gamma correction.*

Gamma correction is applied to Y/G data.

Gamma correction is applied to U/B and V/R data.

Gamma correction is applied to Y/G, U/B, and V/R data.

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Output Control B

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x1F

OFMTB

VSVAV

EVAND[1:0]

EVHS1

EVHAV

EVEHAV

EVAVG

EVANDL

EVAVG

Gate EVAV with VAV before sending to output.

EVAV is not gated with VAV. EVAV may be active outside of active VAV region.*

EVAV is gated with VAV. EVAV can be active only when VAV is active.

EVEHAV

Additional qualifier for EHAV.

No additional qualifier.*

EHAV uses qualifier from EVAND[1:0].

EVHAV

Additional qualifier for HAV.

No additional qualifier.*

HAV uses qualifier from EVAND[1:0].

EVHS1

Additional qualifier for HS1.

No additional qualifier.*

HS1 uses qualifier from EVAND[1:0].

EVAND[1:0],
EVANDL

Qualifier signal that defines active video lines. This control enables 656 codes, HAV, EHAV and
HS1.
EVANDL is the EVAND LSB. These three bits are grouped together and explained below

Qualifier is active for all lines.*

Qualifier is EVAV. -- Any line during vertical active or blank will be output.

Qualifier is EVAV and VAV -- All lines during vertical blank (VAV==0) and all lines
when EVAV is active during vertical active will be output.

Qualifier is VAV -- All lines during vertical active will be output.

Qualifier is EVAV and VAV -- All lines that EVAV is active during vertical active will
be output.

Qualifier is EVAV, VAV and VBI_RAW_EN -- All lines as in option 4 plus the VBI
RAW ADC lines.

Qualifier is EVAV, VAV, VBI_RAW_EN and VBI_SLC_EN-- All lines as in option 5
plus the VBI Sliced Lines.

All VBI sliced and VBI RAW Lines only.

VSVAV

Enable VAV to be output to VS.

Output normal VS.*

VS has the same output as VAV

(this affects the V flag in 656 code)

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VBI Decoder Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x20

VBICTL

VBCVBS

VYFMT[1:0]

VBINSRT

ODDEN

EVENEN

ODDOS[1:0]

Line offset for ODD field. See also VBIL[15:0].

ODD field line offset is -1 compared to EVEN field.*

No offset.

ODD field line offset is 1 compared to EVEN field.

ODD field line offset is 2 compared to EVEN field.

EVENEN

VBI data processing for EVEN field.

No processing.*

VBI processing is enabled for EVEN field.

ODDEN

VBI data processing for ODD field.

No processing.*

VBI processing is enabled for ODD field.

VBINSRT

Enable VBI data to be output on the Y bus.

VBI data is not output on the Y bus.*

VBI data is output on the Y bus.

VYFMT[1:0]

When VBINSRT = 1, these bits control how VBI data are output on the Y bus.

1 bit on Y7 per CK2 clock.*

1 bit on Y7 plus a "1" on Y3 per CK2 clock.

4 bits on Y7..Y4, with first bit on Y7, last bit on Y4, plus a "1" on Y3 per CK2 clock.

8 bits on Y7..Y0, with first bit on Y7, last bit on Y0, per CK2 clock.

VBCVBS

Enable digitized CVBS data from ADC to be output for the selected VBI line instead of sliced
VBI data. The new VBIMID bit allows simultaneous output (line by line bases) of sliced data
and raw ADC data.

Output sliced VBI data for any line whose VBIL value ~= 0.*

Output digitized CVBS data for any line whose VBIL value ~=0.

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First Decoded Close-Caption Data Byte (Read Only)

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x21

CCDAT1

CCDAT1

This byte contains the first byte of the decoded close-caption data as defined in EIA-608. In
order for this register to receive the CC data, VBINSRT must be programmed to a "1", and
VYFMT[1:0] must be programmed with the value 3. The same applies to CCDAT2. For normal
NTSC Closed Caption decoding, ODDEN should be set to a "1", VBIL12 should be
programmed with the value 1.

Second Decoded Close-Caption Data Byte (Read Only)

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x22

CCDAT2

CCDAT2

This byte contains the second byte of the decoded close-caption data as defined in EIA-608.

VBI Data Decoding

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x23

VBIL30

VBIL3

VBIL2

VBIL1

VBIL0

0x24

VBIL74

VBIL7

VBIL6

VBIL5

VBIL4

0x25

VBIL118

VBIL11

VBIL10

VBIL9

VBIL8

0x26

VBIL1512

VBIL15

VBIL14

VBIL13

VBIL12

VBIL0..VBLI15

These 16 2-bit numbers select how the chip should decode the VBI data for each VBI line. For
60 Hz video, VBIL1 through VBIL15 correspond to lines 10 through 24 in the ODD field, and
lines 273 through 286 in the EVEN filed for NTSC (refer to NTSC line numbering convention).
For 50 Hz video, VBIL1 corresponds to line 7 in the ODD field, and line 320 in the EVEN field.
VBIL0 is used for all other lines not covered by VBIL1 through VBIL15.

Decode normal video.*

Decode Closed Caption data.

Decode Teletext data.

Decode WSS data.

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Teletext Frame Alignment Pattern

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x27

TTFRAM

TTFRAM[7:0]

User programmable Teletext frame alignment pattern.

UV Offset Adjustment

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x29

UVOFFH

TSTCLC

TSTCGN

TSTCFR

UOFFST[5:4]

VOFFST[5:4]

0x2A

UVOFFL

UOFFST[3:0]

VOFFST[3:0]

VOFFST[5:0],
UOFFST[5:0]

These two 6-bit 2's compliment values are for offset adjustment to the U and V components of
the chroma data. The resolution is 1/4 LSB of the 8-bit U and V.

TSTCFR

Chroma frequency tracking control.

Chroma frequency tracking is enabled.*

Chroma frequency tracking is open loop.

TSTCGN

Chroma gain control.

Chroma gain tracks input.*

Chroma gain is controlled by SAT only.

TSTCLC

Cloche filter bypass.

Cloche filter is enabled for SECAM input.*

DC bypass of the cloche filter.

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U Component Gain Adjustment

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x2B

UGAIN

UGAIN[7:0]

U component gain adjustment. The nominal value is 0.

V Component Gain Adjustment

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x2C

VGAIN

VGAIN[7:0]

V component gain adjustment. The nominal value is 0.

VAV Begin

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x2D

VAVB

VAVB[6:1]

VAVOD0

VAVEV0

The LSB for VAVB and VAVE for the even field.

VAVOD0

The LSB for VAVB and VAVE for the odd field.

VAVB[6:1]

The 6 MSB's of a 7-bit unsigned number which defines the start of VAV. The value "0"
corresponds to line 4.

VAV End

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x2E

VAVE

VAVE[8:1]

The 8 MSB's of a 9-bit unsigned number which defines the end of VAV. The value "0"
corresponds to line 4.

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Chroma Tracking Control Register

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x2F

CTRACK

DMCTL[1:0]

CGTC[1:0]

CFTC[1:0]

Chroma frequency tracking time constant.

Slower.*

Slow.

Fast.

Faster.

CGTC[1:0]

Chroma gain tracking time constant.

Slower.*

Slow.

Fast.

Faster.

DMCTL[1:0]

Chroma demodulation bypass mode.

Chroma demodulation is enabled.*

Chroma demodulation is bypassed for digital YCbCr input.

Chroma demodulation is bypassed for analog YPbPr input. Cb path is phase
delayed by one half of CK2 clock period.

Chroma demodulation is bypassed for analog YPbPr input. Cr path is phase
delayed by one half of CK2 clock period.

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Timing Signal Polarity Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x30

POLCTL

EVAVPL

VSPL

ODDPL

HAVPL

EHAVPL

HS2PL

VAVPL

HS1PL

HS1 polarity.

Active high.*

Active low.

VAVPL

VAV polarity.

Active high.*

Active low.

HS2PL

HS2 polarity.

Active high.*

Active low.*

EHAVPL

EHAV polarity.

Active high.*

Active low.

HAVPL

HAV polarity.

Active high.*

Active low.

ODDPL

ODD polarity

(this also affects the F bit in 656 code)

Active high.*

Active low.

VSPL

VS polarity

(this also affect the V bit in 656 code)

Active high.*

Active low.

EVAVPL

EVAV polarity.

Active high.*

Active low.

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Reference Code Insertion Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x31

REFCOD

YCRANG

Digital video output range control.

Y and C ranges are limited to 1 - 254; R, G, and B ranges are limited to 1 - 254.*

Y range is limited to 16 - 235; C range is limited to 16 - 240; R, G, and B ranges are
limited to 16 - 240.

Invalid Y Code

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x32

INVALY

INVALY[7:0]

User programmed code to be output for Y data when HAV is active but EHAV is inactive.

Invalid U Code

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x33

INVALU

INVALU[7:0]

User programmed code to be output for U data when HAV is active but EHAV is inactive.

Invalid V Code

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x34

INVALV

INVALV[7:0]

User programmed code to be output for V data when HAV is active but EHAV is inactive.

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Unused Y Code

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x35

UNUSEY

UNUSEY[7:0]

User programmed code to be output for Y data when HAV is inactive.

Unused U Code

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x36

UNUSEU

UNUSEU[7:0]

User programmed code to be output for U data when HAV is inactive.

Unused V Code

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x37

UNUSEV

UNUSEV[7:0]

User programmed code to be output for V data when HAV is inactive.

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Extra Control Bits for the S5D2650 Version

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x38

EXCTRL

PERMIN ENINCST

SLEV[1:0]

OFFST_CONT[1:0]

CLEVEL

Programmable CKILL burst level select bit.

Burst peak level is 11 IRE.*

Burst peak level is 5.5 IRE.

OFFST_CONT
[1:0]

Y-ADC, C-ADC Offset time control

0.5us Y-ADC/1.0us C-ADC Offset timing

1.0us Y-ADC/2.0us C-ADC Offset timing*

2.0us Y-ADC/3.0us C-ADC Offset timing

3.0us Y-ADC/4.0us C-ADC Offset timing

SLEV[1:0]

HSYNC Slice level control for robust sync detection

Slice level fixed to 50%(Same as KS0127B)*

Slice level fixed to 88%

Slice level fixed to 25% or 75% variable, in case of input condition

Auto slice level based on back porch and sync tip.

ENINCST

Scaler enable control bit during VBI.

Scaler on during VBI interval (defined by VAV).*

Scaler off during VBI interval.

PERMIN

Integration time for auto slice level creation

Fast*

Slow

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Tracking Configuration Controls A

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x39

TRACKA

STCTRL MAC_DET VCR_DET

VCR_LEV[1:0]

ATCTRAP VBCTRAP AGCLSB

AGCLSB

AGC LSB for control of the 9 bit AGC gain value. This bit only write to AGC when AGCFRZ is
1.

Write `0' to AGC 9 bit control LSB if AGCFRZ = 1.*

Write `1' to AGC 9 bit control LSB if AGCFRZ = 1.

VBCTRAP

Chroma trap enabled during the VBI.

Chroma trap is controlled by CTRAP only.*

Chroma trap enabled during VBI.

ATCTRAP

Auto Chroma Trap on luma path when VCR input is detected.

Chroma trap is controlled by CTRAP only.*

If VCR type input is detected, then CTRAP is enabled.

VCR_LEV

Set the Fh variation from nominal for detection of VCR type input.

50 PPM.*

100 PPM.

200 PPM.

400 PPM.

VCR_DET

Status bit. Detect input that is not SCH locked such as consumer type VCR (Read only).

SCH locked video.

Color burst not locked to Fh (VCR).

MAC_DET

Status bit. Macrovision Encoded Data detected as input video source (Read only).

Standard video detected.

Macrovision Encoded data detected.

STCTRL

State machine transition control.

Normal state machine transitions.*

Steady state sync level removed as condition for lock.

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VBI Control Register B

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x3A

VBICTLB

VBISWAP

TT_SYS[1:0]

VBIMID

NEW_CC CC_OVFL YOFFENB COFFENB

COFFENB

Disable control for the C-path clamp control.

C-path clamp works as normal.*

C-path clamp disabled.

YOFFENB

Disable control for the Y-path clamp control.*

Y-path clamp works as normal.*

Y-path clamp disabled.

CC_OVFL

Defines when the current CCDAT1,2 data has over written previous data that was not read.
(Read Only)

Current data has not generated an overflow condition.

Current data as written over data that was not read.

NEW_CC

Defines when new Closed Caption data is ready for reading from the CCDAT1,2 bytes. (Read
Only)

Current data in CCDAT1,2 has already been read.

Current data in CCDAT1,2 is new.

VBIMID

Changes function of WSS enable (per line bases during VBI) to a raw CVBS enable.

When VBIL(0-15) = 3, current line is enabled for WSS slicing.*

When VBIL(0-15) = 3, current line is enabled for raw ADC output.

TT_SYS

Select Teletext input system when auto detect is not possible.

Auto Teletext Select.*

Teletext System B.

Teletext System C.

Teletext System D.

VBISWAP

Reverse the bit order for data output from the closed caption or Teletext slicer.

Same as KS0127 -- First bit sliced is located in MSB position.*

First bit sliced (in time) is located in LSB position.

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Tracking Configuration Controls B

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x3B

TRACKB

ALT656

VBI_PH

VBI_FR

PH_CTRL VNOISCT

AGC_LPG[1:0]

AGC_LKG

AGC gain tracking loop time constant for initial tracking mode.

Same as steady state time constant.*

2X faster than selected steady state time constant.

AGC_LPG

AGC gain steady state tracking loop time constant.

Fastest.*

Fast.

Slow.

Slowest.

VNOISCT

Vertical sync noise control enable.

Vertical sync adjusts with all sync phase changes.*

Vertical sync large phase errors must occur for 4 lines to activate a phase change.

PH_CTRL

Controls phase detector response.

Syncs after the "0" point reference have priority.*

Syncs prior to "0" point reference have priority.

VBI_FR

Disables frequency compensation for VCR head switch lines only.

Frequency tracking independent of this control.*

Frequency tracking disabled for VCR head switch lines.

VBI_PH

Enables phase compensation for VCR head switch lines only.

Phase tracking independent of this control.*

Phase tracking enabled for VCR head switch lines only.

ALT656

Alternate 656 Vertical blank location for 50 Hz video.

Vertical blank size per the ITU 656 Specification (ends at 656 digital line 23).*

Vertical blank size same as 60 Hz (ends at 656 digital line (50 Hz) 6).

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RTC Genlock output signal control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x3C

RTC

RTC_DTO RTC_PID SEC_POL TDMOD

VCO_BIAS[1:0]

PUMP_BIAS[1:0]

PUMP_BIAS
[1:0]

PLL Block Charge Pump bias current control

VCO_BIAS[1:0]

PLL Block VCO bias current control

TDMOD

Test bit for chroma demodulation mode.

Normal operation.*

Test mode.

SEC_POL

SECAM ID Polarity Control

Normal*

Inversion

RTC_PID

Polarity control for PAL ID transferred within the RTC data stream.

Same polarity as default PID pin.*

Inverted polarity.

RTC_DTO

Enables a DTO reset inside the S5D2650 and sends a DTO reset within the RTC data stream.
Function is activated on the rising edge of RTC_DTO.

Function disabled.*

Function enabled one time when set to 1.

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Command Register E

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x3D

CMDE

ODFST

VSALG

HCORE[1:0]

CHIPREVID

Four additional bits for determination of current Revision and differentiation from the S5D2650

KS0127B

S5D2650

HCORE

Luma path horizontal coring. Noise limiter for high frequency portion of luma.

Coring function is disabled.*

1 bit of coring.

2 bits of coring.

4 bits of coring.

VSALG

Vertical scaling line dropping algorithm.

Vertical scaling drops the same lines in the Odd and Even fields -- good for fast
motion video.*

Vertical scaling drops lines based on the final de-interlaced video. This is a better
vertical scaling but may be sensitive to fast motion video.

ODFST

Alternate the first scaling line between Odd and Even fields.

Even field is the first scaled field.*

Odd field is the first scaled field.

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VS Delay Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x3E

VSDEL

TR_MS

NOVIDC

VSDEL[5:0]

When the chip is programmed for digital video input operation, this register provides an offset
for the internal line counter to align with input video (VS can be either from the VS pin or from
embedded timing code). The register content is unsigned.

NOVIDC

Allows NOVID bit to be output to PORTB (pin 24).

Normal operation.*

The NOVID bit is output to PORTB if DATAB[2:0]=1 and DIRB=1.

TR_MS

Enable alternative initial tracking mode state machine.

Normal operation - Horizontal tracking mode is controlled by the HFSEL[1:0] bits.*

Variable tracking modes during locking time.

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Command Register F

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x3F

CMDF

CTRAPFSC

VIPMODE

EVAVY

UVDLEN

UVDLSL

REGUD

TASKB

CBWI

Chroma bandwidth increase. This function should be used for digital video input mode only.

Normal chroma bandwidth.*

Increased chroma bandwidth.

TASKB

Select between task A and B as described in "VIP Specification V. 1.0".

Select CCIR 656 timing codes (T-bit is always 1).*

Select between task A and B when VBI data is output. If active video is output, T-bit
is set to 1(task A). If VBI data is output, T-bit is set to 0 (task B).

REGUD

Control register update control.

Registers are updated immediately after being written to.*

The following registers and register bits are updated only during the start of vertical
sync after they are written to:
Index 0x02, indices 0x17 through 0x1D, bit 0 of index 0x04, bits [2:0] and [6:4] of
index 0x0E.

UVDLSL

U or V delay control when UVDLEN is set to 1.

V is delayed by 1 CK period.*

U is delayed by 1 CK period.

UVDLEN

Enable the function of UVDLSL.

UVDLSL is disabled.*

UVDLSL is enabled.

EVAVY

Control the output of INVALY, INVALU, and INVALV codes when EVAV is inactive.

Output of these codes are not affected by EVAV.*

These codes are output when EVAV is inactive (line is being dropped by the vertical
scaler).

VIPMODE

Allows transfer of hardware sliced VBI data as ancillary data during the following line's
horizontal blanking period.

Standard S5D2650 original sliced VBI data transfer.*

Optional ancillary sliced VBI data transfer.

CTRAPFSC

Enable chroma trap location based on Fsc frequency instead of field rate.

Chroma trap based on field rate.*

Chroma trap based on detected Fsc frequency.

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Gamma Base

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x40

GAMMA0

GAMMA0[7:0]

0x41

GAMMA1

GAMMA1[7:0]

0x5F

GAMMA31

GAMMA31[7:0]

GAMMA0
-GAMMA31

Gamma correction base. The desired output for 8*N, where N = 0, .., 31, is programmed into
GAMMAN. Note that data written into these addresses are simultaneously written into
addresses 0xC0 through 0xDF.

Gamma Correction Delta

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x60

GAMMAD0

GAMMAD0[5:0]

0x61

GAMMAD1

GAMMAD1[5:0]

0x7F

GAMMAD31

GAMMAD31[5:0]

GAMMAD0
..GAMMAD31

The Nth location of the 32 locations is programmed with a 6-bit unsigned number which
represents the gamma correction delta for the gamma bases N and N + 1. The last location
will contain the gamma correction delta for gamma base 31 and presumed base 32 which has
the value of 256. Note that data written into these addresses are simultaneously written into
addresses 0xE0 through 0xFF.

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U/V Gamma Base

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0xC0

GAMUV0

GAMUV0[7:0]

0xC1

GAMUV1

GAMUV1[7:0]

0xDF

GAMUV31

GAMUV31[7:0]

GAMUV0
-GAMUV31

U and V gamma correction base. The desired output for 8*N, where N = 0, .., 31, is
programmed into GAMUVN.

U/V Gamma Correction Delta

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0xE0

GAMUVD0

GAMUVD0[5:0]

0xE1

GAMUVD1

GAMUVD1[5:0]

0xFF

GAMUVD31

GAMUVD31[5:0]

GAMUVD0
..GAMUVD31

U and V gamma correction delta. The Nth location of the 32 locations is programmed with a
6-bit unsigned number which represents the gamma correction delta for the gamma bases N
and N + 1. The last location will contain the gamma correction delta for gamma base 31 and
presumed base 32 which has the value of 256.

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ABSOLUTE MAXIMUM RATINGS

Notes: 1.Absolute maximum ratings are limiting values applied individually while all other parameters are within

specified operating conditions.

2.Functional operation under any of these conditions is not implied.
3.Applied voltage must be current limited to a specified range.

OPERATING CONDITIONS

Characteristics

Symbol

Value

Units

3.3-V supply voltage (measured to VSS)

DD3

-0.5 to + 3.8

1.8-V supply voltage (measured to VSS)

DD1

-0.5 to + 2.7

Voltage on any digital pin

-0.5 to

DD3

+0.5)

Ambient operating temperature (case)

-40 to + 100

°C

Storage temperature

-65 to + 150

°C

Junction temperature

150

°C

Vapor phase soldering (1 min.)

Tvsol

220

°C

Characteristics

Symbol

Min

Typ

Max

Units

3.3-V supply voltage (measured to VSS)

DD3

3.0

3.3

3.6

1.8-V supply voltage (measured to VSS)

DD1

1.65

1.8

1.95

Thermal Impedance (case to ambient)

°C/W

Thermal Impedance (junction to case)

°C/W

Ambient operating temperature, still air

°C

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ELECTRICAL CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Units

Supply

+3.3V (Analog+I/O Buffer), normal operation

DD3

120

150

+1.8V (Digital Core), normal operation

DD1

+3V (Analog+I/O Buffer), power down mode

DD3

+1.8V (Digital Core), power down mode

DD1

Analog Characteristics

Integral linearity error (AGC/ADC only)

I-ADC

1.0 lsb

Differential linearity error (AGC/ADC only)

D-ADC

0.5 lsb

Total harmonic distortion (4 MHz full scale)

THD

Signal to noise ratio (4 MHz full scale)

SNR

Analog bandwidth (50 IRE to 3 dB point)

MHz

Input voltage range (peak-peak) 100 IRE input

VI(PP)

0.5

1.5

Input resistance AY0-ACB1

200

Input capacitance for analog video inputs

Charge current for offset control

OFF

±4

Cross talk between analog inputs

-42

-50

Video Performance

Luminance frequency response (maximum
variation to 4.2 MHz - multi burst)

LUMA

1.5

Differential gain - complete chip (Modulated 40
IRE ramp)

1.5

Differential phase - complete chip (Modulated
40 IRE ramp)

1.0

degree

Chrominance frequency response (3 dB point) -
CBWR=0/1

CHROMA

800/500

kHz

Chroma nonlinear gain distortion (NTC-7
Combination)

NGD

Chroma nonlinear phase distortion (NTC-7
Combination)

NPD

1.25

degree

Chroma to luma intermodulation (NTC-7
Combination)

IRE

Chroma luma gain equality (NTC-7 Composite) DEL

±20

Chroma luma delay equality (NTC-7 Composite) AMP

98-101

Noise level for unified weighting 10 kHz-5 MHz
(100 IRE unmodulated ramp)

LUMA

-58

Chroma AM noise (red field)

CAM

-60

Chroma PM noise (red field)

CPM

-54

ELECTRONICS

S5D2650 Data Sheet

MULTIMEDIA VIDEO

PAGE 91 OF 95

7/18/03

Digital I/O Characteristics

Input low voltage

0.8

Input high voltage

2.0

Schmitt trigger, negative going threshold
(SCLK,SDAT)

VT-

0.8

Schmitt trigger, positive going threshold
(SCLK,SDAT)

VT+

2.0

Input low current (V

= VSS)

-10

+10

Input high current(V

= VDD)

-10

+10

Digital output low voltage (I

=1~24mA)

0.4

Digital output high voltage (I

=-1 ~ -24mA)

2.4

three-state output leakage current

-10

Digital output capacitance

OUT

Maximum capacitance load for digital data pins C

L-DATA

Maximum capacitance load for CK and CK2
outputs

L-CK

Timing Characteristics - Digital Inputs

XTALI input pulse width low

pwlX

XTALI input pulse width high

pwhX

Clock and Data Timing

Analog video input to digital video output delay

dCHIP

120

Pulse width high for CK

pwhCK

18.5

Pulse width high for CK2

pwhCK2

Delay from rising edge of CK to CK2

CK2

Delay from rising edge CK to data change
(including pins Y0-Y7, C0-C7, HAV, VAV, EHAV,
EVAV, HS1, HS2, VS, ODD, PID, SCH)

(CK is output)

(CK is input)

Minimum hold time from rising edge of CK for
data output)

0.3

Timing Characteristics -IIC Host Interface

SCLK clock frequency

SCLK

400

kHz

Capacitive load for each bus line

400

Hold time for START condition

hSTA

0.6

Setup time for STOP condition

sSTO

0.6

Rise and fall times for SCLK and SDAT

, t

300

SCLK minimum pulse width low

pwlSCLK

1.3

SCLK minimum pulse width high

pwhSCLK

0.6

SDAT setup time to rising edge of SCLK

SDAT

100

Characteristics

Symbol

Min

Typ

Max

Units

ELECTRONICS

S5D2650 Data Sheet

MULTIMEDIA VIDEO

PAGE 93 OF 95

7/18/03

Figure 41. Data Output

Figure 42. Analog Video Input to Digital Video Output Delay

Figure 43. IIC Host Interface Detailed Timing

pwhCK2

emT

Y,C,HAV
VAV,HS,VS
ODD,PID,
EHAV,
EVAV

CK2

pwhCK

Blank

Analog Video
Input

Digital Video
Output

Active video

dCHIP

SDAT

SCLK

BUF

sSDAT

pwlSCLK

pwhSCLK

hSDA

sSTO

hSDAT

ELECTRONICS

S5D2650 Data Sheet

MULTIMEDIA VIDEO

PAGE 94 OF 95

7/18/03

Application Circuit

S5D2650X

VDD3

VDDD

VDDA

VDDB

VDDP

VDD1

VDD3

VDD1

VDD3

VDD1

A Y 0

A Y 1

A C R 0

A C R 1

A C B 0

A C B 1

Y 7
Y 6
Y 5
Y 4
Y 3
Y 2
Y 1
Y 0

C 7
C 6
C 5
C 4
C 3
C 2
C 1
C 0

V A V

E V A V

E H A V

P I D

C K

C K 2

O D D

V S

H A V

H S 1

C C D A T

C C E N

3
4

5
1 7
1 8

2 1

2 2

2 3

2 5
2 6

7 3
7 4

4 4
3 9
3 8
3 7
3 6
3 5
3 4
3 3

5 6
5 5
5 4
5 3
4 8
4 7
4 6
4 5

8 4

8 6

8 8

9 0

9 2

9 4

T E S T 1

3 0

0 . 1 u F

V C C

FE.BEAD

1 . 8 V

To Frame Buffer Controller

To Frame Buffer

Analog Video Input

VSS

S C L K
S D A T

A E X 0

A E X 1

7 5

7 2

6 9
7 0

IIC Interface

T E S T 0

2 9

S C A N E N

3 1

T E S T 2 5 7

H S 2 7 6

C O M P 2

9 7

1 0 u F

7 5

X T A L I

X T A L O

2 4 . 5 7 6 M H z

2 2 p F

E X V [ 7 : 0 ]

S C H ( P O R T B )

P O R T A

2 4

5 8

O E N

1 5

V C C

R S T B

1 0

C K E

3 2

1 0 K

1 3 . 5 M H z

VSS

100

VSS

0 . 1 u F

1 0 K

0 . 1 u F

FILT

9 9

1 0 p F

5 n F

8 0 K

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Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S5D2650

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S5D2650