þÿ

Data Sheet

Data Sheet, Rev. 1.7

95-SR-000-10-8L

Mobile DiskOnChip

Plus 16/32MByte

1.8V I/O Flash Disk, Protection and Security-Enabling Features

Highlights

Mobile DiskOnChip Plus 16/32MByte
(128/256Mbit) is one of the industry's most efficient
storage solutions, with the fastest write rates, the
smallest size and lowest power consumption.
Additionally, it offers advanced data protection and
security-enabling features. Based on a monolithic
(dual-die) chip that utilizes Toshiba's 0.16

µ NAND

technology, Mobile DiskOnChip Plus attains levels
of reliability that surpass competing products.

These characteristics make Mobile DiskOnChip Plus
ideal for meeting the growing demand for secure and
reliable data storage in mobile multimedia devices,
such as mobile phones and Personal Digital
Assistants (PDAs).

Mobile DiskOnChip Plus 16/32MByte features:

Exceptional read, write and erase performance

Advanced protection and security-enabling
features for data and code

Low voltage:

Core 3V

I/O 1.8V/3V auto-detect

Small form factor: 69-ball 9x12 mm Fine-Pitch
Ball Grid Array (FBGA)

NAND-based flash technology that enables high
density and small die size

Proprietary TrueFFS

technology for full hard

disk emulation, high data reliability and
maximum flash lifetime

Single-die chip: 16MByte
Dual -die chip: 32MByte with device cascade
options for up to 64MByte (512MBit) capacity

Programmable Boot Block with eXecute In Place
(XIP) functionality using 16-bit access, with
download support for more code

Configurable for 8/16/32-bit bus interface

Data integrity with Reed-Solomon-based Error
Detection Code/Error Correction Code
(EDC/ECC)

Deep Power-Down mode for reduced power
consumption

Support for all major mobile OSs, including:
Symbian OS, Windows CE, Smartphone 2002/3,
Pocket PC, Nucleus, OSE, and Linux

Performance

Burst read/write: 13.3 MB/sec

Sustained read: 1.7 MB/sec

Sustained write: 0.86 MB/sec

Protection and Security Enabling
Features

16-byte Unique Identification (UID) number

6KByte user-configurable One Time
Programmable (OTP) area

Two configurable write-protected and
read-protected partitions for data and boot code

Hardware data and code protection:

Protection key and LOCK# signal

Sticky Lock option for lock of boot partition

Protected Bad Block Table

Boot Capability

Programmable Boot Block with XIP
functionality to replace boot ROM:

1KB for 16MB devices

2KB for 32MB devices

Download Engine (DE) for automatic download
of boot code from Programmable Boot Block

Boot capabilities:

CPU initialization

Platform initialization

OS boot

Asynchronous Boot mode to boot CPUs that
wake up in burst mode

The following abbreviations are used in this document: MB for
MByte, Mb for Mbit.

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

Reliability

On-the-fly Reed-Solomon Error Detection
Code/Error Correction Code (EDC/ECC)

Guaranteed data integrity, even after power
failure

Transparent bad-block management

Dynamic and static wear-leveling

Hardware Compatibility

Configurable interface: simple SRAM-like or
multiplexed A/D interface

Compatible with all major CPUs, including:

ARM-based CPUs

Texas Instruments OMAP

Intel StrongARM/XScale

AMD Alchemy

Motorola PowerPCTM MPC8xx

Motorola DragonBall MX1

Philips PR31700

Hitachi SuperHTM SH-x

NEC VR Series

8-bit, 16-bit and 32-bit bus architecture support

TrueFFS Software

Full hard-disk read/write emulation for
transparent file system management

Identical software for all DiskOnChip capacities

Patented methods to extend flash lifetime,
including:

Dynamic virtual mapping

Dynamic and static wear-leveling

Support for all major OS environments,
including:

Symbian OS

Windows CE

Pocket PC

Smartphone

OSE

ATI Nucleus

Linux

Support for OS-less environments

8KByte memory window

Power Requirements

Operating voltage

Core: 2.5

to 3.6V

I/O (auto-detect):
1.65 - 1.95V or 2.5V - 3.6V

Current

Active: 25 mA (Typ.)

Deep Power-Down (Typ.):
10 µA (16MB)
20 µA (32MB)

Capacities

16MB (128Mb) with device-cascading option for
up to 64MB (512Mb)

32MB (256Mb) with device cascading option for
up to 64MB (512Mb)

Packaging

69-ball FBGA: 9 x 12 x 1.4 mm (max)

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

Table of Contents

Introduction ......................................................................................................................... 7

Product Overview................................................................................................................ 8

2.1

Product Description ...................................................................................................................... 8

2.2

Standard Interface ........................................................................................................................ 9

2.2.1

Ball Diagram.............................................................................................................................. 9

2.2.2

System Interface ..................................................................................................................... 10

2.2.3

Signal Description ................................................................................................................... 11

2.3

Multiplexed Interface................................................................................................................... 13

2.3.1

Ball Diagram............................................................................................................................ 13

2.3.2

System Interface ..................................................................................................................... 14

2.3.3

Signal Description ................................................................................................................... 15

Theory of Operation .......................................................................................................... 17

3.1

Overview..................................................................................................................................... 17

3.2

System Interface......................................................................................................................... 18

3.3

Configuration Interface ............................................................................................................... 18

3.4

Protection and Security-Enabling Features................................................................................ 18

3.4.1

Read/Write Protection............................................................................................................. 18

3.4.2

Unique Identification (UID) Number ........................................................................................ 19

3.4.3

One-Time Programmable (OTP) Area.................................................................................... 19

3.5

Programmable Boot Block with eXecute In Place (XIP) Functionality ....................................... 19

3.6

Download Engine (DE) ............................................................................................................... 19

3.7

Error Detection Code/Error Correction Code (EDC/ECC).......................................................... 20

3.8

Data Pipeline .............................................................................................................................. 20

3.9

Control & Status.......................................................................................................................... 20

3.10

Flash Architecture....................................................................................................................... 20

Hardware Protection ......................................................................................................... 22

4.1

Method of Operation................................................................................................................... 22

4.2

Low-Level Structure of the Protected Area ................................................................................ 23

Modes of Operation........................................................................................................... 24

5.1

Normal Mode .............................................................................................................................. 25

5.2

Reset Mode ................................................................................................................................ 25

5.3

Deep Power-Down Mode ........................................................................................................... 25

TrueFFS Technology......................................................................................................... 26

6.1

General Description .................................................................................................................... 26

6.1.1

Built-In Operating System Support ......................................................................................... 26

6.1.2

TrueFFS Software Development Kit (SDK) ............................................................................ 27

6.1.3

File Management .................................................................................................................... 27

6.1.4

Bad-Block Management.......................................................................................................... 27

6.1.5

Wear-Leveling ......................................................................................................................... 27

6.1.6

Power Failure Management.................................................................................................... 28

6.1.7

Error Detection/Correction ...................................................................................................... 28

6.1.8

Special Features through I/O Control (IOCTL) Mechanism.................................................... 28

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

6.1.9

Compatibility............................................................................................................................ 28

6.2

8KB Memory Window in Mobile DiskOnChip Plus 16MB........................................................... 29

6.3

8KB Memory Window for Mobile DiskOnChip Plus 32MB ......................................................... 30

Register Descriptions ....................................................................................................... 31

7.1

Definition of Terms...................................................................................................................... 31

7.2

Reset Values .............................................................................................................................. 31

7.3

Chip Identification (ID) Register.................................................................................................. 31

7.4

No Operation (NOP) Register..................................................................................................... 32

7.5

Test Register .............................................................................................................................. 32

7.6

DiskOnChip Control Register/Control Confirmation Register..................................................... 33

7.7

Device ID Select Register........................................................................................................... 34

7.8

Configuration Register................................................................................................................ 34

7.9

Output Control Register.............................................................................................................. 35

7.10

Interrupt Control.......................................................................................................................... 35

7.11

Toggle Bit Register ..................................................................................................................... 36

Booting from Mobile DiskOnChip Plus ........................................................................... 37

8.1

Introduction ................................................................................................................................. 37

8.2

Boot Procedure in PC-Compatible Platforms ............................................................................. 37

8.3

Boot Replacement ...................................................................................................................... 38

8.3.1

PC Architectures ..................................................................................................................... 38

8.3.2

Non-PC Architectures ............................................................................................................. 38

8.3.3

Using Mobile DiskOnChip Plus in Asynchronous Boot Mode................................................. 39

Design Considerations ..................................................................................................... 40

9.1

Design Environment ................................................................................................................... 40

9.2

System Interface......................................................................................................................... 41

9.2.1

Standard Interface................................................................................................................... 41

9.2.2

Multiplexed Interface............................................................................................................... 42

9.3

Connecting Signals..................................................................................................................... 42

9.3.1

Standard Interface................................................................................................................... 42

9.3.2

Multiplexed Interface............................................................................................................... 43

9.4

Implementing the Interrupt Mechanism ...................................................................................... 43

9.4.1

Hardware Configuration .......................................................................................................... 43

9.4.2

Software Configuration ........................................................................................................... 43

9.5

Platform-Specific Issues ............................................................................................................. 44

9.5.1

Wait State................................................................................................................................ 44

9.5.2

Big and Little Endian Systems ................................................................................................ 44

9.5.3

Busy Signal ............................................................................................................................. 44

9.5.4

Working with 8/16/32-Bit Systems with a Standard Interface................................................. 44

9.6

Device Cascading....................................................................................................................... 46

9.6.1

Standard Interface................................................................................................................... 46

9.6.2

Multiplexed Interface............................................................................................................... 46

9.6.3

Memory Map in a Cascaded Configuration ............................................................................ 47

10.

Product Specifications ..................................................................................................... 48

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

10.1

Environmental Specifications ..................................................................................................... 48

10.1.1

Operating Temperature Ranges ............................................................................................. 48

10.1.2

Thermal Characteristics .......................................................................................................... 48

10.1.3

Humidity .................................................................................................................................. 48

10.1.4

Endurance............................................................................................................................... 48

10.2

Disk Capacity.............................................................................................................................. 48

10.3

Electrical Specifications.............................................................................................................. 49

10.3.1

Absolute Maximum Ratings .................................................................................................... 49

10.3.2

Capacitance ............................................................................................................................ 49

10.3.3

DC Electrical Characteristics Over Operating Range ............................................................. 50

10.3.4

AC Operating Conditions ........................................................................................................ 52

10.4

Timing Specifications.................................................................................................................. 53

10.4.1

Read Cycle Timing Standard Interface................................................................................... 53

10.4.2

Write Cycle Timing Standard Interface ................................................................................... 56

10.4.3

Read Cycle Timing Multiplexed Interface ............................................................................... 58

10.4.4

Write Cycle Timing Multiplexed Interface ............................................................................... 60

10.4.5

Power-Up Timing .................................................................................................................... 62

10.4.6

Interrupt Timing ....................................................................................................................... 63

10.5

Mechanical Dimensions.............................................................................................................. 64

11.

Ordering Information......................................................................................................... 65

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

2. Product

Overview

2.1 Product

Description

Mobile DiskOnChip Plus 16/32MB is a member of M-Systems' DiskOnChip product series. It is a based on a single
die (16MB) or dual die (32MB) with an embedded flash controller and flash memory, providing a complete, easily
integrated flash disk for highly reliable data storage. Mobile DiskOnChip Plus also offers advanced features for
hardware-protected data and code and security-enabling features for both data and code storage. With superior read
and write performance, small size and low power consumption, it is optimized for the high-end handset, multimedia
handset and PDA markets. These markets require fast read and write rates, minimum weight and space, and low
power consumption to support the large and growing pool of data-rich applications.

Mobile DiskOnChip Plus protection and security features offer unique benefits. Two write- and read-protected
partitions, with both software- and hardware-based protection, can be configured independently for maximum
design flexibility. The 16-byte Unique ID (UID) identifies each flash device, used with security and authentication
applications, eliminating the need for a separate ID device (i.e. EEPROM) on the motherboard. The
user-configurable One Time Programmable (OTP) area, written to once and then locked to prevent data and code
from being altered, is ideal for storing customer and product-specific information. In addition, the Bad Block Table
is hardware protected, ensuring that it will not be damaged or accidentally changed to ensure maximum reliability.

Mobile DiskOnChip Plus devices have a simple SRAM-like interface, for easy integration. It can also be configured
to work with a multiplexed interface. Multiplexing data and address lines can save board space, reduce RF noise
effects and more.

Mobile DiskOnChip Plus is based on Toshiba's cutting-edge 0.16 µ NAND flash technology. This technology
enables Mobile DiskOnChip Plus to provide unmatched physical and performance-related benefits. It has the highest
flash density in the smallest die size available on the market, for the best cost structure and the smallest real estate.
Mobile DiskOnChip Plus devices use 8-bit internal flash access, featuring unrivaled write and read performance.

Mobile DiskOnChip Plus is a cost-effective solution for code storage as well as data storage. A Programmable Boot
Block with eXecute In Place (XIP) functionality can store boot code, replacing the boot ROM to function as the only
non-volatile memory on board. The Programmable Boot Block is 1KB for 16MB devices, and 2KB for 32MB
devices. This reduces hardware expenditures and board real estate. M-Systems' Download Engine (DE) is an
automatic bootstrap mechanism that expands the functionality of the Programmable Boot Block to enable CPU and
platform initialization directly from Mobile DiskOnChip Plus.

M-Systems' patented TrueFFS software technology fully emulates a hard disk to manage the files stored on Mobile
DiskOnChip Plus. This transparent file system management enables read/write operations that are identical to a
standard, sector-based hard disk. In addition, TrueFFS employs various patented methods, such as dynamic virtual
mapping, dynamic and static wear-leveling, and automatic bad-block management to ensure high data reliability and
to maximize flash lifetime. TrueFFS binary drivers are available for a wide range of popular OSs, including
Symbian OS, Pocket PC, Smartphone, Windows CE/.NET, OSE, Nucleus, and Linux. Customers developing for
target platforms not supported by TrueFFS binary drivers can use the TrueFFS Software Development Kit (SDK)
developer guide. For customized boot solutions, M-Systems provides the DiskOnChip Boot Software Development
Kit (BDK) developer guide.

Mobile DiskOnChip Plus is designed for compatibility and easy scalability. All capacities of Mobile DiskOnChip
Plus have the same ballout and are interchangeable. Greater capacities may easily be obtained by cascading up to
four 16MB devices or two 32MB devices with no additional glue logic. This upgrade path provides a flash disk of
up to 64MB (512Mb), while remaining totally transparent to the file system and user.

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

2.2.3 Signal Description

The ball designations are listed in the signal descriptions, presented in logic groups, in Table 1.

Table 1: Standard Interface Signal Descriptions

Signal Ball

No.

Input

Type

Description

Signal

Type

System Interface

A[12:11]
A[10:8]
A[7:4]
A[3:0]

D8, C8

F7, E7, C7

C3, D3, E3, F3
D2, E2, F2, G2

ST Address

bus.

Input

BHE# E4

ST,

Byte High Enable, active low. When low, data transaction on
D[15:8] is enabled. Not used and may be left floating when
IF_CFG is set to 0 (8-bit mode).

Input

CE#

ST, R Chip Enable, active low.

Input

D[7:0]

J8, G7, K7, H6,

H5, K4, G4, J3

Data bus, low byte.

Input/
Output

D[15:8]

H8, K8, H7, J7,

K5, J4, H4, K3

IN, R8 Data bus, high byte. Not used and may be left floating when

IF_CFG is set to 0 (8-bit mode).

Input/
Output

OE#

Output Enable, active low

Input

WE#

Write Enable, active low

Input

Configuration

ID[1:0]

G9, F8

Identification.
For Mobile DiskOnChip 16MB, up to four chips can be cascaded
in the same memory window, according to the following
assignment:
Chip 1 = ID1, ID0 = VSS, VSS (0,0); required for single chip
Chip 2 = ID1, ID0 = VSS, VCC (0,1)
Chip 3 = ID1, ID0 = VCC, VSS (1,0)
Chip 4 = ID1, ID0 = VCC, VCC (1,1)
For Mobile DiskOnChip 32MB, up to two chips can be cascaded in
the same memory window, according to the following assignment:
Chip 1 : ID1=VSS, ID0 = VSS ;required for single chip
Chip 2 : ID1=VSS, ID0 = VCC

Input

IF_CFG F4

Interface Configuration, 1 for 16-bit interface mode, 0 for 8-bit
interface mode.

Input

LOCK# E8

Lock, active low. When active, provides full hardware data
protection of selected partitions.

Input

Control

BUSY# E5

Busy, active low, open drain. Indicates that DiskOnChip is
initializing and should not be accessed. A 10 K

pull-up resistor is

required even if the ball is not used.

Output

IRQ# F9

Interrupt Request. Requires a 10 K

pull-up resistor.

Output

RSTIN#

Reset, active low.

Input

Power

VCCQ J6

I/O power supply. Sets the logic `1' voltage level range of I/O
balls/pins. VCCQ may be either 2.5V to 3.6V or 1.65V to 2.0V.
Requires a 10 nF and 0.1 µF capacitor.

Supply

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

Signal Ball

No.

Input

Type

Description

Signal

Type

VCC

Device supply. Requires a 10 nF and 0.1 µF capacitor.

Supply

VSS

G3, J9

Ground. All VSS balls must be connected.

Supply

Reserved

Reserved signal that is not connected internally.

Note: Future DiskOnChip devices will use this pin as a clock input. To be
forward compatible, this pin can already be connected to the system CLK
or to VCC when the clock input feature is not required.

RSRVD

Other. See

Figure 1

All reserved signals are not connected internally and must be left
floating to guarantee forward compatibility with future products.
They should not be connected to arbitrary signals

Mechanical

- M

Mechanical. These balls are for mechanical placement, and are
not connected internally.

- A

Alignment. This ball is for device alignment, and is not connected
internally.

The following abbreviations are used:
IN

Standard (non-Schmidt) input

Schmidt Trigger input

OD Open

drain

Nominal 22 K

pull-up resistor, enabled only for 8-bit interface mode (IF_CFG input is 0)

3.7 M

nominal pull-up resistor

Note: For forward compatibility with future DiskOnChip 7x10 FBGA products, additional pads are required. Please

refer to application note AP-DOC-067,

Preparing Your PCB Footprint for the DiskOnChip BGA Migration

Path, for detailed information.

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

2.3.3 Signal Description

The ball designations are listed in the signal descriptions, presented in logic groups, in Table 2.

Table 2: Multiplexed Interface Signal Descriptions

Signal Ball

No.

Input

Type

Description

Signal

Type

System Interface

AD[15:12]
AD[11:8]
AD[7:4]
AD[3:0]

H8, K8, H7, J7,
K5, J4, H4, K3,
J8, G7, K7, H6,

H5, K4, G4, J3

Multiplexed bus. Address and data signals.

Input/
Output

CE#

ST, R Chip Enable, active low.

Input

OE#

Output Enable, active low.

Input

WE#

Write Enable, active low.

Input

Configuration

AVD#

(For Mobile

DiskOnChip

16MB only)

Sets multiplexed interface. Multiplexed mode is automatically
entered when a rising edge is detected on this ball.

Input

ID0

(For Mobile

DiskOnChip

16MB only)

Identification. For Mobile DiskOnChip 16MB, up to two chips can
be cascaded in the same memory window, according to the
following assignment:
Chip 1: ID0 = VSS; required for single chip
Chip 2: ID0 = VCC

Input

LOCK# E8

Lock, active low. When active, provides full hardware data
protection of selected partitions.

Input

Control

BUSY# E5

Busy, active low, open drain. Indicates that DiskOnChip is
initializing and should not be accessed. A 10 K

pull-up resistor is

required even if the ball is not used.

Output

IRQ# F9

Interrupt Request. Requires a 10 K

pull-up resistor.

Output

RSTIN#

Reset, active low.

Input

Power

VCCQ F4,

I/O power supply. Sets the logic `1' voltage level range of I/O
balls/pins. VCCQ may be either 2.5V to 3.6V or 1.65V to 2.0V.
Requires a 10 nF and 0.1 µF capacitor.

Supply

VCC

J5 -

Device supply. All VCC balls must be connected; each VCC ball
requires a 10 nF and a 0.1 µF capacitor.

Supply

VSS

C3, C7, C8, D2,

D3, D8, E2, E3,

E4, E7, F2, F3,

F7, G2, G3, J9

Ground. All VSS balls must be connected.

Supply

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

Signal Ball

No.

Input

Type

Description

Signal

Type

Reserved

Reserved signal that is not connected internally.

RSRVD

Other. See

Figure 3

Reserved signal that is not connected internally and must be left
floating to guarantee forward compatibility with future products. It
should not be connected to arbitrary signals.

Mechanical

Mechanical. These balls are for mechanical placement, and are
not connected internally.

Alignment. This ball is for device alignment, and is not connected
internally.

The following abbreviations are used:
IN

Standard (non-Schmidt) input

Schmidt Trigger input

OD Open

drain

Nominal 22 K

pull-up resistor, enabled only for 8-bit interface mode (IF_CFG input is 0)

3.7 M

nominal pull-up resistor

Note: For forward compatibility with future DiskOnChip 7x10 FBGA products, additional pads are required. Please

refer to Application Note AP-DOC-067, Preparing your PCB Footprint for the DiskOnChip BGA Migration
Path, for detailed information.

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

3. Theory

Operation

3.1 Overview

Mobile DiskOnChip Plus consists of the following major functional blocks, as shown in Figure 5.

· System Interface for host interface
· Configuration Interface for configuring Mobile DiskOnChip Plus to operate in 8/16-bit mode, cascaded

configuration and hardware write protection.

· Protection and Security-Enabling containing write/read protection and One-Time Programming (OTP),

for advanced data/code security and protection.

· Programmable Boot Block with XIP capability enhanced with a Download Engine (DE) for system

initialization capability.

· Reed-Solomon-based Error Detection and Error Correction Code (EDC/ECC) for on-the-fly error

handling.

· Data Pipeline through which the data flows from the system to the NAND flash arrays.
· Control & Status block that contains registers responsible for transferring the address, data and control

information between the TrueFFS driver and the flash media

· Flash Interface consists of a single 16MB NAND flash array (Figure 5). Mobile DiskOnChip Plus

achieves a 32MB capacity using two stacked 16MB devices in a dual-die package.

· Bus Control for translating the host bus address, data and control signals into valid NAND flash signals.
· Address Decoder to enable the relevant unit inside the DiskOnChip controller, according to the address

range received from the system interface.

Figure 5: Standard Interface Simplified Block Diagram

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

3.2 System

Interface

The system interface block provides an easy-to-integrate SRAM-like (also EEPROM-like) interface to Mobile
DiskOnChip Plus, enabling it to interface with various CPU interfaces, such as a local bus, ISA bus, SRAM
interface, EEPROM interface or any other compatible interface. In addition, the EEPROM-like interface enables
direct access to the Programmable Boot Block to permit XIP functionality during system initialization.

A 13-bit wide address bus enables access to the DiskOnChip 8KB memory window (as shown in Section 6.2). The
16-bit data bus permits 16-bit wide access to the host. The internal access to the flash is 8-bit.

The Chip Enable (CE#), Write Enable (WE#) and Output Enable (OE#) signals trigger read and write cycles. A
write cycle occurs while both the CE# and the WE# inputs are asserted. Similarly, a read cycle occurs while both the
CE# and OE# inputs are asserted. Note that Mobile DiskOnChip Plus does not require a clock signal. Mobile
DiskOnChip Plus features a unique analog static design, optimized for minimal power consumption. The CE#, WE#
and OE# signals trigger the controller (e.g., system interface block, bus control and data pipeline) and flash access.

The Reset In (RSTIN#) and Busy (BUSY#) control signals are used in the reset phase. See Section 5.2 for further
details.

The Interrupt Request (IRQ#) signal can be used when long I/O operations, such as Block Erase, delay the CPU
resources. The signal is also asserted when a Data Protection violation has occurred. When this signal is
implemented, the CPU can run other tasks and only returns to continue read/write operations with Mobile
DiskOnChip Plus after the IRQ# signal has been asserted and an Interrupt Handling Routine (implemented in the
OS) has been called to return control to the TrueFFS driver.

3.3 Configuration

Interface

The Configuration Interface block enables the designer to configure Mobile DiskOnChip Plus to operate in different
modes. The identification signals (ID[1:0]) are used for identifying the relevant DiskOnChip device in a cascaded
configuration (see Section 9.6 on cascading for further details). The Lock (LOCK#) signal enables hard-wire
hardware-controlled protection of code and data, as described below. For a standard interface, the Interface
Configuration (IF_CFG) signal configures Mobile DiskOnChip Plus for 16-bit or 8-bit data access (see Section 9.5.4).

3.4 Protection and Security-Enabling Features

The protection and security-enabling block, consisting of read/write protection, UID and OTP area, enables
advanced data and code security and protection. Located on the main route of traffic between the host and the flash,
this block monitors and controls all data and code transactions to and from Mobile DiskOnChip Plus.

3.4.1 Read/Write Protection

Data and code protection is implemented through a Protection State Machine (PSM). The user can configure one or two
independently programmable areas of the flash memory as read protected, write protected, or read/write protected.

A protection area may be protected by either/both of these hardware mechanisms:

· 64-bit protection key
· Hard-wired LOCK# signal

The size and location of each area is user-defined to provide maximum flexibility for the target platform and
application requirements.

The configuration parameters of the protected areas are stored on the flash media and are automatically downloaded
from the flash to the PSM upon power-up, to enable robust protection throughout the flash lifetime.

In the event of an attempt to bypass the protection mechanism, illegally modify the protection key or in any way
sabotage the configuration parameters, the entire DiskOnChip becomes both read and write protected, and is
completely inaccessible.

For further information on the hardware protection mechanism, refer to Section 4.

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

3.4.2 Unique Identification (UID) Number

Each Mobile DiskOnChip Plus is assigned a 16-byte UID number. Burned onto the flash during production, the UID
cannot be altered and is unique worldwide. The UID is essential in security-related applications, and can be used to
identify end-user products in order to fight fraudulent duplication by imitators.

The UID on Mobile DiskOnChip Plus eliminates the need for an additional on-board ID device, such as a dedicated
EEPROM.

3.4.3 One-Time Programmable (OTP) Area

The 6KB OTP area is user-programmable for complete customization. The user can write to this area once, after
which it is automatically locked permanently. After it is locked, the OTP area becomes read only, just like a ROM
device.

Typically, the OTP area is used to store customer and product information such as: product ID, software version,
production data, customer ID and tracking information.

3.5 Programmable Boot Block with eXecute In Place (XIP) Functionality

During boot, code must be executed directly from the flash media, rather than first copied to the host RAM and then
executed from there. This direct XIP code execution functionality is essential for booting.

The Programmable Boot Block with XIP functionality enables Mobile DiskOnChip Plus to act as a boot ROM
device in addition to being a flash disk. This unique design enables the user to benefit from the advantages of NOR
flash, typically used for boot and code storage, and NAND flash, typically used for data storage. No other boot
device is required on the motherboard.

Mobile DiskOnChip Plus 16MB contains a 1KB Programmable Boot Block, whereas Mobile DiskOnChip Plus
32MB contains a 2KB Programmable Boot Block. The Download Engine (DE) described in the next section
expands the functionality of this block by copying the boot code from the flash into the boot block.

When the maximum number of Mobile DiskOnChip Plus devices are cascaded, the Programmable Boot Block
provides 4KB of boot block area. The Programmable Boot Block of each device is mapped to a unique address
space.

3.6 Download

Engine

(DE)

Upon power up or when the RSTIN# signal is asserted high, the DE automatically downloads the Initial Program
Loader (IPL) from the flash to the Programmable Boot Block. The IPL is responsible for starting the boot process.
The download process is quick (1.3 ms max) and is designed so that when the CPU accesses Mobile DiskOnChip
Plus for code execution, the IPL code is already located in the Programmable Boot Block.

In addition, the DE downloads the Data Protection Structures (DPS) from the flash to the Protection State Machines
(PSMs), so that Mobile DiskOnChip Plus is secure and protected from the first moment it is active.

During the download process, Mobile DiskOnChip Plus asserts the BUSY# signal to indicate to the system that it is
not yet ready to be accessed. After BUSY# is negated, the system can access Mobile DiskOnChip Plus.

A failsafe mechanism prevents improper initialization due to a faulty VCC or invalid assertion of the RSTIN# input.
Another failsafe mechanism is designed to overcome possible NAND flash data errors. It prevents internal registers
from powering up in a state that bypasses the intended data protection. In addition, in any attempt to sabotage the
data structures causes the entire Mobile DiskOnChip Plus to become both read- and write-protected and completely
inaccessible.

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3.7 Error Detection Code/Error Correction Code (EDC/ECC)

NAND flash, being an imperfect memory, requires error handling. Mobile DiskOnChip Plus implements
Reed-Solomon Error Detection Code (EDC). A hardware-generated, 6-byte error detection signature is computed
each time a page (512 bytes) is written to or read from Mobile DiskOnChip Plus.

The TrueFFS driver implements complementary Error Correction Code (ECC). Unlike error detection, which is
required on every cycle, error correction is relatively seldom required, hence implemented in software. The
combination of Mobile DiskOnChip Plus's built-in EDC mechanism and the TrueFFS driver ensures highly reliable
error detection and correction, while providing maximum performance.

The following detection and correction capability is provided for each 512 bytes:

· Corrects up to two 10-bit symbols, including two random bit errors.
· Corrects single bursts up to 11 bits.
· Detects single bursts up to 31 bits and double bursts up to 11 bits.
· Detects up to 4 random bit errors.

3.8 Data

Pipeline

Mobile DiskOnChip Plus uses a two-stage pipeline mechanism, designed for maximum performance while enabling
on-the-fly data manipulation, such as read/write protection and Error Detection/Error Correction.

3.9 Control & Status

The Control & Status block contains registers responsible for transferring the address, data and control information
between the DiskOnChip TrueFFS driver and the flash media. Additional registers are used to monitor the status of
the flash media (ready/busy) and of the DiskOnChip controller. For further information on the Mobile DiskOnChip
Plus registers, refer to Section 6.3).

3.10 Flash Architecture

A 16MB flash bank consists of 1024 blocks organized in 32 pages, as follows:

· Page Each page contains 512 bytes of user data and a 16-byte extra area that is used to store flash

management and EDC/ECC signature data, as shown in Figure 6. A page is the minimal unit for read/write
operations.

· Block Each block contains 32 pages (total of 16KB), as shown in Figure 7. A block is the minimal unit

that can be erased, and is sometimes referred to as an erase block.

16 Bytes

512 Bytes

User Data

Flash Management &

ECC/EDC Signature

0.5 KB

Figure 6: Page Structure

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4. Hardware

Protection

4.1 Method

Operation

Mobile DiskOnChip Plus enables the user to define two partitions that are protected (in hardware) against any
combination of read or write operations. The two protected areas can be configured as read protected or write-
protected, and are protected by a protection key (i.e. password) defined by the user. Each of the protected areas can
be configured separately and can function separately, providing maximal flexibility for the user.

The size and protection attributes (protection key/read/write/changeable/lock) of the protected partition are defined
in the media formatting stage (DFORMAT utility or the format function in the TrueFFS SDK).

In order to set or remove a read/write protection, the protection key (i.e., password) must be used, as follows:

· Insert the protection key to remove read/write protection.
· Remove the protection key to set read/write protection.

Mobile DiskOnChip Plus has an additional hardware safety measurement. If the Lock option is enabled (by means
of software) and the LOCK# ball is asserted, the protected partition has an additional hardware lock that prevents
read/write access to the partition, even with the use of the correct protection key. The LOCK# ball must be asserted
during DFORMAT (and later when the partition is defined as changeable) to enable the additional hard-wired safety
lock.

It is possible to set the Lock option for one session only, that is, until the next power-up or reset. This Sticky Lock
feature can be useful when the boot code in the boot partition must be read/write protected. Upon power-up, the boot
code must be unprotected so the CPU can run it directly from Mobile DiskOnChip Plus. At the end of the boot
process, protection can be set until the next power-up or reset.

Setting the Sticky Lock (SLOCK) bit in the Output Control register to 1 has the same effect as asserting the LOCK#
ball. Once set, SLOCK can only be cleared by asserting the RSTIN# input. Like the LOCK# input, the assertion of
this bit prevents the protection key from disabling the protection for a given partition. For more information, see
Section 7.9. The target partition does not have to be mounted before calling a hardware protection routine.

Only one partition can be defined as "changeable"; i.e., its password and attributes are fully configurable at any time
(from read to write, both or none and visa versa). Note that "un-changeable" partition attributes cannot be changed
unless the media is reformatted.

A change of any of the protection attributes causes a reset of the protection mechanism and consequently the
removal of all device protection keys. That is, if the protection attributes of one partition are changed, the other
partition will lose its key-protected read/write protection.

The only way to read or write from a read or write protected partition is to use the insert key call (even DFORMAT
does not remove the protection). This is also true for modifying its attributes (key, read, write and lock enable state).
Read/write protection is disabled in each one of the following events:

· Power-down
· Change of any protection attribute (not necessarily in the same partition)
· Write operation to the IPL area
· Removal of the protection key.

For further information on hardware protection, please refer to the TrueFFS Software Development Kit (SDK)
developer guide or application note AP-DOC-057, Protection and Security-Enabling Features in DiskOnChip Plus.

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4.2 Low-Level Structure of the Protected Area

The first three blocks on Mobile DiskOnChip Plus contain foundry information, the Data Protect structures, IPL
code, and bad-block mapping information. See Figure 8.

Bad Block Table and Factory-Programmed UID

Data Protect Structure 0

Pages 0-5

Pages 7-12

OTP

Data Protect Structure 1 and IPL Code

Block 0

Block 1

Block 2

Figure 8: Low Level Structure of Mobile DiskOnChip Plus

Blocks 0, 1 and 2 in Mobile DiskOnChip Plus contain the following information:

Block 0

· Bad Block Table (page 2). Contains the mapping information to unusable Erase units on the flash media.
· UID (16 bytes). This number is written during the manufacturing stage, and cannot be altered at a later

time.

· Customer OTP (occupies pages 26-31). The OTP area is written once and then locked.
Block 1

· Data Protect Structure 0. This structure contains configuration information on one of the two user-defined

protected partitions.

Block 2

· Data Protect Structure 1. This structure contains configuration information on one of the two user-defined

protected partitions.

· IPL Code (1KB). This is the boot code that is downloaded by the DE to the internal boot block.

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5. Modes

Operation

Mobile DiskOnChip Plus has three modes of operation:

· Reset
· Normal
· Deep Power-Down

Mode changes can occur due to any of the following events, as shown in Figure 9:

· Assertion of the RSTIN# signal sets the device in Reset mode.
· During power-up, boot detector circuitry sets the device in Reset mode.
· A valid write sequence to Mobile DiskOnChip Plus sets the device in Normal mode. This is done

automatically by the TrueFFS driver on power-up (reset sequence end).

· Switching back from Normal mode to Reset mode can be done by a valid write sequence to Mobile

DiskOnChip Plus, or by triggering the boot detector circuitry (by soft reset).

· Power-down.
· A valid write sequence, initiated by software, sets the device from Normal mode to Deep Power-Down

mode. Four read cycles from offset 0x1FFF set the device back to Normal mode. Alternately, the device
can be set back to Normal mode with an extended access time during a read from the Programmable Boot
Block (see Section 10.4.1 for read cycle timing).

· Asserting the RSTIN# signal and holding it in this state while in Normal mode puts the device in Deep

Power-Down mode. When the RSTIN# signal is released, the device is set in Reset mode.

Power Off

Reset Mode

Deep

Power-Down

Mode

Normal Mode

Power-Up

Power-Down

Assert RSTIN#,

Boot Detect or

Software Control

Power-Down

Reset

Sequence

End

Software Control

4x Read Cycles from

offset 0x1FFF or

extended read cycle

Power-Down

Release RSTIN#

Assert RSTIN#

Assert RSTIN#

Figure 9: Operation Modes and Related Events

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5.1 Normal

Mode

This is the mode in which standard operations involving the flash memory are performed. Normal mode is
automatically entered when a valid write sequence is sent to the DiskOnChip Control register and Control
Confirmation register. The boot detector circuit triggers the software to set the device to Normal mode.

A write cycle occurs when both the CE# and WE# inputs are asserted. Similarly, a read cycle occurs when both the
CE# and OE# inputs are asserted. Because the flash controller generates its internal clock from these CPU cycles
and some read operations return volatile data, it is essential that the specified timing requirements contained in
Section 10.4.1 be met. It is also essential that read and write cycles are not interrupted by glitches or ringing on the
CE#, WE#, OE# address inputs. All inputs to Mobile DiskOnChip Plus are Schmidt Trigger types to improve noise
immunity.

In Normal mode, Mobile DiskOnChip Plus responds to every valid hardware cycle. When there is no activity, it is
possible to reduce the power consumption to a typical deep-power-down current of 10 µA (16MB) or 20 µA
(32MB) by setting the device in Deep Power-Down mode.

5.2 Reset Mode

In Reset mode, Mobile DiskOnChip Plus ignores all write cycles, except for those to the DiskOnChip Control
register and Control Confirmation register. All register read cycles return a value of 00H. Before attempting to
perform a register read operation, the device is set to Normal mode by the TrueFFS software.

5.3 Deep Power-Down Mode

In Deep Power-Down mode, Mobile DiskOnChip Plus internal high current voltage regulators are disabled to reduce
quiescent power consumption to 10

µA (16MB) or 20 µA (32MB) (Typ.). The following signals are also disabled in

this mode:

· Standard interface: input buffers A[12:0], BHE#, WE#, D[15:0] and OE# (when CE# is negated)
· Multiplexed interface: input buffers AD[15:0], AVD#,WE# and OE# (when CE# is negated).

To enter Deep Power-Down mode, a proper sequence must be written to the DiskOnChip Control registers and
DiskOnChip Control Confirmation register, and the CE# input must be negated (CE# = VCC). All other inputs
should be VSS or VCC.

An additional option for setting the device into Deep Power-Down mode, when in Normal mode, is by asserting the
RSTIN# signal and holding it in the low state (see the dotted line in Figure 9). When the RSTIN# signal is released,
the device is set in Reset mode.

In Deep Power-Down mode, write cycles have no effect and read cycles return indeterminate data (Mobile
DiskOnChip Plus does not drive the data bus). Entering Deep Power-Down mode and then returning to the previous
mode does not affect the value of any register.

To exit Deep Power-Down mode, perform the following sequence:

· Read four times from address 1FFFH. The data returned is undefined. (This option is valid for both

standard and multiplexed interfaces).

· Perform a single read cycle from the Programmable Boot Block with an extended access time and address

hold time as specified in Section 10.4.1. The data returned will be correct.

Applications that require both Deep Power-Down mode and boot detection require BIOS support to ensure that
Mobile DiskOnChip Plus exits from Power-Down mode prior to the expansion ROM scan. Similarly, applications
that use Mobile DiskOnChip Plus as a boot ROM must ensure that the device is not in Deep Power-Down mode
before reading the boot vector/instructions, either by pulsing RSTIN# to the asserted state and waiting for the
BUSY# output to be negated, or by entering Reset mode via software.

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6. TrueFFS

Technology

6.1 General

Description

M-Systems' patented TrueFFS technology was designed to maximize the benefits of flash memory while
overcoming inherent flash limitations that would otherwise reduce its performance, reliability and lifetime. TrueFFS
emulates a hard disk, making it completely transparent to the OS. In addition, since it operates under the OS file
system layer (see Figure 10), it is completely transparent to the application.

Figure 10: TrueFFS Location in System Hierarchy

TrueFFS technology support includes:

· Binary driver support for all major OSs
· TrueFFS Software Development Kit (SDK) developer guide
· DiskOnChip Boot Software Development Kit (BDK) developer guide
· Support for all major CPUs, including 8-, 16- and 32-bit bus architectures

TrueFFS technology features:

· Block device API
· Flash file system management
· Bad-block management
· Dynamic virtual mapping
· Dynamic and static wear-leveling
· Power failure management
· Implementation of Reed-Solomon EDC/ECC
· Performance optimization
· Compatibility with all DiskOnChip products

6.1.1 Built-In Operating System Support

The TrueFFS driver is integrated into all major OSs, including Symbian OS, Windows CE, Pocket PC, Smartphone,
OSE, Nucleus, and others. For a complete listing of all available drivers, please refer to M-Systems' website
http://www.m-sys.com. It is advised to use the latest driver versions that can be downloaded from the Mobile
DiskOnChip Plus web page on the M-Systems site.

Application

OS File System

TrueFFS

DiskOnChip

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6.1.2 TrueFFS Software Development Kit (SDK)

The basic TrueFFS Software Development Kit (SDK) provides the source code of the TrueFFS driver. It can be used
in an OS-less environment or when special customization of the driver is required for proprietary OSs.

When using Mobile DiskOnChip Plus as the boot replacement device, the TrueFFS SDK also incorporates in its
source code the BDK, software that is required for this configuration (this package is also available separately).
Please refer to the DiskOnChip Boot Software Development Kit (BDK) developer guide for further information on
using this software package.

6.1.3 File Management

TrueFFS accesses the flash memory within Mobile DiskOnChip Plus through an 8KB window in the CPU memory
space. It provides block device API, by using standard file system calls, identical to those used by a mechanical hard
disk, to enable reading from and writing to any sector on Mobile DiskOnChip Plus. This makes it compatible with
any file system and file system utilities such as diagnostic tools and applications. When using the File Allocation
Table (FAT) file system, the data stored on Mobile DiskOnChip Plus uses FAT-16.

Note:

Mobile DiskOnChip Plus is shipped unformatted and contains virgin media.

6.1.4 Bad-Block Management

As NAND flash is an imperfect storage media, it contains some bad blocks that cannot be used for storage because
of their high error rates. TrueFFS automatically detects and maps bad blocks upon system initialization, ensuring
that they are not used for storage. This management process is completely transparent to the user, who remains
unaware of the existence and location of bad blocks, while remaining confident of the integrity of data stored. The
Bad Block Table on Mobile DiskOnChip Plus is hardware-protected for ensured reliability.

6.1.5 Wear-Leveling

Flash memory can be erased a limited number of times. This number is called the erase cycle limit or write
endurance limit and is defined by the flash array vendor. The erase cycle limit applies to each individual erase block
in the flash device. In Mobile DiskOnChip Plus, the erase cycle limit of the flash is 300,000 erase cycles. This
means that after approximately 300,000 erase cycles, the erase block begins to make storage errors at a rate
significantly higher than the error rate that is typical to the flash.

In a typical application and especially if a file system is used, a specific page or pages are constantly updated (e.g.,
the page/s that contain the FAT, registry etc.). Without any special handling, these pages would wear out more
rapidly than other pages, reducing the lifetime of the entire flash.

To overcome this inherent deficiency, TrueFFS uses M-Systems' patented wear-leveling algorithm. The
wear-leveling algorithm ensures that consecutive writes of a specific sector are not written physically to the same
page in the flash. This spreads flash media usage evenly across all pages, thereby maximizing flash lifetime.
TrueFFS wear-leveling extends the flash lifetime 10 to 15 years beyond the lifetime of a typical application.

Dynamic Wear-Leveling

TrueFFS uses statistical allocation to perform dynamic wear-leveling on newly written data. This not only
minimizes the number of erase cycles per block, it also minimizes the total number of erase cycles. Because a block
erase is the most time-consuming operation, dynamic wear-leveling has a major impact on overall performance. This
impact cannot be noticed during the first write to flash (since there is no need to erase blocks beforehand), but it is
more and more noticeable as the flash media becomes full.

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Static Wear-Leveling

Areas on the flash media may contain static files, characterized by blocks of data that remain unchanged for very
long periods of time, or even for the whole device lifetime. If wear-leveling were only applied on newly written
pages, static areas would never be cycled. This limited application of wear-leveling would lower life expectancy
significantly in cases where flash memory contains large static areas. To overcome this problem, TrueFFS forces
data transfer in static areas as well as in dynamic areas, thereby applying wear-leveling to the entire media.

6.1.6 Power Failure Management

TrueFFS uses algorithms based on "erase after write" instead of "erase before write" to ensure data integrity during
normal operation and in the event of a power failure. Used areas are reclaimed for erasing and writing the flash
management information into them only after an operation is complete. This procedure serves as a check on data
integrity.

The "erase after write" algorithm is also used to update and store mapping information on the flash memory. This
keeps the mapping information coherent even during power failures. The only mapping information held in RAM is
a table pointing to the location of the actual mapping information. This table is reconstructed during power-up or
after reset from the information stored in the flash memory.

To prevent data from being lost or corrupted, TrueFFS uses the following mechanisms:

· When writing, copying, or erasing the flash device, the data format remains valid at all intermediate stages.

Previous data is never erased until the operation has been completed and the new data has been verified.

· A data sector cannot exist in a partially written state. Either the operation is successfully completed, in

which case the new sector contents are valid, or the operation has not yet been completed or has failed, in
which case the old sector contents remain valid.

6.1.7 Error Detection/Correction

TrueFFS implements a Reed-Solomon Error Correction Code (ECC) algorithm to ensure data reliability. Refer to
Section 3.7 for further information on the EDC/ECC mechanism.

6.1.8 Special Features through I/O Control (IOCTL) Mechanism

In addition to standard storage device functionality, the TrueFFS driver provides extended functionality. This
functionality goes beyond simple data storage capabilities to include features such as: format the media, read/write
protect, binary partition(s) access, flash defragmentation and other options. This unique functionality is available in
all TrueFFS-based drivers through the standard I/O control command of the native file system.

For further information, please refer to the Extended Functions of the TrueFFS Driver for DiskOnChip developer
guide.

6.1.9 Compatibility

The TrueFFS driver supports all released DiskOnChip products. Upgrading from one product to another requires no
additional software integration.

When using different drivers (e.g. TrueFFS SDK, BDK, BIOS extension firmware, etc.) to access Mobile
DiskOnChip Plus, the user must verify that all software is based on the same code base version. It is also important
to use only tools (e.g. DFORMAT, DINFO, GETIMAGE, etc.) derived from the same version as the firmware
version and the TrueFFS drivers used in the application. Failure to do so may lead to unexpected results, such as lost
or corrupted data. The driver and firmware version can be verified by the sign-on messages displayed, or by the
version information stored in the driver or tool.

Note: When a new M-Systems DiskOnChip product with new features is released, a new TrueFFS version is

required.

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6.3 8KB Memory Window for Mobile DiskOnChip Plus 32MB

TrueFFS utilizes an 8KB memory window in the CPU address space consisting of four 2KB sections, as depicted in
Figure 11. When in Reset mode, the Programmable Boot Block in sections 0 and 3 will show the IPL (1KB) of the
first 16MB of the dual die, aliased twice. Read cycles from sections 1 and 2 always return the value 00H to create a
fixed and known checksum.

After setting the MAX_ID field in the Configuration register (done by IPL0), the second copy of IPL0 is replaced
with the IPL of the second 16MB device of the dual die, thereby creating a 2KB Programmable Boot Block.

When in Normal mode, sections 1 and 2 are used for the internal registers. The Programmable Boot Block in
section 0 contains IPL0 and IPL1. Section 3 contains IPL0 aliased twice.

The addresses described here are relative to the absolute starting address of the 8KB memory window.

Programmable

boot block

[IPL]

(2 aliases)

Reset Mode

Flash area

window

(+ aliases)

000H

800H

1000H

1800H

Control

Registers

(+ aliases)

Section 0

Section 1

Section 2

Section 3

Normal Mode

00H

Programmable

boot block

[000H-3FFH]

(2 aliases)

Programmable

boot block

[IPL0, IPL1]

(2 aliases)

00H

Programmable

boot block

[IPL0, IPL1]

Figure 12: Mobile DiskOnChip Plus 32MB Memory Map

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7. Register

Descriptions

This section describes various Mobile DiskOnChip Plus registers and their functions, as listed in Table 3. This
section can be used to enable the designer to better evaluate DiskOnChip technology.

Table 3: Mobile DiskOnChip Plus Registers

Address (Hex)

Register Name

1000 Chip Identification (ID)
1002 No

Operation (NOP)

1004 Test
1006 DiskOnChip Control
1008

Device ID Select

100A Configuration
100C Output Control
100E Interrupt Control

1046 Toggle Bit
1076 DiskOnChip Control Confirmation

7.1 Definition of Terms

The following abbreviations and terms are used within this section:

RFU

Reserved for future use. This bit is undefined during a read cycle and "don't care" during a write
cycle.

RFU_0

Reserved for future use; when read, this bit always returns the value 0; when written, software should
ensure that this bit is always set to 0.

RFU_1

Reserved for future use; when read, this bit always returns the value 1; when written, software should
ensure that this bit is always set to 1.

Reset Value Refers to the value immediately present after exiting from Reset mode to Normal mode.

7.2 Reset

Values

All registers return 00H while in Reset mode. The Reset value written in the register description is the register value
after exiting Reset mode and entering Normal mode. Some register contents are undefined at that time (N/A).

7.3 Chip Identification (ID) Register

Description:

This register is used to identify the device residing on the host platform. It always returns 41H
when read.

Address (hex):

1000

Type: Read

only

Reset Value:

41H

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

41H

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7.6 DiskOnChip Control Register/Control Confirmation Register

Description:

These two registers are identical and contain information on the operation mode of Mobile
DiskOnChip Plus. After writing the required value to the DiskOnChip Control register, the
complement of that data byte must also be written to the Control Confirmation register. The two
writes cycles must not be separated by any other read or write cycles to the Mobile DiskOnChip
Plus memory space, except for reads from the Programmable Boot Block space.

Address (hex):

1006/1076

Type: Read/Write

Reset Value:

10H

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RFU_0 RST_LAT

BDET

MDWREN

Mode[1:0]

Bit No.

Description

0-1

Mode. These bits select the mode of operation, as follows:
00: Reset
01: Normal
10: Deep Power-Down

MDWREN (Mode Write Enable). This bit must be set to 1 before changing the mode of operation.

BDET (Boot Detect). This bit is set whenever the device has entered Reset mode as a result of the
Boot Detector triggering. It is cleared by writing a 1 to this bit.

RST_LAT (Reset Latch). This bit is set whenever the device has entered the Reset mode as a
result of the RSTIN# input signal being asserted or the internal voltage detector triggering. It is
cleared by writing a 1 to this bit.

5-7

Reserved for future use

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7.7 Device ID Select Register

Description:

In a cascaded configuration, this register controls which device provides the register space. The
value of bits ID[0:1] is compared to the value of the ID configuration input balls, as defined in
Section 9.6. The device whose ID input balls matches the value of bits ID[0:1] responds to read
and write cycles to register space.

Address (hex):

1008

Type: Read/Write

Reset Value:

00H

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RFU_0

ID[1:0]

Bit No.

Description

0-1

ID[1:0] (Identification). The device whose ID input balls matches the value of bits ID[0:1] responds
to read and write cycles to register space.

2-7

Reserved for future use

7.8 Configuration

Register

Description:

This register indicates the current configuration of the device. Unless otherwise noted, the bits are
reset only by a hardware reset, and not upon boot detection or any other entry to Reset mode.

Address (hex):

100A

Type:

Read/Write (except bit 7, which is Read Only)

Reset Value:

X0000X10

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

IF_CFG

RFU_0

MAX_ID

RFU

RFU_0

Bit No.

Description

0-3, 6

Reserved for future use

4-5

MAX_ID (Maximum Device ID). This field controls the RAM address mapping when multiple
devices are used in a cascaded configuration, using the ID[1:0] inputs. It should be programmed to
the highest ID value that is found by software in order to map all available boot blocks into usable
address space.

IF_CFG (Interface Configuration). Reflects the state of the IF_CFG input pin.

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Data Sheet, Rev. 1.7

95-SR-000-10-8L

7.9 Output Control Register

Description:

This register controls the behavior of certain output balls.

Address (hex):

100C

Type: Read/Write

Reset Value:

01H

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RFU_0

SLOCK RFU_1 RFU_0 RFU_1

Bit No.

Description

0-2, 4-7

Reserved for future use.

SLOCK [Sticky Lock]. Setting this bit to a 1 has the same effect as asserting the LOCK# input, up
until the next power-up or reset. Once set, this bit can only be cleared by asserting the RSTIN#
input. Like the LOCK# input, the assertion of this bit prevents the protection key from disabling the
protection for a given partition if the value of the LOCK bit in its respective Data Protect Structure is
set. When read, this bit always returns the value 0. Setting this bit affects the state of the LOCK# bit
in the Protection Status register.

Note: For further information on the Output Control and Protection Status registers, refer to the addendum to this

data sheet, Mobile DiskOnChip Plus/DIMM Plus Register Description.

7.10 Interrupt Control

Description:

Interrupts may be generated when the flash transitions from the busy state to the ready state, or by
a data protection violation.

Address (hex):

100E

Type: Read/Write

Reset Value:

00H

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RFU_0

IRQ_P

IRQ_F

EDGE

PROT_T

FRDY_T[2:0

Bit No.

Description

0-2

FRDY_T[2:0] (Flash Ready Trigger). This field determines if an interrupt will be generated when the
flash array of Mobile DiskOnChip Plus is ready, as follows:
000: Interrupts are disabled Holds the IRQ# output in the negated state.
001: Interrupt when flash array is ready.

PROT_T (Protection Trigger). When set, an interrupt is generated upon a data protection violation.

EDGE (Edge-sensitive interrupt)
0: Specifies level-sensitive interrupts in which the IRQ# output remains asserted until the interrupt
is cleared.
1: Specifies edge-sensitive interrupts in which the IRQ# output pulses low.

IRQ_F: (Interrupt Request when flash array is ready) Indicates that the IRQ# output has been
asserted due to an indication that the flash array is ready. Writing 1 to this bit clears its value,

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

Booting from Mobile DiskOnChip Plus

8.1 Introduction

Mobile DiskOnChip Plus can function both as a flash disk and the system boot device. If DiskOnChip is configured
as a flash disk, it can operate as the OS boot device. DiskOnChip default firmware contains drivers to enable it to
perform as the OS boot device under DOS (see Section 8.2). For other OSs, please refer to the readme file of the
TrueFFS driver.

If Mobile DiskOnChip Plus is configured as a flash disk and as the system boot device, it contains the boot loader,
an OS image and a file system. In such a configuration, Mobile DiskOnChip Plus can serve as the only non-volatile
device on board. Refer to Section 8.3.2 for further information on boot replacement.

8.2 Boot Procedure in PC-Compatible Platforms

When used in PC-compatible platforms, Mobile DiskOnChip Plus is connected to an 8KB memory window in the
BIOS expansion memory range, typically located between 0C8000H to 0EFFFFH. During the boot process, the
BIOS loads the TrueFFS firmware into the PC memory and installs Mobile DiskOnChip Plus as a disk drive in the
system. When the operating system is loaded, Mobile DiskOnChip Plus is recognized as a standard disk. No external
software is required to boot from Mobile DiskOnChip Plus.

Figure 13 illustrates the location of the Mobile DiskOnChip Plus memory window in the PC memory map.

640k

Display

RAM

0C8000H

BIOS

0B0000H

0F0000H

0FFFFFH

DiskOnChip

Extended Memory

Figure 13: Mobile DiskOnChip Plus Memory Window in PC Memory Map

After reset, the BIOS code first executes the Power On Self-Test (POST) and then searches for all expansion ROM
devices. When Mobile DiskOnChip Plus is located, the BIOS code executes from it the IPL code, located in the XIP
portion of the Programmable Boot Block. This code loads the TrueFFS driver into system memory, installs Mobile
DiskOnChip Plus as a disk in the system, and then returns control to the BIOS code. The operating system
subsequently identifies Mobile DiskOnChip Plus as an available disk. TrueFFS responds by emulating a hard disk.

From this point onward, Mobile DiskOnChip Plus appears as a standard disk drive. It is assigned a drive letter and
can be used by any application, without any modifications to either the BIOS set-up or the autoexec.bat/
config.sys files. Mobile DiskOnChip Plus can be used as the only disk in the system, with or without a floppy drive,
and with or without hard disks.

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

The drive letter assigned depends on how Mobile DiskOnChip Plus is used in the system, as follows:

· If Mobile DiskOnChip Plus is used as the only disk in the system, the system boots directly from it and

assigns it drive C.

· If Mobile DiskOnChip Plus is used with other disks in the system:

o Mobile DiskOnChip Plus can be configured as the last drive (the default configuration). The system

assigns drive C to the hard disk and drive D to Mobile DiskOnChip Plus.

o Alternatively, Mobile DiskOnChip Plus can be configured as the system's first drive. The system

assigns drive D to the hard disk and drive C to Mobile DiskOnChip Plus.

· If Mobile DiskOnChip Plus is used as the OS boot device when configured as drive C, it must be formatted

as a bootable device by copying the OS files onto it. This is done by using the SYS command when
running DOS.

8.3 Boot

Replacement

8.3.1 PC Architectures

In current PC architectures, the first CPU fetch (after reset is negated) is mapped to the boot device area, also known
as the reset vector. The reset vector in PC architectures is located at address FFFF0, by using a Jump command to
the beginning of the BIOS chip (usually F0000 or E0000). The CPU executes the BIOS code, initializes the
hardware and loads Mobile DiskOnChip Plus software using the BIOS expansion search routine (e.g. D0000). Refer
to Section 8.2 for a detailed explanation on the boot sequence in PC-compatible platforms.

Mobile DiskOnChip Plus implements both disk and boot functions when it replaces the BIOS chip. To enable this,
Mobile DiskOnChip Plus requires a location at two different addresses:

· After power-up, Mobile DiskOnChip Plus must be mapped in F segment, so that the CPU fetches the reset

vector from address FFFF0, where Mobile DiskOnChip Plus is located.

· After the BIOS code is loaded into RAM and starts execution, Mobile DiskOnChip Plus must be

reconfigured to be located in the BIOS expansion search area (e.g. D0000) so it can load the TrueFFS
software.

This means that the CS# signal must be remapped between two different addresses. For further information on how
to achieve this, refer to application note AP-DOC-047, Designing DiskOnChip as a Flash Disk and Boot Device
Replacement.

8.3.2 Non-PC Architectures

In non-PC architectures, the boot code is executed from a boot ROM, and the drivers are usually loaded from the
storage device.

When using Mobile DiskOnChip Plus as the system boot device, the CPU fetches the first instructions from the
Mobile DiskOnChip Plus Programmable Boot Block, which contains the IPL. Since in most cases this block cannot
hold the entire boot loader, the IPL runs minimum initialization, after which the Secondary Program Loader (SPL) is
copied to RAM from flash. The remainder of the boot loader code then runs from RAM.

The IPL and SPL are located in a separate (binary) partition on Mobile DiskOnChip Plus, and can be hardware
protected if required.

For further information on software boot code implementation, refer to application note AP-DOC-044, Writing an
IPL for DiskOnChip Plus 16MByte Devices.

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Data Sheet, Rev. 1.7

95-SR-000-10-8L

8.3.3 Using Mobile DiskOnChip Plus in Asynchronous Boot Mode

Platforms that host CPUs that wake up in burst mode should use Asynchronous Boot mode when using Mobile
DiskOnChip Plus as the system boot device.

During platform initialization, certain CPUs wake up in 32-bit mode and issue instruction fetch cycles continuously.
An XScale CPU, for example, initiates a 16-bit read cycle, but after the first word is read, it continues to hold CE#
and OE# asserted while it increments the address and reads additional data as a burst. A StrongARM CPU wakes up
in 32-bit mode and issues double-word instruction fetch cycles.

Since Mobile DiskOnChip Plus derives its internal clock signal from the CE#, OE# and WE# inputs, it cannot
distinguish between these burst cycles. To support this type of access, Mobile DiskOnChip Plus needs to be set in
Asynchronous Boot mode.

To set Mobile DiskOnChip Plus in Asynchronous Boot mode, set the byte RAM MODE SELECT to 8FH. This can
be done through the Mobile DiskOnChip Plus format utility or by customizing the IPL code. For more information
on the format utility, refer to the DiskOnChip Software Utilities user manual or the TrueFFS Software Development
Kit (SDK) developer guide. For further details on customizing the IPL code, refer to application note AP-DOC-044,
Writing an IPL for DiskOnChip Plus 16MByte.

Once in Asynchronous Boot mode, the CPU can fetch its instruction cycles from the Mobile DiskOnChip Plus
Programmable Boot Block. After reading from this block and completing boot, Mobile DiskOnChip Plus returns to
derive its internal clock signal from the CE#, OE# and WE# inputs. Please refer to Section 10.4 for read timing
specifications for Asynchronous Boot mode.

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

9.2 System

Interface

9.2.1 Standard Interface

Mobile DiskOnChip Plus uses an SRAM-like interface that can easily be connected to any microprocessor bus. With
a standard interface, it requires 13 address lines, 8 data lines and basic memory control signals (CE#, OE#, WE#), as
shown in Figure 14 below. Typically, Mobile DiskOnChip Plus can be mapped to any free 8KB memory space. In a
PC compatible platform, it is usually mapped into the BIOS expansion area. If the allocated memory window is
larger than 8KB, an automatic anti-aliasing mechanism prevents the firmware from being loaded more than once
during the ROM expansion search.

Mobile DiskOnChip

Plus

Address

Data

Output Enable

Write Enable

Chip Enable

Reset

Chip ID

VSS

3.3 V

BUSY#

Busy

VCC

D[15:0]

OE#

WE#

CE#

RSTIN#

ID[1:0]

A[12:0]

LOCK#

BHE#

IF_CFG

10 nF

0.1 uF

10 nF

0.1 uF

1.8V/3.3V

VCCQ

1-20KOhm

IRQ

Figure 14: Standard System Interface

Notes: 1. The 0.1 µF and the 10 nF low-inductance high-frequency capacitors must be attached to each of the

device's VCC and VSS balls. These capacitors must be placed as close as possible to the package
leads.

Mobile DiskOnChip Plus is an edge-sensitive device. CE#, OE# and WE# should be properly
terminated (according to board layout, serial parallel or both terminations) to avoid signal ringing.

All capacities support the standard interface.

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

9.2.2 Multiplexed Interface

With a multiplexed interface, Mobile DiskOnChip Plus requires the signals shown in Figure 15 below.

Mobile DiskOnChip

Plus

Address/Data

AVD#

Output Enable

W rite Enable

Chip Enable

Reset

Chip ID

VSS

3.3 V

BUSY#

Busy

VCC

AVD#

OE#

W E#

CE#

RSTIN#

ID0

AD[15:0]

LOCK#

10 nF

0.1 uF

10 nF

0.1 uF

1.8V/3.3V

VCCQ

IRQ#

1-20KOhm

Figure 15: Multiplexed System Interface

9.3 Connecting

Signals

9.3.1 Standard Interface

Mobile DiskOnChip Plus uses standard SRAM-like control signals, which should be connected as follows:

· Address (A[12:0]) Connect these signals to the host address bus.
· Data (D[15:0]) Connect these signals to the host data bus.
· Write (WE#) and Output Enable (OE#) Connect these signals to the host WR# and RD# signals,

respectively.

· Chip Enable (CE#) Connect this signal to the memory address decoder.
· Chip Identification (ID[0:1]) Both signals must be connected to GND if only one Mobile DiskOnChip

Plus is being used. If more than one, refer to Section 9.6 for more information on cascaded configuration.

· Power-On Reset In (RSTIN#) Connect this signal to the host Power-On Reset signal.
· Busy (BUSY#) Connect this signal to an input port. It indicates when the device is ready for first access

after hardware reset.

· Interrupt (IRQ#) Connect this signal to the host interrupt to release the host of this task and improve

performance.

· Byte High Enable (BHE#) This signal definition is compatible with 16 bit platforms that use the

BHE#/BLE# protocol. This signal is only relevant during the boot phase.

· Hardware Lock (LOCK#) This signal prevents the use of the write protect key to disable the protection.
· 8/16 Bit Configuration (IF_CFG) This signal is required for configuring the device for 8 or 16-bit access

mode. When negated, the device is configured for 8-bit access mode. When asserted, 16-bit access mode is
operative.

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

Mobile DiskOnChip Plus derives its internal clock signal from the CE#, OE# and WE# inputs. Since access to
Mobile DiskOnChip Plus' registers is volatile, much like a FIFO or UART, ensure that these signals have clean
rising and falling edges, and are free from ringing that can be interpreted as multiple edges. PC board traces for
these three signals must either be kept short or properly terminated to guarantee proper operation.

9.3.2 Multiplexed Interface

Mobile DiskOnChip Plus can also be configured to work with a multiplexed interface where data and address line
are multiplexed. In this configuration, AVD# input is driven by the host's AVD# signal, and the D[15:0] pins, used
for both address and data, are connected to the host AD[15:0] bus. DiskOnChip address lines A[12:0] and BHE#
should be connected to VSS. IF_CFG should be connected to VCC.

Note: When used in a multiplexed interface, it is not possible to cascade Mobile DiskOnChip Plus 32MB.

This mode is automatically entered when a falling edge is detected on AVD# input. This edge must occur after
RSTIN# is negated and before OE# and CE# are both asserted, i.e. the first read cycle made to Mobile DiskOnChip
Plus must observe the multiplex mode protocol.

Please refer to Section 2.3 for pinout and signal descriptions and to Section 10.4.3 for timing specifications for a
multiplexed interface.

9.4 Implementing the Interrupt Mechanism

9.4.1 Hardware Configuration

To configure the hardware, connect the IRQ# pin to the host interrupt input.

Note: A nominal 10 K pull-up resistor must be connected to this pin.

9.4.2 Software Configuration

Configuring the software to support the IRQ# interrupt is performed in two stages.

Stage 1

Configure the software so that upon system initialization, the following steps occur:

1. The correct value is written to the Interrupt Control register to configure Mobile DiskOnChip Plus for:

· Interrupt source: Flash ready and/or data protection
· Output sensitivity: Either edge or level triggered

Note: Refer to Section 7.10 for further information on the value to be written to this register.

2. The host interrupt is configured to the selected input sensitivity, either edge or level.

3. The handshake mechanism between the interrupt handler and the OS is initialized.

4. The interrupt service routine to the host interrupt is connected and enabled.

Stage 2

Configure the software so that for every long flash I/O operation, the following steps occur:

1. The correct value is written to the Interrupt Control register to enable the IRQ# interrupt.

Note: Refer to Section 7.10 for further information on the value to be written to this register.

2. The flash I/O operation starts.

3. Control is returned to the OS to continue other tasks. When the IRQ# interrupt is received, other interrupts are

disabled and the OS is flagged.

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

4. The OS either returns control immediately to the TrueFFS driver, or waits for the appropriate condition to return

control to the TrueFFS driver.

For further information on implementing the interrupt mechanism, please refer to application note AP-DOC-063,
Improving the Performance of DiskOnChip Plus Devices Using the IRQ# Pin.

9.5 Platform-Specific

Issues

The following section describes hardware design issues.

9.5.1 Wait State

Wait states can be implemented only when Mobile DiskOnChip Plus is designed in a bus that supports a Wait state
insertion, and supplies a WAIT signal.

9.5.2 Big and Little Endian Systems

Power PC, ARM, and other RISC processors can use either Big or Little Endian systems. Mobile DiskOnChip Plus
uses the Little Endian system. Therefore, bytes D[7:0] are its Least Significant Byte (LSB) and bytes D[15:8] are its
Most Significant Byte (MSB). Within the bytes, bit D0 and bit D8 are the least significant bits of their respective
byte. When connecting Mobile DiskOnChip Plus to a device that supports the Big Endian system, make sure to that
the bytes of the CPU and Mobile DiskOnChip Plus match.

Note: Processors like the Power PC also change the bit ordering within the bytes. Failing to follow these rules

results in improper connection of Mobile DiskOnChip Plus and prevents the TrueFFS driver from identifying
Mobile DiskOnChip Plus.

For further information on how to connect Mobile DiskOnChip Plus to support CPUs that use the Big Endian
system, refer to the application note for the relevant CPU.

9.5.3 Busy Signal

The Busy signal (BUSY#) indicates that Mobile DiskOnChip Plus has not yet completed internal initialization. After
reset, BUSY# is asserted while the IPL is downloaded into the internal boot block and the Data Protection Structures
(DPS) are downloaded to the Protection State Machines. After the download process is completed, BUSY# is
negated. It can be used to delay the first access to Mobile DiskOnChip Plus until it is ready to accept valid cycles.

Note: The TrueFFS driver does NOT use this signal to indicate that the flash is in busy state (e.g. program, read, or

erase).

9.5.4 Working with 8/16/32-Bit Systems with a Standard Interface

When using a standard interface, Mobile DiskOnChip Plus can be configured for 8-bit, 16-bit or 32-bit bus
operations.

8-Bit (Byte) Data Access Mode

When configured for 8-bit operation, IF_CFG should be negated. Data should then be driven only on the low data
bus signals D[7:0]. D[15:8] and BHE# are internally pulled up and may be left floating.

16-Bit (Word) Data Access Mode

When configured for 16-bit operation, IF_CFG should be asserted. The following definition is compatible with
16-bit platforms using the BHE#/BLE# protocol:

· When the host BLE# signal asserts Mobile DiskOnChip Plus A0, data is valid on D[7:0].
· When the host BHE# signal asserts Mobile DiskOnChip Plus BHE#, data is valid on D[15:8].
· When both A[0] and BHE# are at logic 0, data is valid on D[15:0].

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

· No data is transferred when both BHE# and A0 are logic 1.
· 16-bit hosts that do not support byte transfers may hardwire the A0 and BHE# inputs to logic 0.

Table 4 shows the active data bus lanes in 16-bit configuration.

Table 4: Active Data Bus Lanes in 16-bit Configuration

Inputs

Data Bus Activity

Transfer Type

BHE# A0 D[7:0] D[15:8]

0 0

Word

0 1

Odd Byte

1 0

Even

Byte

1 1

Operation

Note: Although Mobile DiskOnChip Plus 16/32MB uses 8-bit access to the internal flash, it can be connected to a

16-bit bus. The TrueFFS driver handles all the issues regarding routing data to and from Mobile DiskOnChip
Plus. The Programmable Boot Block is accessed as a true 16-bit device. It responds with the appropriate data
when the CPU issues either an 8-bit or 16-bit read cycle.

32-Bit (Word) Data Access Mode

In a 32-bit bus system that cannot execute byte- or word-aligned accesses, the system address lines SA0 and SA1 are
always zero. Consecutive long-words (32-bit) are differentiated by SA2 toggling. Therefore, in 32-bit systems that
support only 32-bit data access cycles, DiskOnChip A1 is connected to the first system address bit that toggles, i.e.
SA2. DiskOnChip A0 is connected to VSS to configure it for 16-bit operation (see Table 4).

System Host

SA13

SA12

SA11

SA10

SA9

SA8

SA7

SA6

SA5

SA4

SA3

SA2

SA1

SA0

A12

A11

A10

DiskOnChip

Figure 16: 32-Bit (Word) Data Access Mode

Note: The prefix "S" indicates system host address lines

TrueFFS Driver Modifications

TrueFFS supports a wide range of OSs (see Section 6.1.1). The TrueFFS driver is set to work in 8-bit data access
mode as the default. To support 16-bit/32-bit data access modes and their related memory window allocations,
TrueFFS must be modified. In Windows CE and Windows NT Embedded, these changes can be implemented
through the Registry Entries. In all other cases, some minor customization is required in the driver. Please refer to
the readme of each specific driver for further information.

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

9.6 Device

Cascading

9.6.1 Standard Interface

When using a standard interface, up to four Mobile DiskOnChip Plus 16MB or up to two Mobile DiskOnChip Plus
32MB devices can be cascaded, for up to 64MB capacity. No external decoding circuitry or system redesign is
required.

ID[1:0] ball values determine the identity of each device. Systems with only one device must configure it as device
0 by setting ID[1:0] to 00H. Additional devices should be configured as device 1, device 2 and device 3 by setting
ID[1:0] to 01H, 10H and 11H, respectively.

Note: As Mobile DiskOnChip Plus 32MB is a dual die comprised of two internally stacked Mobile DiskOnChip

Plus 16MB devices, only two Mobile DiskOnChip Plus 32MB devices may be cascaded.(Only ID0 is used).

When devices are cascaded, all I/O balls must be wired in common, including the BUSY# output. The ID input balls
should be strapped to VCC or VSS, according to the location of each device. To communicate with a particular
device, its ID must be written into the Device ID Select register (see Section 7.7). Only the device whose ID
corresponds with this value responds to read or write cycles to registers.

Figure 17 illustrates the configuration required to cascade four devices on the host bus. Only the relevant cascading
signals are included in this figure, although all other signals must also be connected.

ID0

ID1

CE#

OE#

WE#

CE#

WE#

OE#

VSS

ID0
ID1

CE#
OE#
WE#

VSS

VCC

2nd

ID0
ID1

CE#
OE#
WE#

VCC

VSS

3rd

ID0

ID1

CE#

OE#

WE#

VCC

4th

1st

Figure 17: Cascading Configuration for Four Devices

9.6.2 Multiplexed Interface

When using a multiplexed interface, up to two Mobile DiskOnChip Plus 16MB devices can be cascaded, for up to
32MB capacity. No external decoding circuitry or system redesign is required.

The ID0 ball value determines the identity of each device. Systems with only one device must configure it as device
0 by connecting ID0 to VSS. The second device should be configured as device 1 by connecting ID0 to VCC.

When two devices are cascaded, all I/O balls must be wired in common, including the BUSY# output. To
communicate with a particular device, its ID must be written into the Device ID Select register (see Section 7.7).
Only the device whose ID corresponds with this value responds to read or write cycles to registers.

Note: Mobile DiskOnChip Plus 32MB devices cannot be cascaded in a multiplexed interface.

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

9.6.3 Memory Map in a Cascaded Configuration

When cascading Mobile DiskOnChip Plus devices, the Programmable Boot Block size is enlarged by 1KB for each
additional 16MB device in the configuration. When four 16MB devices (or two 32MB devices) are connected in a
cascaded configuration, a boot block size of 4KB is available.

The MAX_ID field of the Configuration register can be programmed with the maximum ID value used to enable
access to the boot block of each device in a separate address space.

Initially at power-up, only device 0 responds to reads from the boot block address space with its 1KB of data aliased
at addresses 0K, 1K, 6K and 7K. Figure 18 shows the memory map when the maximum number of devices are
connected in a cascaded configuration, and the location of each IPL.

IPL 3

IPL 2

Flash Area

Window

IPL 1

IPL 0

Programmable

Boot

Block

Reset Mode

0000H

0800H

1000H

1800H

Section 0

Section 1

Section 2

Section 3

Normal Mode

(after setting

MAX_ID)

Programmable

Boot

Block

00H

IPL 0

Control

Registers

Figure 18: Memory Map in a Cascaded Configuration

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

10. Product

Specifications

10.1 Environmental Specifications

10.1.1 Operating Temperature Ranges

Commercial Temperature Range: 0°C to 70°C

Extended Temperature Range:

-40

C to +85

10.1.2 Thermal Characteristics

Table 5: Thermal Characteristics

Thermal Resistance (

°C/W)

Junction to Case (

): 30

Junction to Ambient (

): 85

10.1.3 Humidity

10% to 90% relative, non-condensing.

10.1.4 Endurance

Mobile DiskOnChip Plus is based on NAND flash technology, which guarantees a minimum of 300,000 erase
cycles. Due to the TrueFFS wear-leveling algorithm, the life span of all DiskOnChip products is significantly
prolonged. M-Systems' website (

www.m-sys.com

) provides an online life-span calculator to facilitate application-

specific endurance calculations.

10.2 Disk Capacity

Table 6: Disk Capacity 16MB (in bytes)

DOS 6.22

VxWorks

Formatted Capacity

Sectors

Formatted Capacity

Sectors

16,302,080 31,840 16,367,616 31,968

Table 7: Disk Capacity 32MB (in bytes)

DOS 6.22

VxWorks

Formatted Capacity

Sectors

Formatted Capacity

Sectors

32,800,768 64,064 32,724,992 63,916

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

10.3 Electrical Specifications

10.3.1 Absolute Maximum Ratings

Table 8: Absolute Maximum Ratings

Parameter Symbol Rating

Units

Notes

DC Core Supply Voltage

VCC

-0.6 to 4.6

DC I/O Supply Voltage

VCCQ

-0.6 to 4.6

Input Pin Voltage

-0.6 to VCCQ+0.3,

4.6V max

Input pin Current

-10 to 10

25 °C

Storage Temperature

STG

-55 to 150

°C

Lead Temperature

LEAD

260

°C

sec

Maximum duration of
applying VCCQ without
VCC or VCC without
VCCQ

SUPPLY

500

See Note 3

1. Permanent device damage may occur if absolute maximum ratings are exceeded. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

2. The voltage on any pin may undershoot to -2.0 V or overshoot to 6.6V for less than 20 ns.

3. When operating DiskOnChip with separate power supplies for VCC and VCCQ, it is desirable to turn both supplies on and off
simultaneously. Providing power separately (either at power-on or power-off) can cause excessive power dissipation. Damage to the
device may result if this condition persists for more than 1 second.

10.3.2 Capacitance

Table 9: Capacitance (16MB)

Parameter

Symbol

Conditions

Min

Typ

Max Unit

Input Capacitance

= 0V

Output Capacitance

OUT

= 0V

Capacitance is not 100% tested.

Table 10: Capacitance (32MB)

Parameter

Symbol

Conditions

Min

Typ

Max Unit

Input Capacitance

= 0V

Output Capacitance

OUT

= 0V

Capacitance is not 100% tested.

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

10.3.3 DC Electrical Characteristics Over Operating Range

Table 11: DC Characteristics, 1.65V to 1.95V I/O

Parameter Symbol Conditions

Min

Typ

Max

Unit

Core Supply Voltage

VCC

2.5

3.3

3.6

I/O Supply Voltage

VCCQ

1.65

1.8 1.95 V

High-level Input Voltage

VCCQ

-0.4V

Low-level Input Voltage

0.4 V

High-level Output Voltage

Oh =

-100 µA

VCCQ

-0.1V

D[15:0]
Iol = 100

µA

0.1

Low-level Output Voltage

IRQ#, BUSY#
4 mA

0.3

Input Leakage Current

1,2

ILK

±10

µA

Output Leakage Current

IOLK

±10

µA

Cycle Time = 100 ns (16MB)

Active Supply Current

Cycle Time = 100 ns (32MB)

Deep Power-Down mode

(16MB)

Standby Supply Current
VCC Pins

CCS

Deep Power-Down mode

(32MB)

µA

All inputs 0V or VCCQ 16MB

1.7

Standby Supply Current
VCCQ Pins

CCQS

All inputs 0V or VCCQ 32MB

3.4

µA

1. The CE# input includes a pull-up resistor which sources 0.3~1.4 µA at Vin=0V

2. The D[15:8] and BHE# inputs each include a pull-up resistor which sources 58 ~ 234

µA at Vin = 0V when IF_CFG is a logic-0

3. VCC = 3.3V, VCCQ = 1.8V, Outputs open

4. If DiskOnChip is not set to Deep Power-Down mode and is not accessed for read/write operation, standby supply current is 400 µA (typ.) to
600 µA (max.)

5. Deep Power-Down mode is achieved by asserting RSTIN# (when in Normal mode) or writing the proper write sequence to the DiskOnChip
registers, and asserting the CE# input = VCCQ. See Section 5.3 for further details.

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

Table 12: DC Characteristics, 2.5V-3.6 I/O

Parameter Symbol Conditions

Min

Typ

Max

Unit

Core Supply Voltage

VCC

2.5

3.3

3.6

I/O Supply Voltage

VCCQ

2.5

3.3

3.6 V

High-level Input Voltage

2.1

Low-level Input Voltage

0.7 V

High-level Output Voltage

Oh =

Ohmax

2.4

Low-level Output Voltage

Ol =

Olmax

0.4

3.0V < VCCQ < 3.6V

-4

High-level Output Current

OHM AX

2.5V < VCCQ < 3.0V

-4

3.0V < VCCQ < 3.6V

Low-level Output Current

OHMAX

2.5V < VCCQ < 3.0V

Input Leakage Current

ILK

±10

µA

Output Leakage Current

IOLK

±10

µA

Cycle Time = 100 ns (16MB)

Active Supply Current

Cycle Time = 100 ns (32MB)

Deep Power-Down mode

(16MB)

Standby Supply Current
VCC Pins

CCS

Deep Power-Down mode

(32MB)

µA

1. The CE# input includes a pull-up resistor which sources 0.3~1.4 uA at Vin=0V

2. The D[15:8] and BHE# inputs each include a pull-up resistor which sources 58 ~ 234

µA at Vin = 0V when IF_CFG is a logic-0

3. VCC = VCCQ = 3.3V, Outputs open

4. If DiskOnChip is not set to Deep Power-Down mode and is not accessed for read/write operation, standby supply current is 400 µA (typ.) to
600 µA (max.)

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

Table 14: Standard Interface Read Cycle Timing Parameters (VCC=2.5-3.6V)

VCCQ=VCC

VCC=2.5-3.6V

VCCQ=1.65-1.9V

VCC=2.5-3.6V

Symbol

Description

Min Max Min Max

Units

Tsu(A)

Address to OE# setup time

-2

Tho(A) OE#

to Address hold time

Tsu(CE0) CE# to OE# setup time

Tho(CE0) OE# to CE# hold time

Tho(CE1)

OE# or WE# to CE# hold time

Tsu(CE1) CE# to WE# or OE# setup time

Trec(OE)

OE# negated to start of next cycle

Read access time (RAM)

3,4,5

107

116

Tacc

Read access time (all other addresses)

87 96 ns

Tloz(D) OE#

to D driven

Thiz(D) OE#

to D Hi-Z delay

Asynchronous Boot Mode

tacc(A)

RAM Read access time from A[9:1]

101

tho(A-D)

Data hold time from A[9:1] (RAM)

Note: When designing your board to support DiskOnChip Plus 32MB or 64MB devices, it is not possible to use VCC=2.5-3.6V, as these devices

only support VCC=2.7-3.6V.

Table 15: Standard Interface Read Cycle Timing Parameters (VCC=2.7-3.6V)

VCCQ=VCC

VCC=2.7-3.6V

VCCQ=1.65-1.9V

VCC=2.7-3.6V

Symbol

Description

Min Max Min Max

Units

Tsu(A)

Address to OE# setup time

-2

Tho(A) OE#

to Address hold time

Tsu(CE0) CE# to OE# setup time

-- -- ns

Tho(CE0) OE# to CE# hold time

-- -- ns

Tho(CE1)

OE# or WE# to CE# hold time

Tsu(CE1) CE# to WE# or OE# setup time

Trec(OE)

OE# negated to start of next cycle

Read access time (RAM)

3,4,5

101 111

Tacc

Read access time (all other addresses)

82 92

Tloz(D) OE#

to D driven

15 15 ns

Thiz(D) OE#

to D Hi-Z delay

Asynchronous Boot Mode

tacc(A)

RAM Read access time from A[9:1]

tho(A-D)

Data hold time from A[9:1] (RAM)

1. CE# may be asserted any time before or after OE# is asserted. If CE# is asserted after OE#, all timing relative to when OE# was asserted
will be referenced to the time CE# was asserted.

2. CE# may be negated any time before or after OE# is negated. If CE# is negated before OE#, all timing relative to when OE# was negated
will be referenced to the time CE# was negated.

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

10.4.2 Write Cycle Timing Standard Interface

CE#

A[12:0], BHE#

REC

(WE)

(CE1

(CE0)

(D)

Tw(WE)

(D)

(A)

OE#

D[15:0]

WE#

(CE1

Figure 21: Standard Interface Write Cycle Timing

Table 16: Standard Interface Write Cycle Parameters (VCC=2.5-3.6V)

VCCQ=VCC

VCC=2.5-3.6V

VCCQ=1.65-1.9V

VCC=2.5-3.6V

Symbol

Description

Min Max Min Max

Units

(A)

Address to WE# setup time

-2

Tho(A) WE#

to Address hold time

Tw(WE)

WE#

asserted

width

50 49 ns

WCYC

Write Cycle Time

Tsu (CE0)

CE# to WE# setup time

-- -- ns

Tho (CE0)

WE# to CE# hold time

-- -- ns

Tho (CE1)

OE# or WE# to CE# hold time

Tsu (CE1)

CE# to WE# or OE# setup time

Trec (WE)

WE# to start of next cycle

Tsu(D)

D to WE# setup time

Tho (D)

WE# to D hold time

Note: When designing your board to support also DiskOnChip Plus 32MB or 64MB devices, it is not possible to use VCC=2.5-3.6V, as these

devices only support VCC=2.7-3.6V.

WCYC

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

10.4.3 Read Cycle Timing Multiplexed Interface

CE#

AD[15:0]

REC

(OE)

(CE1)

(CE0)

(CE1)

(CE0)

HIZ

(D)

ACC

(AVD)

OE#

WE#

AVD#

Tw(AVD)

ADDR DATA

Figure 22: Multiplexed Interface Read Cycle Timing

Table 18: Multiplexed Interface Read Cycle Parameters (VCC 2.5-3.6V)

VCCQ=VCC

VCC=2.5-3.6V

VCCQ=1.65-1.9V

VCC=2.5-3.6V

Symbol

Description

Min Max Min Max

Units

tsu(AVD)

Address to AVD# setup time

tho(AVD)

Address to AVD# hold time

Tw(AVD)

AVD# low pulse width

tsu(CE0)

CE#

to OE# setup time

-- --

tho(CE0)

OE#

to CE# hold time

-- -- ns

tho(CE1)

OE# or WE# to CE# hold time

tsu(CE1)

CE# to WE# or OE# setup

time

6 ns

trec(OE)

OE# negated to start of next cycle

Read access time (RAM)

107

116

Tacc

Read access time (all other

addresses)

tloz(D)

OE#

to D driven

Thiz(D) OE#

to D Hi-Z delay

Note: When designing your board to support also DiskOnChip Plus 32MB or 64MB devices, it is not possible to use VCC=2.5-3.6V, as these

devices only support VCC=2.7-3.6V.

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

Table 19: Multiplexed Interface Read Cycle Parameters (VCC=2.7V-3.6V)

VCCQ=VCC

VCC=2.7-3.6V

VCCQ=1.65-1.9V

VCC=2.7-3.6V

Symbol

Description

Min Max Min Max

Units

tsu(AVD)

Address to AVD# setup time

tho(AVD)

Address to AVD# hold time

Tw(AVD)

AVD# low pulse width

tsu(CE0)

CE#

to OE# setup time

-- --

tho(CE0)

OE#

to CE# hold time

-- -- ns

tho(CE1)

OE# or WE# to CE# hold time

tsu(CE1)

CE# to WE# or OE# setup

time

6 ns

trec(OE)

OE# negated to start of next cycle

Read access time (RAM)

101

111

Tacc

Read access time (all other

addresses)

tloz(D)

OE#

to D driven

Thiz(D) OE#

to D Hi-Z delay

1. CE# may be asserted any time before or after OE# is asserted. If CE# is asserted after OE#, all timing relative to OE# asserted will be
referenced instead to the time of CE# asserted.

2. CE# may be negated any time before or after OE# is negated. If CE# is negated before OE#, all timing relative to OE# negated will be
referenced instead to the time of CE# negated.

3. No load (C

= 0 pF).

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

10.4.4 Write Cycle Timing Multiplexed Interface

CE#

REC

(WE)

(CE1)

(CE0)

(D)

Tw(WE)

(D)

OE#

WE#

(CE1)

WCYC

AD[15:0]

(AVD)

AVD#

Tw(AVD)

ADDR

DATA

(AVD-WE)

REC

(WE-AVD)

NEXT ADDR

Figure 23: Multiplexed Interface Write Cycle Timing

Table 20: Multiplexed Interface Write Cycle Parameters (VCC=2.5V-3.6V)

VCCQ=VCC

VCC=2.5-3.6V

VCCQ=1.65-1.9V

VCC=2.5-3.6V

Symbol

Description

Min Max Min Max

Units

tsu(AVD)

Address to AVD# setup time

tho(AVD)

Address to AVD# hold time

Tw(AVD)

AVD# low pulse width

tsu(AVD-WE)

AVD# to WE# setup time

Trec(WE-AVD) WE# to AVD# in next cycle

WE# asserted width (RAM)

tw(WE)

WE# asserted width (all other addresses)

Twcyc

Write Cycle Time

tsu(CE0)

CE#

to WE# setup time

tho(CE0)

WE#

to CE# hold time

tho(CE1)

OE# or WE# to CE# hold time

tsu(CE1) CE#

to WE# or OE# setup time

trec(WE) WE#

to start of next cycle

Tsu(D)

D to WE# setup time (RAM)

Tho(D) WE#

to D hold time

Note: When designing your board to support also DiskOnChip Plus 32MB or 64MB devices, it is not possible to use VCC=2.5-3.6V, as these

devices only support VCC=2.7-3.6V.

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

Table 21: Multiplexed Interface Write Cycle Parameters (VCC=2.7-3.6V)

VCCQ=VCC

VCC=2.7-3.6V

VCCQ=1.65-1.9V

VCC=2.7-3.6V

Symbol

Description

Min Max Min Max

Units

tsu(AVD)

Address to AVD# setup time

tho(AVD)

Address to AVD# hold time

Tw(AVD)

AVD# low pulse width

tsu(AVD-WE)

AVD# to WE# setup time

Trec(WE-AVD) WE# to AVD# in next cycle

WE# asserted width (RAM)

tw(WE)

WE# asserted width (all other addresses)

Twcyc

Write Cycle Time

tsu(CE0)

CE#

to WE# setup time

tho(CE0)

WE#

to CE# hold time

tho(CE1)

OE# or WE# to CE# hold time

tsu(CE1) CE#

to WE# or OE# setup time

trec(WE) WE#

to start of next cycle

Tsu(D)

D to WE# setup time (RAM)

Tho(D) WE#

to D hold time

1. CE# may be asserted any time before or after WE# is asserted. If CE# is asserted after WE#, all timing relative to WE# asserted will be
referenced instead to the time of CE# asserted.

2. CE# may be negated any time before or after WE# is negated. If CE# is negated before WE#, all timing relative to WE# negated will be
referenced instead to the time of CE# negated.

3. WE# may be asserted before or after the rising edge of AVD#. The beginning of the WE# asserted pulse width spec is measured from the
later of the falling edge of WE# or the rising edge of AVD#.

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

10.4.5 Power-Up Timing

Mobile DiskOnChip Plus is reset by assertion of the RSTIN# input. When this signal is negated, DiskOnChip
initiates a download procedure from the flash memory into the internal Programmable Boot Block. During this
procedure, Mobile DiskOnChip Plus does not respond to read or write accesses.

Host systems must therefore observe the requirements described below for first access to Mobile DiskOnChip Plus.
Any of the following methods may be employed to guarantee first-access timing requirements:

a. Use a software loop to wait at least Tp (BUSY1) before accessing the device after the reset signal is

negated.

b. Poll the state of the BUSY# output.
c. Use the BUSY# output to hold the host CPU in wait state before completing the first access.

Host systems that boot from Mobile DiskOnChip Plus must employ option c), or use another method to guarantee
the required timing for first-time access.

RSTIN#

VCC

BUSY#

VCC = 2.5V

VCCQ = 1.65 or 2.5V

(BUSY1)

REC

(VCC-RSTIN)

CE#, OE#, WE#

(VCC-BUSY0)

(D-BUSY1)

D (Read cycle)

(BUSY-CS)

(RSTIN)

(BUSY0)

AVD#

(Muxed Mode Only)

(RSTIN-AVD)

A[12:0], BHE#

(BUSY-A)

VALID

Figure 24: Reset Timing

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

Table 22: Power-Up Timing Parameters

Symbol Description

Min

Max

Units

REC

(VCC-RSTIN)

VCC/VCCQ stable to RSTIN# 500

µs

Tp (VCC-BUSY0)

VCC/VCCQ stable to BUSY# 500 µs

(RSTIN)

RSTIN# asserted pulse width

(BUSY0)

RSTIN# to BUSY#

(BUSY1)

RSTIN#

to BUSY#

1.3

(BUSY-CE)

BUSY#

to CE# 0

(D-BUSY1)

Data valid to BUSY# 0

Tho(RSTIN-AVD)

RSTIN#

to AVD# low hold

1. Specified from the final positive crossing of Vcc above 2.5V and VCCQ above 1.65 or 2.5V.

2. If the assertion of RSTIN# occurs during a flash erase cycle, this time could be extended by up to 500

µS.

3. Normal read/write cycle timing applies. This parameter applies only when the cycle is extended until the negation of the BUSY#
signal.

4. Applies to multiplexed interface only.

5. When operating DiskOnChip with separate power supplies for VCC and VCCQ, it is recommended to turn both power supplies
on and off simultaneously. Providing power separately (either at power-on or power-off) can cause excessive power dissipation.
Damage to the device may result if this condition persists for more than 1 second.

10.4.6 Interrupt Timing

The interrupt timing is illustrated in Figure 25, and described in Table 23.

IRQ#

Tw(IRQ)

Figure 25: IRQ# Pulse Width in Edge Mode

Table 23: Interrupt Timing

Symbol Description Min

Max

Units

Tw(IRQ)

IRQ# asserted pulse width (edge mode)

300

800

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O

Data Sheet, Rev. 1.7

95-SR-000-10-8L

How to Contact Us

Internet:

http://www.m-sys.com

General Information:

info@m-sys.com

Sales and Technical Information:

techsupport@m-sys.com

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M-Systems Inc.
8371 Central Ave, Suite A
Newark CA 94560
Phone: +1-510-494-2090
Fax: +1-510-494-5545

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Room B, 13 F, No. 133 Sec. 3
Min Sheng East Road
Taipei, Taiwan
R.O.C.
Tel: +886-2-8770-6226
Fax: +886-2-8770-6295

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Shinagawa-ku Tokyo, 141-0022
Tel: +81-3-5423-8101
Fax: +81-3-5423-8102

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25A International Business Commercial Bldg.
Nanhu Rd., Lou Hu District
Shenzhen, China 518001
Phone: +86-755-2519-4732
Fax: +86-755-2519-4729

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M-Systems Ltd.
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Kfar Saba 44425, Israel
Tel: +972-9-764-5000
Fax: +972-3-548-8666

This document is for information use only and is subject to change without prior notice. M-Systems Flash Disk Pioneers Ltd.
assumes no responsibility for any errors that may appear in this document. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrievable manner or translated into any language or computer language, in any form or by any
means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise, without prior written consent of M-Systems.

M-Systems products are not warranted to operate without failure. Accordingly, in any use of the Product in life support systems or
other applications where failure could cause injury or loss of life, the Product should only be incorporated in systems designed with
appropriate and sufficient redundancy or backup features.

Contact your local M-Systems sales office or distributor, or visit our website at

www.m-sys.com

to obtain the latest specifications

before placing your order.

DiskOnChip

, DiskOnChip Millennium

DiskOnKey

and TrueFFS

are registered trademarks of M-Systems. FFDTM and

SuperMAPTM are trademarks of M-Systems. Other product names mentioned in this document may be trademarks or registered
trademarks of their respective owners and are hereby acknowledged.

Document Outline

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Document Outline

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