LB1875

No. 6002-1/17

LB1875

Polygon Mirror Motor Predriver IC

Monolithic Digital IC

The LB1875 is a predriver IC for polygon mirror

motors. By using a driver array or discrete transis-

tors (FETs) at the output, motor drive with high

rotation precision is possible. PAM drive or direct

PWM drive can be selected for the output to realize

high-efficiency control with minimum power loss.

Package Dimensions

unit: mm

3235-HSOP36

Overview

SANYO : HSOP36

[LB1875]

Features

· Three-phase bipolar drive

· Direct PWM drive (bottom side) or PAM drive selectable

· PLL speed control circuit

· PWM oscillator

· Quartz oscillator

· Frequency divider

· FG with Schmitt comparator

· FG input single edge, dual edge selector circuit

· Integrating amplifier

· Phase lock detector output

· Current limiter

· Motor lock protection

· Thermal protection

· Forward/reverse circuit

· 5V regulator output

D0898RM(KI)

Ordering number : EN6002

SANYO Electric Co., Ltd. Semiconductor Business Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

6.2

0.8

17.9

2.7

0.3

(4.9)

1.3

10.5

0.65

0.25

0.55

7.9

2.25

2.5max

0.1

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

LB1875

No. 6002-2/17

Specifications

Maximum Ratings

at Ta = 25

Operation Conditions

at Ta = 25

Parameter

Symbol

Conditions

Ratings

Unit

Maximum supply voltage

max

14.5

Output current

max

Allowable power dissipation

Pd max

IC only

0.9

2.1

Operating temperature

Topr

Storage temperature

Tstg

20 to +80

55 to +150

with substrate (114.3 x 76.1 x 1.6 mm

glass exposy)

Parameter

Symbol

Conditions

Ratings

Unit

Maximum supply voltage

8 to 13.5

When shorted between V

and V

REG

4.5 to 5.5

Output current

5V regulated output current

REG

0 to 20

Voltage applied at LD pin

0 to 13.5

LD pin output current

L D

0 to 10

Voltage applied at PWM pin

PWM

0 to 13.5

PWM pin output current

PWM

0 to 20

100

120

0.8

0.5

1.18

0.9

0.4

1.2

1.6

2.0

2.1

2.4

Ambient temperature, Ta °C

Power dissipation, Pd max W

Pd max Ta

With substrate

(114.3 x 76.1 x 1.6 mm, glass exposy)

IC only

LB1875

No. 6002-3/17

Electrical Characteristics

at Ta = 25

C, V

= 12V

Continued on next page

min

typ

max

Power supply current

C C

[5V regulated output ]

Output fluctuation

REG

4.65

5.0

5.35

Voltage fluctuation

REG

=8 to 13.5V

100

Load fluctuation

REG

=0 to 15 mA

100

Temperature coefficcient

REG

Design target value

mV/

[Output Section]

Output saturation voltage

(sat)1-1 UH, VH, WH "L" level, I

=50

0.1 0.3

Vo(sat)1-2 UH, VH, WH "L" level, I

=10 mA

0.9 1.1

(sat)2

UH, VH, WH "L" level, I

=20 mA

0.9

1.1

(sat)3

UL, VL, WL, I

=20 mA

0.2 0.4

Output leak current

leak

UL, VL, WL

[Hall amplifier]

Input bias current

(HA)

4 1

Same-phase input voltage range

ICM

0 V

2.0

Hall input sensitivity

30 mV

P-P

Hysteresis width

(HA)

8 14 24

Input voltage L->H

SLH

7 mV

Input voltage H->L

SHL

7 mV

[FG/Schmitt comparator section]

Input bias current

(FGS)

4 1

Same-phase input voltage range

ICM

(FGS)

0 V

2.0

Input sensitivity

(FGS)

30 mV

P-P

Hysteresis width

(FGS) Design target value

Input voltage L->H

SLH

(FGS) Design target value

Input voltage H->L

SHL

(FGS) Design target value

[PWM oscillator]

Output High level voltage

(OSC)

2.7 3.0

3.3

Output Low level voltage

(OSC)

1.5 1.8 2.1

Oscillator frequency

f(OSC)

C=2200 pF

kHz

Amplitude

V(OSC)

1.0

1.2 1.4

P-P

[PWM output]

Output saturation voltage

(PWM) I

PWM

=15 mA

0.9 2.0

Output leak current

(PWM)

[CSD oscillator ]

Output High level voltage

(CSD)

2.5 2.8 3.1

Output Low level voltage

(CSD)

0.55 0.85 1.15

External C charge current

CHG

13 10 7

External C discharge current

CHG

10 13

Oscillator frequency

CSD

C=0.068

35 Hz

Amplitude

CSD

1.75

1.95 2.15

P-P

[Phase comparator output]

Output High level voltage

PDH

=100

REG

0.2

REG

0.1

Output Low level voltage

PDL

=100

0.1 0.2

Output source current

REG

0.6

Output sink current

REG

1.5 mA

[Phase lock detector output]

Output saturation voltage

(LD)

=10 mA

0.1

0.4

Output leak current

(LD)

Ratings

Parameter

Symbol

Conditions

Unit

LB1875

No. 6002-4/17

Continued on next page

Continued from preceding page

min

typ

max

[ERR amplifier]

Input offset voltage

(ER)

Design target value

10 +10

Input bias current

(ER)

1 +1

Ouput High level voltage

(ER)

= 500

REG

1.2

REG

0.9

Ouput Low level voltage

(ER)

=500

0.9 1.2

DC bias level

(ER)

REG

[Current limiter]

Limiter voltage

0.45 0.5

0.55

[Low-voltage protection circuit]

Operation voltage

SDL

3.55

3.75 3.95 V

Release voltage

SDH

3.8 4.0

4.2

Hysteresis width

VSD

0.15 0.25 0.35

[Thermal shutdown operation]

Termal shutdown temperature

TSD

Design target value (junction temperature)

150 180

Hysteresis width

TSD

Design target value (junction temperature)

[SOFT pin]

Stop voltage

SFT

In stop condition

3.0

3.3

3.6

External C discharge current

D C H G

[Quartz oscillator]

Quartz oscillator frequency

OSC

2 10

MHz

Low level pin voltage

OSCL

OSC

=0.5 mA

1.45

High level pin voltage

OSCH

OSC

OSCL

+0.6V

0.5 mA

[CLK

OUT

pin]

Output saturation voltage

(CKOUT)

CKOUT

=2 mA

0.1

0.4

Output leak current

(CKOUT) V

[CLK

pin]

External input frequency

I(CKIN)

0.1 10

kHz

High level input voltage

IH(CKIN)

3.5 V

REG

Low level input voltage

IL(CKIN

)

0 1.5

Input open voltage

IO(CKIN)

REG

0.5

REG

Hysteresis width

IS(CKIN)

0.3

0.4 0.5

High level input current

IH(CKIN)

CKIN

REG

10 0

+10

Low level input current

IL(CKIN)

CKIN

=0V

200 140

[S/S pin]

High level input voltage

(SS)

3.5 V

REG

Low level input voltage

(SS)

0 1.5

Input open voltage

(SS)

REG

0.5

REG

Hysteresis width

(SS)

0.3 0.4 0.5

High level input current

(SS)

VS/S=V

REG

10 0

+10

Low level input current

(SS)

VS/S=0V

200 140

[F/R pin]

High level input voltage

(FR)

3.5 V

REG

Low level input voltage

(FR)

1.5 V

Input open voltage

(FR)

REG

0.5

REG

High level input current

(FR)

VF/R=V

REG

10 0

+10

Low level input current

(FR)

VF/R=0V

200 140

[FG

SEL

pin]

High level input voltage

(FSEL)

3.5

REG

Low level input voltage

(FSEL)

1.5

Input open voltage

(FSEL)

REG

0.5

REG

High level input current

(FSEL)

FSEL

REG

10 0

+10

Low level input current

(FSEL)

FSEL

=0V

200 140

Ratings

Parameter

Symbol

Conditions

Unit

+ 5%

LB1875

No. 6002-5/17

3-phase logic truth table (IN = "H" indicates the IN

> IN

condition)

FGSEL pin

Continued from previous page

CLKSEL pin

S/S pin

LIM pin

Pin Assignment

IN1

IN2

IN3

IN1

IN2

IN3

SOURCE

SYNC

F/R= "L"

F/R= "H"

Output

Input state

Condition

Input state

Edge detection

Input state

Divisor

High or open

Stop

High or open

FG dual edge

High or open

1024 x 4

Start

FG single edge

1024

1024 x 3

Input state

Output pin (UH, VH, WH)

PWMOUT pin

High or open

No PWM (PAM operation)

PWM output

PWM (direct PWN operation)

FG/Schmitt comparator output

min

typ

max

[CLK

SEL

pin]

High level input voltage

(CSEL)

4.0

REG

Middle level input voltage

(CSEL)

2.0

3.0

Low level input voltage

(CSEL)

0 1.0

Input open voltage

(CSEL)

REG

0.5

REG

High level input current

(CSEL) V

CSEL

REG

10 0

+10

Low level input current

(CSEL) V

CSEL

=0V

200 140

[LIM pin]

High level input voltage

(LIM)

3.5

REG

Low level input voltage

(LIM)

1.5 V

Input open voltage

(LIM)

REG

0.5

REG

High level input current

(LIM)

LIM

REG

10 0

+10

Low level input current

(LIM)

LIM

=0V

200 140

Ratings

Parameter

Symbol

Conditions

Unit

REG

S/S

CLK

SEL

CLK

OUT

F/R

SEL

LIM

LD1

LD2

TOC

SOFT

PWM

GND

PWM

OUT

IN3

IN2

IN1

CSD

GND

LB1875

A11348

LB1875

No. 6002-6/17

Block Diagram and Sample Application Circuit

(Sample application: PAM drive, FET output)

Note: For applications where the motor has variable speed and control at low motor voltages is required, the base voltage of the

output interface transistor must be made low. In this case, a P-channel FET which can be used at low gate voltages must be

selected.

FILTER

SELECT

CLK

SELECT

OSC

ECL

1/8

1/128
1/384
1/512

CLK

PWM

OSC

S/S

F/R

VREG

LVSD

TSD

COMP

PWM

LOGIC

OSC

HALL LOGIC

HALL

HYS AMP

CURR

LIM

PRI

DRIVER

PLL

VREG

FGIN

CLKIN

CLKOUT

CPWM

VREG

S/S

F/R

CSD

CLKSEL

FGSEL

IN1+

IN1

IN2+

IN2

IN3+

IN3 SOFT

GND

LIM

VCC

TOC

PWM
OUT

VREG

VCC

LD1

LD2

VREG

24V

12V

A11596

LB1875

No. 6002-9/17

Description of the LB1875

1. Speed control circuit

This IC uses the PLL speed control technique which allows stable, high-precision motor rotation with low jitter. The PLL circuit

performs phase comparison of the falling edge of the clock input (CLK

) with the edge of the FG input. Control is based on the

differential output.

When the FG

SEL

pin is Low, only the falling edge of the FG signal is valid. When the pin is High or open, both edges are valid. When

both edges are used, the FG waveform precision becomes critical.

When using an external clock input (supplied from CLK

pin), the FG servo frequency is determined by the following equation.

(servo) = f

CLK

(FG

SEL

= Low)

(servo) = f

CLK

/2 (FG

SEL

= High or open)

When using the internal clock, the FG servo frequency is determined by the following equation. The number of FG pulses and the

quartz oscillator frequency determine the motor rotation speed.

(servo) = f

OSC

/N (FG

SEL

= Low)

(servo) = f

OSC

/2N (FG

SEL

= High or open)

OSC

: Quartz oscillator frequency

N: Clock divisor (see table)

2. Output drive

This IC allows selection of PAM drive or direct PWM drive.

When the LIM pin is Low, the direct PWM mode is selected. The ON duty cycle of the UH, VH, and WH output (external bottom-

side transistor drive output) changes, thereby controlling the motor speed. Current control is also realized by changing the ON duty

cycle to limit the current. At this time, the Schmitt comparator output of the FG is supplied at the PWM

OUT

pin. When bipolar

transistors are used externally, the top-side transistors should not have an integrated diode, but Schottky barrier diodes should be used

instead (to prevent feedthrough current caused by diode reverse recovery during PWM switching).

When the LIM pin is High or open, the PAM drive mode is selected. The PWM

OUT

pin carries the PWM signal. This output can drive

an external switching regulator circuit for varying the motor supply voltage and thereby controlling motor speed. Current control is

also realized by changing the motor supply voltage. In this case, a delay in the switching regulator circuit will cause a delay in the

current control action. During the delay, a higher current than the set current may flow, which must be taken into consideration when

selecting output transistors. For applications where the motor has variable speed and control at low motor voltages is required, the

lowest operation voltage is limited by the base voltage of the interface transistor for top-side output transistor drive. If this causes a

problem, the base voltage must be made low (for example by dividing the V

REG

voltage with resistors). When FETs are used as top-

side output transistors, types which can be used at low gate voltages must be selected.

3. Current limiting circuit

The current limiting circuit limits the peak current to the value I = V

/Rf (V

= 0.5V typ., Rf: current detector resistor). As

mentioned above, in PAM drive mode, a current higher than the set current may flow during the delay interval. If the capacitor

charge current of the switching regulator circuit is a problem, a smoothing capacitor may be inserted, with the negative side connected

to the RF pin.

If PWM noise is a problem in the RF waveform, a filter should be provided at the input.

LB1875

No. 6002-10/17

Oscillator frequency (MHz)

C1 (

C2 (pF)

C3 (pF)

R1 ( )

2 to 3

0.1

100

330k

3 to 7

0.1

None

330k

7 to 9

0.1

None

330k

9 to 10

0.1

None

330k

4. Reference clock

Since the clock input of the PLL circuit (CLK

) and the internal divisor output (CLK

OUT

) are separate, various applications are

possible.

(1) Using the internal divider circuit

Basically, CLK

and CLK

OUT

are shorted. If a division ratio other than the built-in ratio is required, an external divider circuit can be

inserted between these two pins.

[1] Using a quartz oscillator

An oscillator using a quartz crystal and C, R components can be configured as shown below.

The circuit configuration and values are for reference only. The quartz crystal characteristics as well as the possibility of floating

capacitance and noise due to layout factors must be taken into consideration when designing an actual application.

[Precautions for wiring layout design]

Since the quartz oscillator circuit operates at high frequencies, it is susceptible to the influence of floating capacitance from the

circuit board. Wiring should be kept as short as possible and traces should be kept narrow.

[2] External clock input (equivalent to quartz oscillator, several MHz)

When using an external signal source instead of a quartz oscillator, a resistor of about 13 k

should be inserted in series at the X

input. The XO pin should be left open.

Signal input level

Low: 0 to 0.8 V

High: 2.5 to 5 V

(2) When not using the internal divider circuit

When using an external signal source to supply a signal equivalent to the FG frequency (several kHz), the signal is input via the

CLK

pin. When not using a quartz oscillator, the X

pin should be left open or connected to the V

REG

pin (XO is open).

5. Hall input signal

The Hall input requires a signal with an amplitude of at least the hysteresis width (24 mV max.). Taking possible noise influences

into consideration, an amplitude of at least 100 mV is desirable. If noise at the Hall input is a problem, a noise-canceling capacitor

(about 0.001 to 0.1

F) should be connected across the Hall input pins .

Since the same-phase input range is 0 to V

2V, a Hall element can be connected in series if 12V is applied at the V

pin.

6. FG input signal

The FG input is designed mainly for input from a Hall element and has the same specifications as the Hall input. If the input is to be

used for an FG pattern or other very low-level signal, an external amplifier must be used to amplify the signal first.

When there is noise at the FG input, locking may be impaired and jitter may increase. If PWM switching noise or other noise is found

to be present, countermeasures such as making the Hall element power supply more stable or connecting a capacitor across the input

will be necessary.

(Reference values)

C1, R1 : For stable oscillation

C2 : For overtone oscillation prevention

: For crystal coupling

VREG

A11349

LB1875

No. 6002-11/17

7. PWM frequency

The PWM frequency is determined by the capacitance connected to the C

PWM

pin.

f PWM 1/(15000 x C)

The PWM frequency should be between 15 and 50 kHz. If the frequency is too low, noise and control performance may be a

problem. If it is too high, switching losses will increase.

8. LD output

The LD1 output is ON when phase lock is achieved. Phase lock is evaluated only by the phase (through edge comparison), not by

speed deviation. Therefore when LD1 is ON, speed deviation is affected by the FG signal acceleration for example when establishing

the lock condition. (The lower the acceleration, the lower the speed deviation.) When it is necessary to limit speed deviation when

LD1 is ON, the results of actual motor speed measurement must be applied.

9. Power supply

When using FETs as bottom-side output transistors, applying a voltage of 12V to the V

pin makes it possible to supply a gate

voltage of about 10V. When using FETs or bipolar transistors that can handle a low gate voltage, the V

and V

REG

pins can also be

short- circuited to apply 5V. (In this case, do not apply voltage higher than 5.5V.)

Since this IC is designed for use in high-current motors, the power supply line may fluctuate easily. Therefore a capacitor of

sufficient capacitance must be provided between the V

pin and ground, to assure stable operation. If a diode is used in the power

line for reverse-connection protection, power line fluctuations may be further increased, which will require more capacitance.

10. Motor lock protection circuit

To protect the IC and the motor itself when rotation is inhibited, a motor lock protection circuit is provided. If the LD output is High

(unlocked) for a certain interval in the start condition, the external bottom-side transistors are turned off. The length of the interval

is determined by the capacitance at the CSD pin. A capacitance of 0.1

F results in a trigger interval of about 10 seconds.

Trigger interval (S) 110 x C (

The trigger interval should be set so as to leave sufficient leeway for motor startup. Speed reduction due to clock frequency switching

does not trigger the protection circuit.

When the protection circuit has been triggered, the condition can only be canceled by setting the system to the stop condition or by

turning the power off and on again. When wishing not to use the motor lock protection circuit, connect the CSD pin to ground.

11. Low voltage protection circuit

The low voltage protection circuit cuts off the bottom-side output transistors (external) when the voltage at the V

REG

pin falls below

3.75V (typ.). The circuit action is released when the voltage rises above approx. 4.0V (typ.).

12. F/R switching

Forward/reverse switching in principle should be carried out while the motor is stopped. If switching is carried out while the motor

is running, feedthrough current (due to output transistor delay) is prevented by the circuit design, but a high current will flow in the

output transistors (due to counterelectromotive voltage and coil resistance). If such a condition is anticipated, the output transistors

must be selected appropriately, to allow handling even higher current than in normal use.

13. Soft start

In PAM drive mode, connecting a capacitor (approx. 0.01 to 0.1

F) between the SOFT pin and ground enables soft start (gradual

increase in PWM ON duty cycle, causing a sloped rise in motor supply voltage). This prevents the current flow exceeding the set

current due to switching regulator circuit delay at startup. The Soft start function is active only immediately after motor startup.

When the motor is stopped, the output transistors are turned off, therefore the charge accumulated in the switching regulator smoothing

capacitors can only be discharged as leak current of the output transistors. When the motor is restarted before the supply voltage has

dropped, the soft start function will not be active. Therefore it is necessary to discharge the capacitors via a resistor so that the soft

start function operates properly.

LB1875

No. 6002-12/17

Pin number

Pin name

Equivalent circuit

Pin function

REG

S/S

CLK

SEL

Pin Descriptions

5V regulator output (control circuit

power supply)

For stable operation, pin should be

connected to ground via a capacitor

(0.1

F or more).

Pin 2: Quartz oscillator input. Maximum

oscillation frequency is 10 MHz

Pin 3: Quartz oscillator output

Generates reference clock. When an

external clock (several MHz) is used,

connect a resistor of about 13 k in

series to the X

pin, so that the signal is

input via the resistor. Leave the X

open.

Start/stop pin

Low: Start

High: Stop

High when open.

Divisor selector pin

"L": (divisor 3072): 0 to 1.0V

"M": (divisor 1024): 2.0 to 3.0V

"H": (divisor 4093): 4.0V to V

REG

High when open.

Continued on next page

VCC

A11350

VREG

A11351

VREG

5.6 K

30 k

A11352

VREG

5.6 k

30 k

A11353

LB1875

No. 6002-13/17

Pin number

Pin name

Equivalent circuit

Pin function

CLK

OUT

F/R

SEL

LIM

Continued from preceding page

Clock input (max. 10 kHz)

Low: 0 to 1.5V

High: 3.5V to V

REG

High when open.

Quartz oscillator divider output

Ratio is selected with pin 5.

Open collector output

Forward/reverse switching pin

Low: 0 to 1.5V

High: 3.5V to V

REG

High when open.

FG comparator selector pin

Low: 0 to 1.5V

> Speed control on FG single edge

High: 3.5V to V

REG

> Speed control on FG dual edge

High when open.

Drive mode selector pin

Low: 0 to 1.5V

> Direct PWM drive mode

High: 3.5 V to V

REG

> PAM drive mode

High when open.

Continued on next page

VREG

5.6 K

30 k

A11354

VREG

A11355

VREG

5.6 k

30 k

A11356

VREG

5.6 k

30 k

A11357

VREG

5.6 k

30 k

A11358

LB1875

No. 6002-14/17

Pin number

Pin name

Equivalent circuit

Pin function

LD1

LD2

TOC

SOFT

Continued on next page

Continued from preceding page

Phase lock detector output

On when PLL phase lock is achieved.

Open collector output

Phase lock detector output

(LD1 inverted output)

On when PLL phase lock is achieved.

Open collector output

Phase comparator output (PLL output)

Outputs the phase difference as a signal

with changing pulse duty cycle. The

higher the duty cycle, the higher the

output current.

Differential amplifier output

Output current increases at Low.

Torque control input

Normally connected to EO pin. When

TOC pin goes Low, duty cycle of UH,

VH, WH (direct PWM mode) or PWM

output (PAM mode) changes, resulting

in increased torque.

Soft start control pin

Connect to ground via a capacitor.

Leave open when soft start is not to be

used.

Differential amplifier input

11 12

VREG

A11359

VREG

A11360

VREG

200

A11361

20 k

VREG

A11362

200

VREG

A11363

200

LB1875

No. 6002-15/17

Pin number

Pin name

Equivalent circuit

Pin function

PWM

OUT

Continued on next page

Continued from preceding page

PWM oscillator pin

Connect to ground with a capacitor to

set oscillation frequency.

PWM output

Open collector output (Darlington

connection). In direct PWM mode (LIM

pin Low) the output is an FG Schmitt

output.

Output current detector pin

Connect to ground via a lower resistor.

Sets maximum output current I

OUT

0.5/Rf.

Output pin (for external bottom-side

transistor drive)

Performs duty cycle control in direct

PWM mode (LIM pin Low).

Output pin (for external bottom-side

transistor drive) .

Open collector output.

VREG

200

A11364

2 k

VREG

A11365

VREG

5 k

A11366

21 23 25

VCC

A11367

22 24 26

VCC

A11368

LB1875

No. 6002-16/17

Pin number

Pin name

Equivalent circuit

Pin function

IN1

IN2

IN3

CSD

FRAME

GND

Continued from preceding page

Power supply pin (output and regulator

circuit power supply). Connect to

ground via capacitor to prevent noise.

When using the IC with a single 5V

source, short this pin to the V

REG

pin.

Hall inputs for various phases

Logic "High" indicates V

FG comparator input

Pin 35: Non-inverted input

Pin 36: Inverted input

Reference signal oscillator for motor

lock protection circuit, clock interrup-

tion error protection circuit etc.

Connect to ground via capacitor.

Connect directly to ground if protection

circuit is not to be used.

Ground

VCC

200

A11369

200

VCC

200

A11370

200

VREG

200

A11371

LB1875

No. 6002-17/17

This catalog provides information as of December, 1998. Specifications and information herein are subject to change

without notice.

Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer's products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.

In the event that any or all SANYO products(including technical data,services) described or
contained herein are controlled under any of applicable local export control laws and regulations,
such products must not be exported without obtaining the export license from the authorities
concerned in accordance with the above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co. , Ltd.

Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LB1875