POWER MANAGEMENT
1
www.semtech.com
SC1104A/B
Simple, Synchronous
Voltage Mode PWM Controller
Features
Applications
Revision 7, July 2003
Typical Application Circuit
Description
The SC1104A/B is a versatile voltage-mode PWM con-
troller designed for use in single ended DC/DC power
supply applications. A simple, fixed frequency high effi-
ciency buck regulator can be implemented using the
SC1104A/B with a minimum of external components.
Internal level shift and drive circuitry eliminates the need
for an expensive P-channel, high-side switch. The small
device footprint allows for compact circuit design.
SC1104A/B features include temperature compensated
voltage reference, triangle wave oscillator, current limit
comparator and an externally compensated error ampli-
fier. Current limit is implemented by sensing the voltage
drop across the top FET's R
DS(ON)
.
The SC1104 operates at fixed frequencies of
300kHz(A) or 600kHz(B) providing an optimum com-
promise between efficiency, external component size,
and cost. 600kHz switching frequency is reserved for
the SC1104B, +5V operation only.
SC1104A/B has a thermal protection circuit, which is
activated if the junction temperature exceeds 150C.
+5V or +12V 300kHz operation (SC1104A)
+5V 600kHz operation (SC1104B)
High efficiency (>90%)
1% Reference voltage accuracy
Hiccup mode over current protection
Robust output drive
R
DS(ON)
Current sensing
Industrial temperature range
SO-8 package
Termination supplies
Low cost microprocessor supplies
Peripheral card supplies
Industrial power supplies
High density DC/DC conversion
Typical Distributed Power Supply
Figure 1
Q1
Si4884DY
Q2
Si4874DY
L1
1.5-6.8uH
C9
0.1
C10
220/4V
C11
220/4V
C12
220/4V
C13
220/4V
C6
47/16V
C5
47/16V
+
_
+
_
Vin 5 to 12V
3.3V
R3
1.00k
R4
2.32k
C3
1
C14-17
1.0
C7
47/16V
VCC
7
DL
3
DH
4
PHASE
6
COMP/SS
1
BST
5
SENSE
8
GND
2
U1
SC1104A/B
R6
1-5.1
R7
1-5.1
R1
200-2k
D1
MBRA130L
C2
0.01
C4
10.0
C1
510-1500pF
C8
0.1-0.33
R5
200-1k
R8
opt
D2
(opt)
2
2003 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC1104A/B
Electrical Characteristics
Absolute Maximum Ratings
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Unless specified: A: V
CC
= 12 0.6V, V
BST
= 23 1V, V
OUT
= 3.3V, T
J
= T
A
= 25
o
C.
B: V
CC
= 5 0.25V, V
BST
= 12 0.6V, V
OUT
= 2.0V, T
J
= T
A
= 25
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6
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
3
2003 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC1104A/B
Electrical Characteristics
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V
Unless specified: A: V
CC
= 12 0.6V, V
BST
= 23 1V, V
OUT
= 3.3V, T
J
= T
A
= 25
o
C.
B: V
CC
= 5 0.25V, V
BST
= 12 0.6V, V
OUT
= 2.0V, T
J
= T
A
= 25
o
C
4
2003 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC1104A/B
Figure 2
Block Diagram
Figure 3
Electrical Characteristics
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5
1
C
Unless specified: A: V
CC
= 12 0.6V, V
BST
= 23 1V, V
OUT
= 3.3V, T
J
= T
A
= 25
o
C.
B: V
CC
= 5 0.25V, V
BST
= 12 0.6V, V
OUT
= 2.0V, T
J
= T
A
= 25
o
C
5
2003 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC1104A/B
Pin Configuration
Ordering Information
Pin Descriptions
Top View
(8-Pin SOI
C)
n
i
P
#
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N
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g
a
k
c
a
P
T
(
e
g
n
a
R
p
m
e
T
J
)
R
T
S
I
X
4
0
1
1
C
S
)
1
(
8
-
C
I
O
S
C
5
2
1
o
t
0
4
-
B
V
E
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1
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v
E
Notes:
(1) In place of "X": A = 300kHz, V
CC
= 5V to 12V.
B = 600kHz, V
CC
= 5V.
(2) Only available in tape and reel packaging. A reel
contains 2500 devices.
Marking Information
yyww = Date Code (Example: 0012)
xxxxxxxx = Semtech Lot No. (Example: E90101-1)
6
2003 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC1104A/B
Synchronous Buck Converter
The output voltage of the synchronous converter is set
and controlled by the output of the error amplifier. The
inverting input of the error amplifier receives its voltage
from the SENSE pin. The non-inverting input of the error
amplifier is connected to an internal 1V reference.
The error amplifier output is connected to the
COMPensation pin. The error amplifier generates a cur-
rent proportional to (Vsense 1V), which is the COMP
pin output current (Transconductance ~ 12mS). The
voltage on the COMP pin is the integral of the error am-
plifier current. The COMP voltage is the non-inverting
input to the PWM comparator and controls the duty cycle
of the MOSFET drivers. The size of capacitor Ccomp con-
trols the stability and transient response of the regula-
tor. The larger the capacitor, the slower the COMP volt-
age changes, and the slower the duty cycle changes.
The inverting input voltage of the PWM comparator is
the triangular output of the oscillator.
When the oscillator output voltage drops below the COMP
voltage, the comparator output goes high. This pulls DL
low, turning off the low-side FET. After a short delay ("dead
time"), DH is pulled high, turning on the high-side FET.
When the oscillator voltage rises back above the error
amplifier output voltage, the comparator output goes low.
This pulls DH low, turning off the high-side FET, and after
a dead time delay, DL is pulled high, turning on the low-
side FET. The dead time delay is determined by a
monostable on the chip.
The triangle wave minimum is about 1V, and the maxi-
mum is about 2V. Thus, if Vcomp = 0.9V, high side duty
cycle is the minimum (~0%) , but if Vcomp is 2.0V, duty
cycle is at maximum ( ~90%).The internal oscillator uses
an on-chip capacitor and trimmed precision current
sources to set the oscillation frequency to 300kHz
(SC1104A) or 600kHz (SC1104B).
Figure 1 shows a 3.3V output converter. If the Vout <3.3V,
then the SENSE voltage < 1V. In this case the error
amplifier will be sourcing current into the COMP pin so
that COMP voltage and duty cycle will gradually increase.
If Vout > 3.3V, the error amplifier will sink current and
reduce the COMP voltage, so that duty cycle will decrease.
The circuit will be in steady state when Vout =3.3V ,
Vsense = 1V, Icomp = 0 . The COMP voltage and duty
cycle depend on Vin.
Under Voltage Lockout
The under voltage lockout circuit of the SC1104A/B as-
sures that both high-side and low-side MOSFET driver
outputs remain in the off state whenever the supply volt-
age drops below set parameters. Lockout occurs if V
CC
falls below 4.2V typ.
R
DS(ON)
Current Limiting
In case of a short circuit or overload, the high-side (HS)
FET will conduct large currents. To prevent damage, in
this situation, large currents will generate a fault condi-
tion and begin a soft start cycle.
While the HS driver is on, the phase voltage is compared
to the Vcc pin voltage. If the phase voltage is 200mV
lower than Vcc, a fault is latched and the soft start cycle
begins.
The voltages are compared during the middle of the HS
pulse, to prevent transients from affecting the accuracy.
The sampling of the voltage across the top FET occurs
after a time delay t
DELAY
= 100ns_typ from the time the
DH is pulled high. This delay prevents the measurement
to be effected by ringing on the leading edge of the phase
node pulse. The duration of the sampling is t
SAMPLE
=
100ns_typ. It is being disabled at very low duty cycle when
t
ON
< 300ns_typ. This feature allows for the orderly start-
up during the inrush of the current charging output ca-
pacitor and the fault free operation with extremely high
input/output voltage ratio, e.g., V
IN
= 12V and V
OUT
= 1V.
The over-current comparator (OC) is only active if the
phase node is > 3.3V. This means that in the case of
power source being < 3V the OC will be disabled even
though the rest of the circuitry is completely functional.
SC1104 still can be used for stepping down, e.g. 2.8V to
2.5V, 2V, 1.8V, etc.
Theory of Operation
7
2003 Semtech Corp.
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POWER MANAGEMENT
SC1104A/B
Theory of Operation (Cont.)
When choosing OC trip point one should consider the
Tempco of the MOSFETs Rds_on and SC1104's Vtrip.
Also, any ringing on the Vcc and Phase nodes due to
parasitic L and C will have some effect on the OC Vtrip.
Example:
Iout_nom = 6A; assume I_max = 125% Iout_nom =
7.5A
Rds_on = 0.014
; assume Rds_on_max
150%
Rds_on = 0.02
Voc = 7.5A 0.02
= 150mV.
This proves that MOSFETs with R
DS_ON
= 0.014
@
25C
is the right choice.
Soft Start
The soft start (or hiccup) circuitry is activated when a
fault occurs. Faults occur for three reasons:
1) Under voltage (V
CC
< 4.2V)
2) Over temperature (die temperature > 150C)
3) Over current in high side FET.
All faults are handled the same way. Both DH and DL are
forced low. The error amplifier is turned off, but a 2A
current flows into the comp pin (soft start current). The
sink current reduces the Comp voltage down to 0.6V
over a period of a few milliseconds. When Vcomp ~ 0.6V,
the fault is cleared and the DL goes high. Also, the soft
start current changes polarity and begins to increase the
voltage on the Comp capacitor. The DH remains low, be-
cause Vcomp is less than the lowest excursion of the
oscillator ramp (1.0V). After a few ms, the Vcomp in-
creases to about 1.0V and the DH will start to switch.
The duty cycle will gradually increase, and Vsns will in-
crease. When Vsns ~ 1.00V, the error amplifier turns on
again. The circuit has now reached its operating point. If
a fault occurs during the soft start, the cycle will begin
again (drivers low, Vcomp decreasing down to 0.6V).
Closing the Loop
In order to have a stable closed loop system with optimum
transient response one should make sure that open-loop
frequency response has an adequate Gain & Phase
margins. The Bode plot of log. Gain vs Freq. and Phase
vs Freq. provide the necessary means for the circuit
evaluation. Loop stability defined by compensation
networks around transconductance error amplifier (EA)
and output divider, see below and output capacitor Cout
and inductor Lout.
Cp
Cn
Ra
Rn
Rb
+
_
Vref
Vout
EA
Gm
Typical transconductance error amplifier
The inductor and output capacitor form a "double pole"
at the frequency:
=
Co
Lo
2
1
f
LC
The ESR of the output capacitor and the output capacitor
value create a "zero" at the frequency.
=
Co
ESR
2
1
f
ESR
The "zero" and "pole" from the EA compensation network
are:
=
Cc
Rc
2
1
f
Z
=
Cp
Rc
2
1
f
P
The additional "lead" network R
A
, C
N
, R
N
can be used to
improve phase margin in case when output capacitors
with extra-low ESR are used and there is a need to
compensate for "high quality" output Lo, Co filter.
C
C
R
C
8
2003 Semtech Corp.
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POWER MANAGEMENT
SC1104A/B
=
Cn
Ra
2
1
f
NET
Value for the resistor R
N
should be 1/10 of the output
divider upper resistor R
A
.
Example.
Switching frequency f
SW
= 300kHz
Output capacitance C
OUT
= 3 x 330
F
Output capacitor ESR = 45m
/each
Output inductance L
OUT
= 4.7
H
Input voltage V
IN
= 12V
Output voltage V
OUT
= 3.3V
Let's choose crossover frequency
f
CO
= 1/20
f
SW
= 15kHz
The compensation values used in this example are based
on the following criteria:
f
Z
= f
LC
; f
NET
= 1/10
f
LC
; f
P
= 10
f
CO
= 150kHz
Therefore,
kHz
33
.
2
F
990
H
4.7
2
1
f
LC
=
=
kHz
72
.
10
F
990
015
.
0
2
1
f
ESR
=
=
Since, the EA can sink/source about 1mA, let's choose
Rc = 680
, then
F
1
.
0
Rc
Fz
2
1
C
C
=
=
pF
1500
Rc
Fp
2
1
C
P
=
=
Assuming the output divider lower resistor R
B
= 1k, then
for V
OUT
= 3.3V the R
A
= 2.32k.
F
3
.
0
Ra
f
2
1
C
NET
N
=
=
At the closed-loop crossover frequency f
CO
, the
Theory of Operation (Cont.)
attenuation due to the L
O
, C
O
filter and the output
resistor divider R
A
, R
B
is compensated by the gain of
the PWM modulator and the gain of the
transconductance error amplifier (Gm
EA
Z
COMP
).
Shown below is a typical Bode plot of the open-loop
frequency response of SC1104 based buck converter.
1
10
100
1k
10k
100k
1Meg
frequency in hertz
-450
-350
-250
-150
-50.0
v
phe
r
r
i
n
degr
ees
-80.0
-40.0
0
40.0
80.0
v
dbe
r
r
i
n
db(
v
o
lt
s
)
Pl
o
t
1
1
2
1
vdberr
2
vpherr
9
2003 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC1104A/B
Evaluation Board Schematic - V
IN
= 5V
Evaluation Board Schematic - V
IN
= 12V
Q1
Si4410DY
Q2
Si4410DY
L1
3.9uH
C4
0.1
C9
47/6.3V
C8
47/6.3V
+
_
+
_
Vin=5V
Vout=2.5@6A
R7
1.0k
R8
1.50k
C3
1.0
C10
47/6.3V
VCC
7
DL
3
DH
4
PHASE
6
COMP/SS
1
BST
5
SENSE
8
GND
2
U1
SC1104AISTR
R3
1
R4
2.2
R1
1k
0
C2
0.1
C7
10.0
D2
MBRA130L(opt)
R5
0
R6
2.2
C5
6800p
C11
0.47
R9
150
C1
1500p
C18
10
D1
MBRA130L
C15
330/4V
C16
330/4V
C17
330/4V
Q1
Si4410DY
Q2
Si4410DY
L1
4.7uH
C4
0.1
C9
33/16V
C8
33/16V
+
_
+
_
Vin=12V
Vout=3.3@6A
R7
1.0k
R8
2.32k
C3
1.0
C10
33/16V
VCC
7
DL
3
DH
4
PHASE
6
COMP/SS
1
BST
5
SENSE
8
GND
2
U1
SC1104AISTR
R3
2.2
R4
2.2
R1
680
0
C2
0.1
C7
10.0
D2
MBRA130L(opt)
R5
5.1opt
R6
3.3
C5
3300p
C11
0.33
R9
220
C1
1500p
C18
10
D1
LL4148
C15
330/4V
C16
330/4V
C17
330/4V
10
2003 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC1104A/B
Evaluation PC Board
Top View
Top Layer
Bottom Layer
11
2003 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC1104A/B
Typical Characteristics
60%
65%
70%
75%
80%
85%
90%
95%
100%
0
2
4
6
8
10
12
Current, A
E
ffi
ci
e
n
c
y
-1.0%
-0.8%
-0.6%
-0.4%
-0.2%
0.0%
0.2%
0.4%
0.6%
0.8%
1.0%
0
2
4
6
8
10
12
Current, A
R
e
gul
a
t
i
o
n
12V = Vin
3.3V = Vout
12A = Iout
12
2003 Semtech Corp.
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POWER MANAGEMENT
SC1104A/B
5V = Vin
2V = Vout
12A = Iout
Typical Characteristics (Cont.)
60%
65%
70%
75%
80%
85%
90%
95%
100%
0
2
4
6
8
10
12
Current, A
E
ffi
ci
e
n
cy
-1.0%
-0.8%
-0.6%
-0.4%
-0.2%
0.0%
0.2%
0.4%
0.6%
0.8%
1.0%
0
2
4
6
8
10
12
Current, A
R
e
gu
l
a
t
i
on
13
2003 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC1104A/B
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
Outline Drawing - SO-8
Contact Information
Land Pattern - SO-8
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