POWER MANAGEMENT
1
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SC1112
Triple Low Dropout
Regulator Controllers
.eatures
Applications
Revision 7, October 2001
Typical Application Circuit
Description
The SC1112 was designed for the latest high speed
motherboards. It includes three low dropout regulator con-
trollers. The controllers provide the power for the system
AGTL bus Termination Voltage, Chipset, and clock circuitry.
An adjustable controller with a 1.2V reference is available,
while two selectable outputs are provided for the VTT
(1.25 V or 1.5V, SC1112) or (1.2V or 1.5V, SC1112A)
and the AGP (1.5V or 3.3V). The SC1112 low dropout
regulators are designed to track the 3.3V power supply
as the VTTIN supply is cycled On and Off. A latched short
circuit protection is also available for the VTT output.
Other features include an integrated charge pump that
provides adequate gate drives for the external Mosfets,
and a capacitive programable delay for the power good
signal.
K
Triple linear controllers
K
Selectable and Adjustable Output Voltages
K
LDOs track input voltage within 200mV (.unction of
the Mosfets used) until regulation
K
Integrated Charge Pump
K
Programmable Power Good delay Signal
K
Latched Over Current Protection (VTT)
K
Pentium
III Motherboards
K
Triple power supplies
Q 1
R A
SC1112/A
PWRGD
DELAY
5VSTBY
VTTSEL
AGPSEL
GND
FC
CAP+
CAP-
VTTGATE
VTTSEN
AGPGATE
AGPSEN
ADJGATE
ADJSEN
VTTIN
A D J
Q 2
C 1 4
330u
C 1 2
330u
AGP SELECT Signal
C 8
330u
A G P
C 1 7
0.1u
R B
C 1 6
330u
C 3
0.1u
C 1
10u
C 1 8
330u
VTT SELECT Signal
P O W E R G O O D
C 5
22n
C 1 0
1u
C 1 3
0.1u
+3.3V
R 1
1 K
+5V STBY
Q 3
C 1 1
0.1u
C 9
0.1u
VTT
C 6
330u
VTT
C 1 9
330u
C 2
2
2001 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC1112
Electrical Characteristics
Absolute Maximum Ratings
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3
2001 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC1112
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Electrical Characteristics (Cont.)
Unless specified: 5VSTBY=4.75V to 5.25V; VTTIN=3.3V; T
A
= 25C
Notes:
(1) All electrical characteristics are for the application circuit on page 19.
(2) Guaranteed by design
(3) Tracking Difference is defined as the delta between 3.3V Vin and the VTT, AGP, ADJ output voltages during the linear ramp up until
regulation is achieved. The Tracking Voltage difference might vary depending on MOSFETs Rdson, and Load Conditions.
(4) During power up, an internal short circuit glitch timer will start once the VTT Input Voltage exceeds the VTTIN
TH
(1.5V). During the glitch
timer immunity time, determined by the Delay capacitor (Delay time is approximately equal to (Cdelay*SCTH)/ISC), the short circuit
protection is disabled to allow VTT output to rise above the trip threshold (0.7V). If the VTT output has not risen above the trip
threshold after the immunity time has elapsed, the VTT output is latched off and will only be enabled again if either the VTT input
voltage or the 5VSTBY is cycled.
(5) PWRGD pin is kept low during the power up, until the VTT output has reached its PG
td1.2
or PG
td1.5
level. At that time the PWRGD
source current I
PG
(20uA) is enabled and will start charging the external PWRGD delay capacitor connected to the DELAY pin. Once the
capacitor is charged above the PG
Delay_TH
(1.5V), the PWRGD pin is released from ground.
4
2001 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC1112
VTTGATE
VTTIN=1.5V
The delay capacitor does not
begin charging until VTTIN has
reached 1.5V and VTT is above
the powergood threshold of
1.08V.
Once DELAY reaches 1.5V,
the PWRGD signal goes high.
VTTGATE initially turns on
hard, until VTT reaches
regulation. Then VTTGATE
drops to its normal regulating
level.
PWRGD
DELAY
VTT
VTTIN
DELAY=1.5V
NORMAL STARTUP CONDITION
The delay capacitor does not
begin charging until VTTIN has
r e a c h e d 1 . 5 V a n d V T T i s b e l o w
the short circuit threshold of
0 . 7 V .
VTTGATE initially turns on hard
a n d i s l a t c h e d o f f w h e n D E L A Y
r e a c h e s 1 . 5 V a n d V T T i s b e l o w
0 . 7 V
D E L A Y
V T T
P W R G D
V T T I N
V T T G A T E
VTTIN=1.5V
S H O R T - C I R C U I T S T A R T U P
DELAY=1.5V
Timing Diagrams
5
2001 Semtech Corp.
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POWER MANAGEMENT
SC1112
P W R G D
DELAY=1.5V
D E L A Y
V T T
S H O R T - C I R C U I T D U R I N G N O R M A L
O P E R A T I O N
O n c e V T T d r o p s o u t o f
r e g u l a t i o n , V T T G A T E t u r n s o n
harder to try and raise VTT.
W h e n V T T d r o p s b e l o w 1 . 0 8 V ,
the delay capacitor is
d i s c h a r g e d a n d P W R G D g o e s
l o w . W h e n V T T d r o p s b e l o w
0.7V, the delay capacitor
b e g i n s c h a r g i n g .
If VTT is still below 0.7V when
D E L A Y r e a c h e s 1 . 5 V ,
V T T G A T E i s l a t c h e d o f f .
V T T I N
VTT=0.7V
VTT=1.08V
V T T G A T E
VTT=0.7V
P W R G D
VTT=1.08V
D E L A Y
S H O R T - C I R C U I T A N D R E C O V E R Y
D U R I N G N O R M A L O P E R A T I O N
V T T
O n c e V T T d r o p s o u t o f
r e g u l a t i o n , V T T G A T E t u r n s o n
harder to try and raise VTT.
W h e n V T T d r o p s b e l o w 1 . 0 8 V ,
the delay capacitor is discharged
a n d P W R G D g o e s l o w . W h e n
VTT drops below 0.7V, the delay
capacitor begins charging.
I f V T T r e c o v e r s a b o v e 0 . 7 V
b e f o r e D E L A Y r e a c h e s 1 . 5 V ,
D E L A Y i s a g a i n d i s c h a r g e d .
If VTT reaches 1.08V the delay
capacitor begins charging and
normal operation continues.
V T T I N
VTT=1.08V
V T T G A T E
DELAY=1.5V
Timing Diagrams (Cont.)
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