POWER MANAGEMENT
1
www.semtech.com
SC1164 & SC1165
Programmable Synchronous DC/DC
Converter, Dual LDO Controller
Features
Applications
Revision 1, January 2001
Description
The SC1164/5 combines a synchronous voltage mode con-
troller with two low-dropout linear regulators providing
most of the circuitry necessary to implement three DC/
DC converters for powering advanced microprocessors
such as Pentium
II .
The SC1164/5 switching section features an integrated 5
bit D/A converter, pulse by pulse current limiting, inte-
grated power good signaling, and logic compatible shut-
down. The SC1164/5 switching section operates at a fixed
frequency of 200kHz, providing an optimum compromise
between size, efficiency and cost in the intended applica-
tion areas. The integrated D/A converter provides pro-
grammability of output voltage from 2.0V to 3.5V in 100mV
increments and 1.30V to 2.05V in 50mV increments with
no external components.
The SC1164/5 linear sections are low dropout regulators.
The SC1164 supplies 1.5V for GTL bus and 2.5V for non-
GTL I/O, the SC1165 features adjustable LDO voltages.
u
Synchronous design, enables no heatsink solution.
u
95% efficiency (switching section).
u
5 bit DAC for output programmability.
u
On chip power good function.
u
Designed for Intel Pentium
ll VRM8.1 requirements.
u
1.5V, 2.5V or Adjustable @ 1% for linear section.
u
Pentium
ll microprocessor supplies
u
Flexible motherboards
u
1.3V to 3.5V microprocessor supplies
u
Programmable triple power supplies
Typical Application Circuit
O V P
+
4 . 7 u F
U 4
S C 1 1 6 4 / 5 C S W
1
5
6
7
8
9
1 0
1 1
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
1 3
1 2
1 4
2 4
2
2 3
3
4
A G N D
V C C
O V P
P W R G O O D
C S -
C S +
P G N D H
D H
B S T H
E N
V O S E N S E
V I D 4
V I D 3
V I D 2
V I D 1
V I D 0
D L
P G N D L
B S T L
G A T E 2
G A T E 1
L D O V
L D O S 1
L D O S 2
1 0
+
3 3 0 u F
5 m O h m
x4
I R L R 3 1 0 3 N
0 . 1 u F
V I D 3
1 . 5 V
I R L R 3 1 0 3 N
V I D 1
+
3 3 0 u F
0 . 1 u F
+
1 5 0 0 u F
1 2 V
0 . 1 u F
V C C _ C O R E
2 . 3 2 k
V I D 0
I R L R 0 2 4 N
+
3 3 0 u F
2 R 2
5 V
3 . 3 V
2 R 2
V I D 4
P W R G O O D
V I D 2
1 . 9 u H
I R L R 0 2 4 N
E N
+
1 5 0 0 u F
2 . 5 V
0 . 1 u F
1 . 0 0 k
x2
5
2001 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC1164 & SC1165
Block Diagram
S Y N C H R O N O U S
D R I V E
VCC
R
S
Q
+
-
7 0 m V
LDOS1
1 . 2 6 5 V
R E F
VID0
LDOS2
D / A
PWRGOOD
R E F
EN
OVP
A G N D
+
-
LDOV
O S C I L L A T O R
GATE1
L E V E L S H I F T
A N D H I G H S I D E
D R I V E
DL
PGNDL
+
-
+
-
DH
O P E N
C O L L E C T O R S
VID3
GATE2
BSTH
S H O O T
T H R U
C O N T R O L
+
-
C U R R E N T L I M I T
VOSENSE
+
-
F E T
C O N T R O L L E R
2 . 5 V / A D J .
A G N D
VID1
AGND
E R R O R
A M P
F E T
C O N T R O L L E R
1 . 5 V / A D J .
CS+
BSTL
V C C
PGNDH
VID4
VID2
CS-
Setting LDO Output Voltage.
R
B
R
A
V
T
U
O
)
2
O
D
L
(
1
O
D
L
V
5
4
.
3
5
0
1
2
8
1
V
0
3
.
3
5
0
1
9
6
1
V
0
1
.
3
2
0
1
7
4
1
V
0
9
.
2
0
0
1
0
3
1
V
0
8
.
2
0
0
1
1
2
1
V
0
5
.
2
0
0
1
6
.
7
9
V
0
5
.
1
0
0
1
7
.
8
1
For the SC1165, LDO Output voltages must be set by se-
lecting appropriate resistor values. These values may be
determined from the eqution below, or from the table at
right.
error
t
significan
cause
not
does
term
)
R
(I
the
that
so
enough
low
be
must
R
ion
clarificat
for
diagram
layout
See
resistor
feedback
Bottom
R
resistor
feedback
Top
R
current
bias
pin
Feedback
I
:
where
)
R
I
(
R
)
R
R
(
265
.
1
V
A
FB
A
B
A
FB
A
FB
B
B
A
OUT
=
=
=
+
+
=
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