1
www.semtech.com
SC4612
Wide Input Range High Performance
Synchronous Buck Switching Controller
POWER MANAGEMENT
Description
Features
Applications
Typical Application Circuit
Wide input voltage range, up to 28V
Internally regulated DRV
Output voltage as low as 0.5V
1.7A gate drive capability
Asynchronous start up mode
Low side R
DS-ON
sensing with hiccup mode current
limit
Programmable current limit
Programmable frequency up to 1.2 MHz
Available in MLPD-12 and SOIC-14 lead free
packages. This product is fully WEEE and RoHS
compliant
SC4612 is a high performance synchronous buck controller
that can be configured for a wide range of applications.
The SC4612 utilizes synchronous rectified buck topology
where high efficiency is the primary consideration. SC4612
is optimized for applications requiring wide input supply
range and low output voltages down to 500mV.
SC4612 implements an asynchronous soft-start mode,
which keeps the lower side MOSFET off during soft-start, a
desired feature when a converter turns on into a preset
external voltage or pre-biased output voltage. With the lower
MOSFET off, the external bus is not discharged, preventing
any disturbances in the start up slope and any latch-up of
modern day ASIC circuits.
SC4612 comes with a rich set of features such as regulated
DRV supply, programmable soft-start, high current gate
drivers, internal bootstrapping for driving high side
N-channel MOSFET, shoot through protection, R
DS-ON
sensing
with hiccup over current protection, and asynchronous start
up with over current protection.
Distributed power architectures
Telecommunication equipment
Servers/work stations
Mixed signal applications
Base station power management
Point of use low voltage high current applications
Revision: September 21, 2005
Q1
Q2
L1
C8
C10
+
_
+
_
Vin
Vout
R3
R4
C5
R1
C1
C9
C2
R5
C3
D1
C7
C4
R2
R6
C6
ILIM
1
PHASE
12
OSC
2
SS/EN
3
FB
5
VDD
6
GND
7
DL
8
DRV
9
BST
10
DH
11
EAO
4
U1
SC4612MLP
2
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
Absolute Maximum Ratings
All voltages with respect to GND. Positive currents are into, and negative currents are out of the specified terminal. Pulsed
is defined as a less than 10% duty cycle with a maximum duration of 500ns. Consult Packaging Section of Data sheet for
thermal limitations and considerations of packages.
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in
the Electrical Characteristics section is not implied.
Note:
(1). 1 sq. inch of FR-4, double-sided, 1 oz copper weight.
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2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
VIN = VDD = 12V, F
OSC
= 600kHz, T
A
= T
J
= -40
C to 125C.
Unless otherwise specified:
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Electrical Characteristics
Note:
(1). Guaranteed by design.
4
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
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Electrical Characteristics (Cont.)
Unless otherwise specified:
Note:
(1). Guaranteed by design.
VIN = VDD = 12V, F
OSC
= 600kHz, T
A
= T
J
= -40
C to 125C.
5
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
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Unless otherwise specified:
Note:
(1). Guaranteed by design.
Electrical Characteristics (Cont.)
VIN = VDD = 12V, F
OSC
= 600kHz, T
A
= T
J
= -40
C to 125C.
6
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
Timing Diagrams
SS/EN
2.75V
EAO
DH
DL
Soft Start Duration
Asynchronous
Operation
0.5V
0.8V
1.3V
VCC
Vcc
UVLO
4.58V
No fault start up sequence
SS/EN
2.75V
EAO
DH
DL
0.5V
0.8V
1.3V
VCC
Vcc
UVLO
4.58V
Over current fault at Asynchronous start up sequence
Fault
occur
EOA<FB+0.7V
Soft Start Duration
Asynchronous
Operation
Fault removed,
normal operation resumed
Fault
present for
10 cycles
7
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
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Pin Configurations
Ordering Information
Notes:
(1) When ordering please specify MLPD or SOIC
package.
(2) Only available in tape and reel packaging. A reel
contains 2500 devices.
(3) Lead free product. This product is fully WEEE and
RoHS compliant.
1
2
3
4
5
6
7
PHASE
ILIM
TOP VIEW
(12 Pin MLPD)
12
8
DH
OSC
BST
SS/EN
DRV
EAO
DL
FB
GND
VDD
10
9
11
Top Mark
Marking Information
nnnn
= Part Number (Example: 1531)
yyww
= Date Code (Example: 0012)
xxxxx
= Semtech Lot No. (Example:E9010)
4612
yyww
xxxxx
1
2
3
4
5
6
7
PHASE
NC
TOP VIEW
(14 Pin SOIC)
13
12
14
11
10
DH
ILIM
BST
OSC
DRV
SS/EN
DL
EAO
GND
VDD
FB
NC
9
8
8
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
Pin Descriptions
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2
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C
T
9
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
Block Diagram
OCP @ Asynchronous Start up
EAO > FB + 0.7
True
False
for more than 10
cycles
Allow
Synchronous
mode
Soft Start
Cycle
PWM
Enable
Vcc
UVLO
SS
+
-
800mV
PWM
Disable
Vcc UVLO
+
-
Over Voltage Protection
S Q
R
FB
600mV
20% OVP
Low Side 100% on
Top Side off
PWM
Enable
+
-
FB
Vref
Synchronous
Mode
S Q
R
PWM
Enable
Low Side
Rdson OCP
S Q
R
PWM
Enable
PWM
Disable
+
-
SS
Vref+0.5
REF
INTERNAL REGULATOR
&
BANDGAP GENERATOR
VDD
DRV
GND
Oscillator
900mV
OSC
Current
Limit
ILIM
SOFT START
&
Enable
SS/EN
TOP Side
Gate Driver
BST
DH
PHASE
PWM Control
Low Side
Gate Driver
VCC
DL
GND
BST
DH
PHASE
DL
+
-
Error
Amp.
FB
SS
FB
+
-
EN
SYNC
OCP
Synchronous
Mode
PWM
PWM
EAO
OTP
OVP
OCP
OVP
OTP
Q
S R
SS
10
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
Applications Information
INTRODUCTION
The SC4612 is a versatile voltage mode synchronous
rectified buck PWM convertor, with an input supply (VIN)
ranging from 4.5V to 28V designed to control and drive
N-channel MOSFETs.
The power dissipation is controlled using a novel low volt-
age supply technique, allowing high speed and integra-
tion with the high drive currents to ensure low MOSFET
switching loss. The synchronous buck configuration also
allows converter sinking current from load without losing
output regulation.
The internal reference is trimmed to 500mV with 1%
accuracy, and the output voltage can be adjusted by two
external resistors.
A fixed oscillator frequency (up to 1.2MHz) can be
programmed by an external capacitor for an optimized
design.
During the Asynchronous start up, the SC4612 provides a
top MOSFET shut down over current protection, while under
normal operating conditions a low side MOSFET R
DS-ON
current sensing with hiccup mode over current protection,
minimizes power dissipation and provides further
protection.
Other features of the SC4612 include:
Wide input power voltage range (from 4.5V to 28V), low
output voltages down to 500mV, externally programmable
soft-start, hiccup over current protection, wide duty cycle
range, thermal shutdown, asynchronous start-up
protection, and a -40 to 125C junction operating
temperature range.
THEORY OF OPERATION
SUPPLIES
Two pins (VDD and DRV) are used to power up the SC4612.
If input supply (VDD) is less than 10V (MAX), tie DRV and
VDD together.
This supply should be bypassed with a low ESR 2.2uF (or
greater) ceramic capacitor directly at the DRV to GND pins
of the SC4612.
The DRV supply also provides the bias for the low and the
high side MOSFET gate drive.
The maximum rating for DRV supply is 10V and for
applications where input supply is below 10V, it may be
connected directly to VDD.
START UP SEQUENCE
Start up is inhibited until VDD input reaches its UVLO
threshold. The UVLO limit is 4.5V (TYP).
Meanwhile, the high side and low side gate drivers DH,
and DL, are kept low. Once VDD exceeds the UVLO
threshold, the external soft-start capacitor starts to be
charged by a 25A current source. If an over current
condition occurs, the SS/EN pin will discharge to 500mV
by an internal switch. During this time, both DH and DL
will be turned off.
When the SS pin reaches 0.8V, the converter will start
switching. The reference input of the error amplifier is
ramped up with the soft-start signal. Initially only the high
side driver is enabled. Keeping the low side MOSFET off
during start up is useful where multiple convertors are
operating in parallel. It prevents forward conduction in the
freewheeling MOSFET which might otherwise cause a dip
in the common output bus.
In case of over current condition which is longer than 10
cycles during the asynchronous start up, SC4612 will turn
off the high side MOSFET gate drive, and the soft-start
sequence will repeat.
When the SS pin reaches 1.3V, the low side MOSFET will
begin to switch and the convertor is fully operational in
the synchronous mode. The soft-start duration is
controlled by the value of the SS cap. If the SS pin is pulled
below 0.5V, the SC4612 is disabled and draws a typical
quiescent current of 5mA.
Bias Generation
A 4.5V to 10V (MAX) supply voltage is required to power
up the SC4612. This voltage could be provided by an ex-
ternal power supply or derived from VDD (VDD >10V)
through an internal pass transistor.
The internal pass transistor will regulate the DRV from an
external supply >10V connected to VDD to produce 7.8V
(TYP) at the DRV pin.
Soft start / Shut down
An external capacitor at the SS/EN pin is used to set up
the soft-start duration. The capacitor value in conjunction
with the internal current source, controls the duration of
soft-start time. If the SS/EN pin is pulled down to GND,
the SC4612 is disabled. The soft-start pin is charged by a
25A current source and discharged by an internal switch.
When SS/EN is released it charges up to 0.5V as the con-
trol circuit starts up.
11
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
Applications Information (Cont.)
The reference input of the error amplifier is effectively
ramped up with the soft-start signal. The error amp output
will vary between 100mV and 1.2V, depending on the duty
cycle. The error amp will be off until SS/EN reaches 0.7V
(TYP) and will move the output up to its desired voltage by
the time SS/EN reaches 1.3V. The gate drivers will be in
asynchronous mode until the FB pin reaches 500mV.
The intention for the asynchronous start up is to keep the
low side MOSFET from being switched on which forces the
low side MOSFETs body diode or the parallel Schottky di-
ode to conduct. The conduction by the diode prevents any
dips in an existing output voltage that might be present,
allowing for a glitch free start up in applications that are
sensitive to any bus disturbances.
During the asynchronous start up SC4612 monitors the
output and if within 10 cycles the FB has not reached the
internal soft start ramp level, the device switches to syn-
chronous mode. This provides an added protection in case
of short circuit at the output during the asynchronous start
when the bottom MOSFET is not being switched to provide
the R
DS-ON
sensing current limit protection.
In case of a current limit, the gate drives will be held off
until the soft-start is initiated. The soft-start cycle defined
by the SS cap being charged from 800mV to 1.3V
and
slowly discharged to achieve an approximate hiccup duty
cycle of 1% to minimize excessive power dissipation.
The part will try to restart on the next softstart cycle. If the
fault has cleared, the outputs will start . If the fault still
remains, the part will repeat the soft-start cycle above in-
definitely until the fault has been removed.
The soft-start time is determined by the value of the
softstart capacitor (see formula below).
SS
SS
SS
I
2
.
1
X
C
T
Oscillator Frequency Selection
The internal oscillator sawtooth signal is generated by
charging an external capacitor with a current source of
100A charge current.
See Table 1 "Frequency vs. C
OSC
" on page 14 to determine
oscillator frequency.
OVERCURRENT PROTECTION
SC4612 features low side MOSFET on-state Rds current
sensing and hiccup mode over current protection. ILIM pin
would be connected to DRV or PHASE via programming
resistors to adjust the over current trip point to meet
different customer requirements.
The sampling of the current thru the bottom FET is set at
~150ns after the bottom FET drive comes ON. It is done to
prevent a false tripping of the current limit circuit due to
the ringing at the phase node when the top FET is turned
OFF.
Internally overcurrent threshold is set to 100mV_typ. If
voltage magnitude at the phase node during sampling is
such that the current comparator meets this condition then
the OCP occurs.
Connecting a resistor from external voltage source such
as VDD, DRV, etc. to ILIM increases the current limit.
Connecting a resistor from ILIM to PHASE lowers the current
limit (see the block diagram in page 9).
Internal current source at ILIM node is ~20A. External
programming resistors add to or subtract from that source
and hence vary the threshold.
The tolerance of the collective current sink at ILIM node is
fairly loose when combined with variations of the FET's
Rds(on). Therefore when setting current limit some iteration
might be required to get to the wanted trip point.
Nonetheless, this circuit does serve the purpose of a hard
fault protection of the power switches. When choosing the
current limit one should consider the cumulative effect of
the load and inductor ripple current. As a rule of thumb,
the limit should be set at least x10 greater then the pk-pk
ripple current. Whenever a high current peak is detected,
SC4612 would first block the driving of the high side and
low side MOSFET, and then discharge the soft-start
capacitor. Discharge rate of the SS capacitor is 1/25 of
the charge rate.
Under Voltage Lock Out
Under Voltage Lock Out (UVLO) circuitry senses the VDD
through a voltage divider. If this signal falls below 4.5V (typi-
cal) with a 400mV hysteresis (typical), the output drivers
are disabled . During the thermal shutdown, the output
drivers are disabled.
12
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
Applications Information (Cont.)
Below are examples of calculating the OCP trip voltages.
Low Side R
DS_ON
Current Limit
1. Ra, Rb - Not installed:
2
R
Vphase
mV
100
3
R
mV
100
V
75
.
2
-
=
-
solving for: V
PHASE
= -100mV, therefore the circuit will trip @ R
DS_ON
x I
LOAD
= 100mV
2. To lower trip voltage - install Rb. For example: Rb = 8k
)
1
R
Rb
(
||
2
R
Vphase
mV
100
3
R
mV
100
V
75
.
2
+
-
=
-
solving for: V
PHASE
= -20mV, obviously more sensitive! R
DS_ON
x I
LOAD
= 20mV
3. To increase trip voltage - install Ra. For example: Ra = 800k; V
DRIVE
= 7.8V typ.
2
R
Vphase
mV
100
1
R
Ra
Vdrive
3
R
mV
100
V
75
.
2
-
=
+
+
-
solving for: V
PHASE
= -200mV. Current limit has doubled compared to original conditions.
NOTE! Allow for tempco and R
DS_ON
variation of the MOSFET - see "overcurrent protection" information on page 11 in the
datasheet.
PHASE pin
2.75V
OCP
SC4612
R5
10k
R1
2k
Ra
Rb
R4
260k
R3
130k
R2
10k
C2
5pF
C1
2pF
ILIM pin
DRV pin
COMP
+100mV
L
R
load
Vin
Iload@Toff
13
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
where,
V
IN
Input voltage
R
L
Load resistance
L Output inductance
C Output capacitance
ESR
C
Output capacitor ESR
V
S
Peak to peak ramp voltage
The classical Type III compensation network can be built
around the error amplifier as shown below:
R3
C3
R2
R1
C1
Vref
C2
-
+
Figure 1. Voltage mode buck converter compensation
network
The transfer function of the compensation network is as
follows:
)
s
1
)(
s
1
(
)
s
1
)(
s
1
(
s
)
s
(
G
2
P
1
P
2
Z
1
Z
I
COMP
+
+
+
+
=
where,
Cout
Lout
1
,
C
)
R
R
(
1
,
C
R
1
o
2
3
1
2
Z
1
2
1
Z
=
+
=
=
3
1
3
1
2
2
P
2
3
1
P
3
1
1
I
C
C
C
C
R
1
,
C
R
1
,
)
C
C
(
R
1
+
=
=
+
=
Applications Information (Cont.)
Gate Drive/Control
The SC4612 also provides integrated high current gate
drives for fast switching of large MOSFETs. The high side
and low side MOSFET gates could be switched with a peak
gate current of 1.7A. The higher gate current will reduce
switching losses of the larger MOSFETs.
The low side gate drives are supplied directly from the DRV.
The high side gate drives could be provided with the clas-
sical bootstrapping technique from DRV.
Cross conduction prevention circuitry ensures a non over-
lapping (30ns typical) gate drive between the top and bot-
tom MOSFETs. This prevents shoot through losses which
provides higher efficiency. Typical total minimum off time
for the SC4612 is about 30ns which will cause the maxi-
mum duty cycle at higher frequencies to be limited to lower
than 100%.
OVERVOLTAGE PROTECTION
If the FB pin ever exceeds 600mV, the top side driver is
latched OFF, and the low side driver is latched ON. This
mode can only be reset by power supply cycling.
ERROR AMPLIFIER DESIGN
The SC4612 is a voltage mode buck controller that utilizes
an externally compensated high bandwidth error amplifier
to regulate output voltage. The power stage of the
synchronous rectified buck converter control-to-output
transfer function is as shown below:
+
+
+
=
LC
2
s
L
R
L
s
1
C
C
sESR
1
S
V
IN
V
)
s
(
VD
G
14
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
The design guidelines are as following:
1. Set the loop gain crossover frequency w
C
for given
switching frequency.
2. Place an integrator at the origin to increase DC and low
frequency gains.
3. Select w
Z1
and w
Z2
such that they are placed near w
O
to
dampen peaking; the loop gain should cross 0dB at a rate
of -20dB/dec.
4. Cancel w
ESR
with compensation pole w
P1
(w
P1
= w
ESR
).
5. Place a high frequency compensation pole w
P2
at half
the switching frequency to get the maximum attenuation
of the switching ripple and the high frequency noise with
adequate phase lag at w
C
.
Application Information (Cont.)
0dB
Gd
T
Z1
Z2
p1
p2
c
ESR
o
Loop gain T(s)
Figure 2. Simplified asymptotic diagram of buck power
stage and its compensated loop gain.
Table 1
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
0
100
200
300
400
500
600
700
800
900
1000 1100 1200
Frequency, (kHz)
Co
s
c
,
(
p
F
)
Switching Frequency, F
SW
vs. C
OSC
.
15
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
PCB LAYOUT GUIDELINES
Careful attention to layout is necessary for successful
implementation of the SC4612 PWM controller. High
switching currents are present in the application and their
effect on ground plane voltage differentials must be
understood and minimized.
1) The high power section of the circuit should be laid out
first. A ground plane should be used. The number and
position of ground plane interruptions should not
unnecessarily compromise ground plane integrity. Isolated
or semi-isolated areas of the ground plane may be
deliberately introduced to constrain ground currents to
particular areas; for example, the input capacitor and
bottom FET ground.
2) The loop formed by the Input Capacitor(s) (Cin), the Top
FET (M1), and the Bottom FET (M2) must be kept as small
as possible. This loop contains all the high current, fast
transition switching. Connections should be as wide and
as short as possible to minimize loop inductance.
Minimizing this loop area will a) reduce EMI, b) lower ground
injection currents, resulting in electrically "cleaner" grounds
for the rest of the system and c) minimize source ringing,
resulting in more reliable gate switching signals.
3) The connection between the junction of M1, M2 and
the output inductor should be a wide trace or copper region.
It should be as short as practical. Since this connection
has fast voltage transitions, keeping this connection short
will minimize EMI. Also keep the Phase connection to the
IC short. Top FET gate charge currents flow in this trace.
4) The Output Capacitor(s) (Cout) should be located as
close to the load as possible. Fast transient load currents
are supplied by Cout only, and therefore, connections
between Cout and the load must be short, wide copper
areas to minimize inductance and resistance.
5) The SC4612 is best placed over a quiet ground plane
area. Avoid pulse currents in the Cin, M1, M2 loop flowing
in this area. GND should be returned to the ground plane
close to the package and close to the ground side of (one
of) the output capacitor(s). If this is not possible, the GND
pin may be connected to the ground path between the
Output Capacitor(s) and the Cin, M1, M2 loop. Under no
circumstances should GND be returned to a ground inside
the Cin, M1, M2 loop.
6) Allow adequate heat sinking area for the power
components. If multiple layers will be used, provide
sufficent vias for heat ransfer
Application Information (Cont.)
Voltage and current waveforms of buck power stage .
Vout
VIN
+
+
Ids (Top Fet)
Ids (Bottom Fet)
I (Input Capacitor)
Vphase
I (Inductor)
Vout
I (Output Capacitor)
16
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
COMPONENT SELECTION:
SWITCHING SECTION
OUTPUT CAPACITORS - Selection begins with the most
critical component. Because of fast transient load current
requirements in modern microprocessor core supplies, the
output capacitors must supply all transient load current
requirements until the current in the output inductor ramps
up to the new level. Output capacitor ESR is therefore one
of the most important criteria. The maximum ESR can be
simply calculated from:
step
current
Transient
I
excursion
voltage
transient
Maximum
V
Where
I
V
R
t
t
t
t
ESR
=
=
For example, to meet a 100mV transient limit with a 10A
load step, the output capacitor ESR must be less than
10m
. To meet this kind of ESR level, there are three
available capacitor technologies.
y
g
o
l
o
n
h
c
e
T
h
c
a
E
r
o
ti
c
a
p
a
C
y
t
Q
.
d
q
R
l
a
t
o
T
C
)
F
u
(
R
S
E
m
(
)
C
)
F
u
(
R
S
E
m
(
)
m
u
l
a
t
n
a
T
R
S
E
w
o
L
0
3
3
0
6
6
0
0
0
2
0
1
N
O
C
-
S
O
0
3
3
5
2
3
0
9
9
3
.
8
m
u
n
i
m
u
l
A
R
S
E
w
o
L
0
0
5
1
4
4
5
0
0
5
7
8
.
8
The choice of which to use is simply a cost/performance
issue, with low ESR Aluminum being the cheapest, but
taking up the most space.
INDUCTOR - Having decided on a suitable type and value
of output capacitor, the maximum allowable value of
inductor can be calculated. Too large an inductor will
produce a slow current ramp rate and will cause the output
capacitor to supply more of the transient load current for
longer - leading to an output voltage sag below the ESR
excursion calculated above.
The maximum inductor value may be calculated from:
(
)
O
IN
t
ESR
V
V
I
C
R
L
-
The calculated maximum inductor value assumes 100%
duty cycle, so some allowance must be made. Choosing
an inductor value of 50 to 75% of the calculated maximum
will guarantee that the inductor current will ramp fast
enough to reduce the voltage dropped across the ESR at a
faster rate than the capacitor sags, hence ensuring a good
recovery from transient with no additional excursions. We
must also be concerned with ripple current in the output
inductor and a general rule of thumb has been to allow
10% of maximum output current as ripple current. Note
that most of the output voltage ripple is produced by the
inductor ripple current flowing in the output capacitor ESR.
Ripple current can be calculated from:
OSC
IN
L
f
L
4
V
I
RIPPLE
=
Ripple current allowance will define the minimum permitted
inductor value.
POWER FETS - The FETs are chosen based on several
criteria with probably the most important being power
dissipation and power handling capability.
TOP FET - The power dissipation in the top FET is a
combination of conduction losses, switching losses and
bottom FET body diode recovery losses.
a) Conduction losses are simply calculated as:
IN
O
)
on
(
DS
2
O
COND
V
V
cycle
duty
=
D
where
D
R
I
P
=
b) Switching losses can be estimated by assuming a
switching time, If we assume 100ns then:
SW
IN
O
SW
T
ns
100
V
I
P
=
or more generally,
2
f
)
t
t
(
V
I
P
OSC
f
r
IN
O
SW
+
=
c) Body diode recovery losses are more difficult to estimate,
but to a first approximation, it is reasonable to assume
Application Information (Cont.)
17
2005 Semtech Corp.
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SC4612
POWER MANAGEMENT
that the stored charge on the bottom FET body diode will
be moved through the top FET as it starts to turn on. The
resulting power dissipation in the top FET will be:
OSC
IN
RR
RR
f
V
Q
P
=
To a first order approximation, it is convenient to only
consider conduction losses to determine FET suitability.
For a 5V in, 2.8V out at 14.2A requirement, typical FET
losses would be:
e
p
y
T
T
E
F
R
)
n
o
(
S
D
m
(
)
)
W
(
D
P
e
g
a
k
c
a
P
S
2
0
4
3
L
R
I
5
1
9
6
.
1
D
2
K
A
P
3
0
2
2
L
R
I
5
.
0
1
9
1
.
1
D
2
K
A
P
0
1
4
4
i
S
0
2
6
2
.
2
8
-
O
S
Using 1.5X Room temp R
DS(ON)
to allow for temperature rise.
BOTTOM FET - Bottom FET losses are almost entirely due
to conduction. The body diode is forced into conduction at
the beginning and end of the bottom switch conduction
period, so when the FET turns on and off, there is very little
voltage across it resulting in very low switching losses.
Conduction losses for the FET can be determined by:
)
D
1
(
R
I
P
)
on
(
DS
2
O
COND
-
=
For the example above:
e
p
y
T
T
E
F
R
)
n
o
(
S
D
m
(
)
P
D
)
W
(
e
g
a
k
c
a
P
S
2
0
4
3
L
R
I
5
1
3
3
.
1
D
2
K
A
P
3
0
2
2
L
R
I
5
.
0
1
3
9
.
0
D
2
K
A
P
0
1
4
4
i
S
0
2
7
7
.
1
8
-
O
S
Each of the package types has a characteristic thermal
impedance, for the TO-220 package, thermal impedance
is mostly determined by the heatsink used. For the surface
mount packages on double sided FR4, 2 oz printed circuit
board material, thermal impedances of 40
o
C/W for the
D
2
PAK and 80
o
C/W for the SO-8 are readily achievable.
The corresponding temperature rise is detailed below:
(
e
s
i
r
e
r
u
t
a
r
e
p
m
e
T
0
)
C
e
p
y
T
T
E
F
T
E
F
p
o
T
T
E
F
m
o
t
t
o
B
S
2
0
4
3
L
R
I
6
.
7
6
2
.
3
5
3
0
2
2
L
R
I
6
.
7
4
2
.
7
3
0
1
4
4
i
S
8
.
0
8
1
6
.
1
4
1
It is apparent that single SO-8 Si4410 are not adequate for
this application, By using parallel pairs in each position,
power dissipation will be approximately halved and
temperature rise reduced by a factor of 4.
INPUT CAPACITORS - Since the RMS ripple current in the
input capacitors may be as high as 50% of the output
current, suitable capacitors must be chosen accordingly.
Also, during fast load transients, there may be restrictions
on input di/dt. These restrictions require useable energy
storage within the converter circuitry, either as extra output
capacitance or, more usually, additional input capacitors.
Choosing low ESR input capacitors will help maximize ripple
rating for a given size.
Application Information (Cont.)
18
2005 Semtech Corp.
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SC4612
POWER MANAGEMENT
Application Information (Cont.)
Application Circuit 1: Vin = 36V; Vout = 5V @ 20A, Fsw = 250kHz.
Efficiency:
Q1
HAT2172H
Q2
HAT2172H
L1
4.7uH@22A
C10
0.1
C12A
330/6.3V
+
_
+
_
Vin=36V
Vout=5@20A
R3
10k
R5
5.36k
C6
1/16V
R1
560k
C2
430p
C9
10/50V_cer
C3
0.1
R6
48.7k
C4
9.1n
D 1
MBR0540
C8
2.2/10V
C5
1.3n
ILIM
1
PHASE
12
OSC
2
SS/EN
3
FB
5
VDD
6
GND
7
DL
8
DRV
9
BST
10
DH
11
EAO
4
U 1
SC4612MLP
R4*
1.5k
R7
910
C7
1.3n
C13B
10/6.3V_cer
C12B
330/6.3V
Fsw=250kHz
C13A
330/6.3V
C14B
330/50V_AL
C14A
330/50V_AL
R4*: if Vin > 30V, then R4 prevents VDD from exceeding 28Vmax
SC4612: 36Vin, 5Vout @ 20A
80%
82%
84%
86%
88%
90%
92%
94%
96%
98%
100%
0
2
4
6
8
10
12
14
16
18
20
22
Current, (A)
E
f
fi
ci
e
n
cy
19
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
Application Information (Cont.)
Application Circuit 2: Vin = 24V; Vout = 3.3V @ 20A, Fsw = 470kHz.
Efficiency:
Q1
HAT2168H
Q2
HAT2165H
L1
1.5uH@22A
C10
0.1
C12A
180/4V_PosCap
+
_
+
_
Vin=24V
Vout=3.3@20A
R3
10k
R5
6.98k
C6
1/16V
R8
0
R9
0
R1
560k
C2
200p
C9
22/25V_cer
C3
0.1
R6
39.2k
C4
3.9n
D1
MBR0540
C8
2.2/10V
C5
300p
ILIM
1
PHASE
12
OSC
2
SS/EN
3
FB
5
VDD
6
GND
7
DL
8
DRV
9
BST
10
DH
11
EAO
4
U1
SC4612MLP
R4opt
R7
887
C7
750p
C13B
10/6.3V_cer
C12B
180/4V
Fsw=500kHz
C13A
180/4V
C14B
470/35V_AL
C14A
470/35V_AL
SC4612: 24Vin, 3.3Vout @ 20A
80%
82%
84%
86%
88%
90%
92%
94%
96%
98%
100%
0
2
4
6
8
10
12
14
16
18
20
22
Current, (A)
E
f
fi
ci
e
n
cy
20
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
Application Information (Cont.)
Efficiency:
Application Circuit 3: Vin = 12V; Vout = 2.5V @ 12A, Fsw = 770kHz
Q1
HAT2168H
Q2
HAT2165H
L1
1.4uH@14A
C10
0.1
C12A
220/4V _PosCap
+
_
+
_
Vin=12V
Vout=2.5@12A
R3
10k
R5
2.74k
C6
1/16V
R8
0
R9
0
R1
825k
C2
120p
C9
22/16V _cer
C3
0.1
R6
11.0k
C4
3.3n
D1
SD107WS
C8
2.2/10V
C5
300p
ILIM
1
PHASE
12
OSC
2
SS/EN
3
FB
5
VDD
6
GND
7
DL
8
DRV
9
BST
10
DH
11
EAO
4
U1
SC4612MLP
R4opt
20
R7
178
C7
2.2n
C13B
10/6.3V_cer
C12B
220/4V
Fsw=800kHz
C13A
N/A
C14B
47/16V _AL
C14A
47/16V_AL
SC4612: 12Vin, 2.5Vout @ 12A
80%
82%
84%
86%
88%
90%
92%
94%
96%
98%
100%
0
1
2
3
4
5
6
7
8
9
10
11
12
Current, (A)
E
ffi
ci
e
n
c
y
21
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
Application Information (Cont.)
Efficiency:
Application Circuit 4: Vin = 5V; Vout = 1.35V @ 12A, Fsw = 960kHz.
Q1
HAT2168H
Q2
HAT2168H
L1
0.47uH@15A
C10
0.1
C11
100/6.3_1210_cer
+
_
+
_
Vin=5V
Vout=1.35@12A
R3
10k
R5
8.87k
C6
1
C2
82p
C9
100/6.3_1210_cer
C3
0.1
R6
13.3k
C4
1n
D1
SD107WS
C8
2.2
C5
33p
ILIM
1
PHASE
12
OSC
2
SS/EN
3
FB
5
VDD
6
GND
7
DL
8
DRV
9
BST
10
DH
11
EAO
4
U1
SC4612MLP
R7
649
C7
510p
R2
825k
Fsw=1MHz
SC4612: 5Vin, 1.35Vout @ 12A
80%
82%
84%
86%
88%
90%
92%
94%
96%
98%
100%
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Current, (A)
E
f
fi
ci
e
n
cy
22
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
Application Information (Cont.)
Evaluation Board 1:
Top layer and components view
Bottom Layer:
23
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
Application Information (Cont.)
Evaluation Board 2 (actual size):
Top layer:
Bottom layer:
24
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
Outline Drawing - MLPD - 12
bxN
e
MILLIMETERS
0.50 BSC
.002
.001
0.00
.000
A1
.114
.154
.061
.124
.012
.007
E1
aaa
bbb
N
e
L
A2
D1
D
E
b
.020 BSC
.067
.016
.003
.004
12
.118
(.008)
.130
.157
.010
-
1.55
.071
.020 0.30
.161
.122
.134
-
.012
3.90
2.90
3.15
-
0.18
.031
MIN
DIM
A
MAX
DIMENSIONS
INCHES
.035
NOM
.040 0.80
MIN
0.02 0.05
3.10
4.10
1.80
3.40
0.50
0.30
1.70
0.40
0.10
0.08
12
3.00
(0.20)
3.30
4.00
0.25
-
1.00
MAX
0.90
NOM
A
B
PIN1
INDICATOR
(LASER MARK)
A1
A
aaa C
A2
C
SEATING
PLANE
1 2
N
bbb
C A B
COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
NOTES:
2.
1.
D
E
D1/2
D1
E1/2
E1
LxN
Land Pattern - MLPD - 12
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
NOTES:
1.
DIM
X
Y
H
K
P
C
G
MILLIMETERS
INCHES
(2.90)
.012
.028
.087
.020
.138
.067
(.114)
0.30
0.70
1.70
0.50
3.50
2.20
DIMENSIONS
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
3.60
.142
Z
25
2005 Semtech Corp.
www.semtech.com
SC4612
POWER MANAGEMENT
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
Contact Information
Outline Drawing - SOIC - 14
SEE DETAIL
DETAIL
A
A
.050 BSC
.236 BSC
14
.010
.150
.337
.154
.341
.012
-
14
0.25
1.27 BSC
6.00 BSC
3.90
8.65
-
.157
.344
3.80
8.55
.020 0.31
4.00
8.75
0.51
bxN
2X N/2 TIPS
SEATING
aaa C
E/2
2X
3
A
D
A1
E1
bbb
C A-B D
ccc C
A2
(.041)
.004
.008
-
.028
-
-
-
-
0
.016
.007
.049
.004
.053
8
0
0.20
0.10
-
8
0.40
0.17
1.25
0.10
.041
.010
.069
.065
.010
1.35
(1.04)
0.72
-
1.04
0.25
-
-
-
1.75
1.65
0.25
0.25
-
.010
.020
0.50
-
c
L
(L1)
01
0.25
GAGE
PLANE
h
h
PLANE
N
1
2
A
e
D
C
H
B
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
-B-
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
DATUMS AND TO BE DETERMINED AT DATUM PLANE
NOTES:
1.
2.
-A-
-H-
SIDE VIEW
REFERENCE JEDEC STD MS-012, VARIATION AB.
4.
L1
ccc
aaa
bbb
01
N
DIM
E1
D
A1
A2
DIMENSIONS
MILLIMETERS
MIN
e
L
h
E
b
c
INCHES
NOM
MIN
A
MAX
MAX
NOM
E
Z
G
Y
P
(C)
X
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
NOTES:
1.
REFERENCE IPC-SM-782A, RLP NO. 302A.
2.
.291
.087
.024
.118
(.205)
INCHES
DIMENSIONS
Z
P
Y
X
DIM
C
G
MILLIMETERS
.050
(5.20)
7.40
2.20
0.60
3.00
1.27
Land Pattern - SOIC - 14
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