1
www.semtech.com
SC485
Dual Synchronous Buck For
Dynamic Voltage Transitioning
POWER MANAGEMENT
Revision: February 11, 2005
Description
Features
Applications
Typical Application Circuit
The SC485 is a dual output constant on-time
synchronous-buck PWM controller intended for use in
notebook computers and graphics cards. Features
include high efficiency and a fast dynamic response with
no minimum on-time. The excellent transient response
means that SC485 based solutions will require less
output capacitance than competing fixed frequency
converters. The two outputs are designed according to
their target role. Output 1 is designed to power IO or
other static rails, whereas output 2 is designed to power
rails requiring dynamic voltage transitioning. Output 2 has
a tighter DC accuracy of 0.85% combined with a higher
OVP threshold of 20% to simplify the design and reduce
component count.
Each output voltage can be independently adjusted from
0.5V to VCCA. Two frequency setting resistors set the
on-time for each buck controller. The frequency can thus
be tailored to minimize crosstalk. The integrated gate
drivers feature adaptive shoot-through protection and
soft switching, requiring no gate resistors for the top
MOSFET. Additional features include cycle-by-cycle current
limit, digital soft-start, over-voltage and under-voltage
protection, and a Power Good output for each controller.
Graphics cards
Embedded graphics processors
High performance processors
Output 1 has 1% DC accuracy and 10% OVP
Output 2 has 0.85% DC accuracy and 20% OVP for
simple dynamic voltage transitioning
Constant on-time for fast dynamic response
Programmable VOUT range = 0.5 VCCA
VBAT Range = 1.8V 25V
DC current sense using low-side RDS(ON) sensing
or sense resistor
Resistor programmable on-time
Cycle-by-cycle current limit
Digital soft-start
Separate ENABLE & PSAVE for each switcher
Over-voltage/Under-voltage fault protection
10uA typical shutdown current
Low quiescent power dissipation
Two separate power good indicators
Integrated gate drivers with soft switching - no gate
resistors required
28 pin TSSOP (lead free)
C10
1uF
L2
R4
5VSUS
R1
RTON1
R2
10R
VBAT
VSSA1
+
C3
R9
10R
PGOOD
C5
1nF
VOUT1
R12
L1
+
C9
C7 0.1uF
Q3
R5
VSSA1
R11
Q1
R3
VBAT
VOUT1
R8
RTON2
VSSA2
C12
1uF
VOUT2
5VSUS
C1 0.1uF
C8
10uF
VSSA2
R7
Q2
VBAT
C6
1uF
5VSUS
Q4
PGOOD
VOUT2
C11
1nF
C2
10uF
R14
VBAT
R6 0R
D1
R10
U1
SC485
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
EN/PSV1
TON1
VOUT1
VCCA1
FB1
PGD1
VSSA1
PGND1
DL1
VDDP1
ILIM1
LX1
DH1
BST1
EN/PSV2
TON2
VOUT2
VCCA2
FB2
PGD2
VSSA2
PGND2
DL2
VDDP2
ILIM2
LX2
DH2
BST2
D2
5VSUS
R13 0R
C4
1uF
2
2005 Semtech Corp.
www.semtech.com
SC485
POWER MANAGEMENT
Absolute Maximum Ratings
(3)
Electrical Characteristics
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A
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may
affect device reliability.
3
2005 Semtech Corp.
www.semtech.com
SC485
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Test Conditions: V
BAT
= 15V, EN/PSV1=EN/PSV2 = 5V, VCCA1 = VDDP1 = VCCA2=VDDP2=5.0V, V
OUT1
= 1.25V, R
TON1
= 1M, VOUT2 = 1.25V, R
TON2
= 1M
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4
2005 Semtech Corp.
www.semtech.com
SC485
POWER MANAGEMENT
Notes:
(1) When the inductor is in continuous and discontinuous conduction mode, the output voltage will have a DC
regulation level higher than the error-comparator threshold by 50% of the ripple voltage.
(2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the
low-side MOSFET. These values guaranteed by the ILIM Source Current and Current Comparator Offset tests.
(3) This device is ESD sensitive. Use of standard ESD handling precautions is required.
(4) Guaranteed by design. See Shoot-Through Delay Timing Diagram on Page 6.
(5) Measured in accordance with JESD51-1, JESD51-2 and JESD51-7.
(6) clks = switching cycles
Electrical Characteristics (Cont.)
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5
2005 Semtech Corp.
www.semtech.com
SC485
POWER MANAGEMENT
Pin Configuration
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Pin Descriptions
Notes:
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6
2005 Semtech Corp.
www.semtech.com
SC485
POWER MANAGEMENT
Pin Descriptions (Cont.)
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Shoot-Through Delay Timing Diagram
tplhDL
tplhDH
LX
DL
DL
DH
7
2005 Semtech Corp.
www.semtech.com
SC485
POWER MANAGEMENT
Figure 1
Block Diagram
X3
OV
TON2 (9)
REF + 20%
TON1 (23)
MONITOR
PWM
PWM
+
-
+
-
TOFF
EN/SPV1 (22)
FB2 (12)
1.5V REF
VCCA1 (25)
TON
VSSA2 (14)
OFF
ISENSE
BST1 (7)
LOGIC
REF - 30%
UV
HI
VOUT2 (10)
OT
DH1 (6)
ILIM2 (18)
POR / SS
LX1 (5)
EN/SPV2 (8)
ON
LO
ISENSE
ILIM1 (4)
OFF
REF - 30%
OC
VDDP1 (3)
LO
PGD2 (13)
UV
ON
VDDP2 (17)
DL1 (2)
ZERO I
DH2 (20)
VCCA2 (11)
CONTROL
PGND1 (1)
CONTROL
PGND2 (15)
LOGIC
MONITOR
POR / SS
VSSA1 (28)
FAULT
REF + 10%
TOFF
LX2 (19)
OC
OT
OV
ZERO I
DL2 (16)
FAULT
1.5V REF
PGD1 (27)
TON
X3
FB1 (26)
REF - 10%
HI
REF - 10%
VOUT1 (24)
BST2 (21)
EN/PSV1
EN/PSV2
8
2005 Semtech Corp.
www.semtech.com
SC485
POWER MANAGEMENT
+5V Bias Supplies
The SC485 requires an external +5V bias supply in
addition to the battery. If stand-alone capability is
required, the +5V supply can be generated with an
external linear regulator such as the Semtech LP2951.
.
Pseudo-fixed Frequency Constant On-Time PWM
Controller
The PWM control architecture consists of a constant on-
time, pseudo fixed frequency PWM controller (see Figure
1, SC485 Block Diagram). The output ripple voltage
developed across the output filter capacitor's ESR
provides the PWM ramp signal eliminating the need for a
current sense resistor. The high-side switch on-time is
determined by a one-shot whose period is directly
proportional to output voltage and inversely proportional
to input voltage. A second one-shot sets the minimum
off-time which is typically 400ns.
On-Time One-Shot (t
ON
)
The on-time one-shot comparator has two inputs. One
input looks at the output voltage, while the other input
samples the input voltage and converts it to a current.
zero volts to VOUT, thereby making the on-time of the
high-side switch directly proportional to output voltage
and inversely proportional to input voltage. This
implementation results in a nearly constant switching
frequency without the need for a clock generator.
For VOUT < 3.3V:
ns
50
V
V
)
10
x
37
R
(
10
x
3
.
3
t
BAT
OUT
3
TON
12
ON
+
+
=
-
For 3.3V
VOUT
5V:
ns
50
V
V
)
10
x
37
R
(
10
x
3
.
3
85
.
0
t
BAT
OUT
3
TON
12
ON
+
+
=
-
R
TON
is a resistor connected from the input supply (VBAT)
to the TON
pin. Due to the high impedance of this
resistor, the TON pin should always be bypassed to VSSA
using a 1nF ceramic capacitor.
Enable & Psave
The EN/PSV pin enables the supply. When EN/PSV is
tied to VCCA the controller is enabled and power save
will also be enabled. When the EN/PSV pin is tri-stated,
an internal pull-up will activate the controller and power
save will be disabled. If PSAVE is enabled, the SC485
PSAVE comparator will look for the inductor current to
cross zero on eight consecutive switching cycles by
comparing the phase node (LX) to PGND. Once observed,
the controller will enter power save and turn off the low
side MOSFET when the current crosses zero. To improve
light-load efficiency and add hysteresis, the on-time is
increased by 50% in power save. The efficiency
improvement at light-loads more than offsets the
disadvantage of slightly higher output ripple. If the
inductor current does not cross zero on any switching
cycle, the controller will immediately exit power save. Since
the controller counts zero crossings, the converter can
sink current as long as the current does not cross zero
on eight consecutive cycles. This allows the output
voltage to recover quickly in response to negative load
steps even when psave is enabled.
Applications Information
To avoid interference between outputs, each controller
has its own ground reference, VSSA, which should be
tied by a single trace to PGND at the negative terminal of
that controller's output capacitor (see Layout Guidelines).
All external components referenced to VSSA in the
schematic should be connected to the appropriate VSSA
trace. The supply decoupling capacitor for controller 1
should be tied between VCCA1 and VSSA1. Likewise, the
supply decoupling capacitor for controller 2 should be
tied between VCCA2 and VSSA2. A 10
resistor should
be used to decouple each VCCA supply from the main
VDDP supplies. PGND can then be a separate plane which
is not used for routing traces. All PGND connections are
connected directly to the ground plane with special
attention given to avoiding indirect connections which
may create ground loops. As mentioned above, VSSA1
and VSSA2 must be connected to the PGND plane at
the negative terminal of their respective output
capacitors only. The VDDP1 and VDDP2 inputs provide
power to the upper and lower gate drivers. A decoupling
capacitor for each supply is required. No series resistor
between VDDP and 5V is required. See layout guidelines
for more details.
This input voltage-proportional current is used to charge
an internal on-time capacitor. The on-time is the time
required for the voltage on this capacitor to charge from
9
2005 Semtech Corp.
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SC485
POWER MANAGEMENT
Output Voltage Selection
The output voltage (OUT2 shown) is set by the feedback
resistors R9 & R13 of Figure 2 below. The internal
reference is 1.5V, so the voltage at the feedback pin is
multiplied by three to match the 1.5V reference.
Therefore the output can be set to a minimum of 0.5V.
The equation for setting the output voltage is:
5
.
0
13
R
9
R
1
V
OUT
+
=
0402
0402
C15
56p
0402
VOUT2
VSSA2
R9
20k0
R13
20k0
VOUT
EN/PSV2
8
TON2
9
VOUT2
10
VCCA2
11
FB2
12
PGD2
13
VSSA2
14
PGND2
15
DL2
16
VDDP2
17
ILIM2
18
LX2
19
DH2
20
BST2
21
U1
SC485 OUT2
Figure 2: Setting The Output Voltage
Current Limit Circuit
Current limiting of the SC485 can be accomplished in
two ways. The on-state resistance of the low-side MOSFET
can be used as the current sensing element or sense
resistors in series with the low-side source can be used
if greater accuracy is desired. R
DS(ON)
sensing is more
efficient and less expensive. In both cases, the R
ILIM
resistor between the ILIM pin and LX pin set the over
current threshold. This resistor R
ILIM
is connected to a
10
A current source within the SC485 which is turned
on when the low side MOSFET turns on. When the
voltage drop across the sense resistor or low side
MOSFET equals the voltage across the RILIM resistor,
positive current limit will activate. The high side MOSFET
will not be turned on until the voltage drop across the
sense element (resistor or MOSFET) falls below the
voltage across the R
ILIM
resistor. In an extreme over-
current situation, the top MOSFET will never turn back
on and eventually the part will latch off due to output
undervoltage (see Output Undervoltage Protection).
The current sensing circuit actually regulates the
inductor valley current (see Figure 3). This means that if
the current limit is set to 10A, the peak current through
the inductor would be 10A plus the peak ripple current,
and the average current through the inductor would be
10A plus 1/2 the peak-to-peak ripple current. The
equations for setting the valley current and calculating
the average current through the inductor are shown
below:
I
LIMIT
I
LOAD
I
PEAK
I
N
DU
CT
O
R
CUR
R
E
N
T
TIME
Valley Current-Limit Threshold Point
Figure 3: Valley Current Limiting
The equation for the current limit threshold is as follows:
A
R
R
10e
I
SENSE
ILIM
6
-
LIMIT
=
Where (referring to Figure 8 on Page 17) R
ILIM
is R10 and
R
SENSE
is the R
DS(ON)
of Q4.
For resistor sensing, a sense resistor is placed between
the source of Q4 and PGND. The current through the
source sense resistor develops a voltage that opposes
the voltage developed across R
ILIM
. When the voltage
developed across the R
SENSE
resistor reaches the voltage
drop across R
ILIM
, a positive over-current exists and the
high side MOSFET will not be allowed to turn on. When
using an external sense resistor R
SENSE
is the resistance
of the sense resistor.
The current limit circuitry also protects against negative
over-current (i.e. when the current is flowing from the
load to PGND through the inductor and bottom MOSFET).
In this case, when the bottom MOSFET is turned on, the
phase node, LX, will be higher than PGND initially. The
SC485 monitors the voltage at LX, and if it is greater
10
2005 Semtech Corp.
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SC485
POWER MANAGEMENT
than a set threshold voltage of 125mV (nom.) the
bottom MOSFET is turned off. The device then waits for
approximately 2.5s and then DL goes high for 300ns
(typ.) once more to sense the current. This repeats until
either the over-current condition goes away or the part
latches off due to output overvoltage (see Output
Overvoltage Protection).
Power Good Output
The power good output is an open-drain output and
requires a pull-up resistor. When the output voltage is
10% above (OUT1, 20% for OUT2) or 10% below its set
voltage, PGD gets pulled low. It is held low until the
output voltage returns to within these tolerances once
more. PGD is also held low during start-up and will not be
allowed to transition high until soft start is over (440
switching cycles) and the output reaches 90% of its set
voltage. There is a 5s delay built into the PGD circuitry
to prevent false transitions.
Output Overvoltage Protection
When the output exceeds 10% (OUT1, 20% for OUT2) of
its set voltage the low-side MOSFET is latched on. It stays
latched on and the controller is latched off until reset
(see below). There is a 5s delay built into the OV
protection circuit to prevent false transitions.
Output Undervoltage Protection
When the output is 30% below its set voltage the output
is latched in a tri-stated condition. It stays latched and
the controller is latched off until reset (see below). There
is a 5s delay built into the UV protection circuit to
prevent false transitions. Note: to reset from any fault,
VCCA or EN/PSV must be toggled.
POR, UVLO and Softstart
An internal power-on reset (POR) occurs when VCCA
exceeds 3V, starting up the internal biasing. VCCA
undervoltage lockout (UVLO) circuitry inhibits the
controller until VCCA rises above 4.2V. At this time the
UVLO circuitry resets the fault latch and soft start timer,
and allows switching to occur if the device is enabled.
Switching always starts with DL to charge up the BST
capacitor. With the softstart circuit (automatically)
enabled, it will progressively limit the output current (by
limiting the current out of the ILIM pin) over a
predetermined time period of 440 switching cycles.
The ramp occurs in four steps:
1) 110 cycles at 25% ILIM with double minimum off-time
2) 110 cycles at 50% ILIM with normal minimum off-time
3) 110 cycles at 75% ILIM with normal minimum off-time
4) 110 cycles at 100% ILIM with normal minimum
off-time. At this point the output undervoltage and power
good circuitry is enabled.
There is 100mV of hysteresis built into the UVLO circuit
and when VCCA
falls to 4.1V (nom.) the output drivers
are shut down and tristated.
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving
moderate-sized high-side, and larger low-side power
MOSFETs. An adaptive dead-time circuit monitors the DL
output and prevents the high-side MOSFET from turning
on until DL is fully off (below ~1V). Semtech's
SmartDriverTM FET drive first pulls DH high with a pull-up
resistance of 10
(typ.) until LX = 1.5V (typ.). At this
point, an additional pull-up device is activated, reducing
the resistance to 2
(typ.). This negates the need for an
external gate or boost resistor. The adaptive dead-time
circuit also monitors the phase node, LX, to determine
the state of the high side MOSFET, and prevents the low-
side MOSFET from turning on until DH is fully off (LX
below ~1V). Be sure to have low resistance and low
inductance between the DH and DL outputs to the gate
of each MOSFET.
Dropout Performance
The output voltage adjust range for continuous-
conduction operation is limited by the fixed 550ns
(maximum) minimum off-time one-shot. For best dropout
performance, use the slowest on-time setting of 200kHz.
When working with low input voltages, the duty-factor
limit must be calculated using worst-case values for on
and off times. The IC duty-factor limitation is given by:
)
MAX
(
OFF
t
)
MIN
(
ON
t
)
MIN
(
ON
t
DUTY
+
=
Be sure to include inductor resistance and MOSFET on-
state voltage drops when performing worst-case dropout
duty-factor calculations.
11
2005 Semtech Corp.
www.semtech.com
SC485
POWER MANAGEMENT
485 System DC Accuracy
Two IC parameters affect system DC accuracy, the error
comparator threshold voltage variation and the switching
frequency variation with line and load. The error
comparator threshold does not drift significantly with
supply and temperature. Thus, the error comparator
contributes 1% (OUT1, 0.85% for OUT2) or less to DC
system inaccuracy.
Board components and layout also influence DC
accuracy. The use of 1% feedback resistors contribute
1%. If tighter DC accuracy is required use 0.1% feedback
resistors.
The on pulse in the SC485 is calculated to give a pseudo
fixed frequency. Nevertheless, some frequency variation
with line and load can be expected. This variation changes
the output ripple voltage. Because constant on regulators
regulate to the valley of the output ripple, of the output
ripple appears as a DC regulation error. For example, if
the feedback resistors are chosen to divide down the
output by a factor of five, the valley of the output ripple
will be VOUT. For example: if VOUT is 2.5V and the ripple
is 50mV with VBAT = 6V, then the measured DC output
will be 2.525V. If the ripple increases to 80mV with VBAT
= 25V, then the measured DC output will be 2.540V.
The output inductor value may change with current. This
will change the output ripple and thus the DC output
voltage. It will not change the frequency.
Switching frequency variation with load can be minimized
by choosing MOSFETs with lower R
DS(ON)
. High R
DS(ON)
MOSFETs will cause the switching frequency to increase
as the load current increases. This will reduce the ripple
and thus the DC output voltage.
Design Procedure
Prior to designing an output and making component
selections, it is necessary to determine the input voltage
range and the output voltage specifications. For purposes
of demonstrating the procedure the output for the
schematic in Figure 8 on Page 17 will be designed.
The maximum input voltage (V
BAT(MAX)
) is determined by
the highest AC adaptor voltage. The minimum input
voltage (V
BAT(MIN)
) is determined by the lowest battery
voltage after accounting for voltage drops due to
connectors, fuses and battery selector switches. For the
purposes of this design example we will use a V
BAT
range
of 8V to 20V and design OUT2. The design for OUT1
employs the same technique.
Four parameters are needed for the output:
1) nominal output voltage, V
OUT
(we will use 1.2V)
2) static (or DC) tolerance, TOL
ST
(we will use +/-4%)
3) transient tolerance, TOL
TR
and size of transient (we will
use +/-8% and 6A for purposes of this demonstration).
4) maximum output current, I
OUT
(we will design for 6A)
Switching frequency determines the trade-off between
size and efficiency. Increased frequency increases the
switching losses in the MOSFETs, since losses are a
function of VIN
2
. Knowing the maximum input voltage and
budget for MOSFET switches usually dictates where the
design ends up. It is recommended that the two outputs
are designed to operate at frequencies approximately
25% apart to avoid any possible interaction. It is also
recommended that the higher frequency output is the
lower output voltage output, since this will tend to have
lower output ripple and tighter specifications. The
default R
tON
values of 1M
and 715k
are suggested
as a starting point, but these are not set in stone. The
first thing to do is to calculate the on-time, t
ON
, at V
BAT(MIN)
and V
BAT(MAX)
, since this depends only upon V
BAT
, V
OUT
and
R
tON
.
For V
OUT
< 3.3V:
(
)
s
10
50
V
V
10
37
R
10
3
.
3
t
9
)
MIN
(
BAT
OUT
3
tON
12
)
MIN
(
VBAT
_
ON
-
-
+
+
=
and
(
)
s
10
50
V
V
10
37
R
10
3
.
3
t
9
)
MAX
(
BAT
OUT
3
tON
12
)
MAX
(
VBAT
_
ON
-
-
+
+
=
From these values of t
ON
we can calculate the nominal
switching frequency as follows:
(
)
Hz
t
V
V
f
)
MIN
(
VBAT
_
ON
)
MIN
(
BAT
OUT
)
MIN
(
VBAT
_
SW
=
and
(
)
Hz
t
V
V
f
)
MAX
(
VBAT
_
ON
)
MAX
(
BAT
OUT
)
MAX
(
VBAT
_
SW
=
t
ON
is generated by a one-shot comparator that samples
V
BAT
via R
tON
, converting this to a current. This current is
used to charge an internal 3.3pF capacitor to V
OUT
. The
12
2005 Semtech Corp.
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SC485
POWER MANAGEMENT
equations above reflect this along with any internal
components or delays that influence t
ON
. For our example
we select R
tON
= 1M
:
t
ON_VBAT(MIN)
= 563ns and t
ON_VBAT(MAX)
= 255ns
f
SW_VBAT(MIN)
= 266kHz and f
SW_VBAT(MAX)
= 235kHz
Now that we know t
ON
we can calculate suitable values
for the inductor. To do this we select an acceptable
inductor ripple current. The calculations below assume
50% of I
OUT
which will give us a starting place.
(
)
(
)
H
I
5
.
0
t
V
V
L
OUT
)
MIN
(
VBAT
_
ON
OUT
)
MIN
(
BAT
)
MIN
(
VBAT
-
=
and
(
)
(
)
H
I
5
.
0
t
V
V
L
OUT
)
MAX
(
VBAT
_
ON
OUT
)
MAX
(
BAT
)
MAX
(
VBAT
-
=
For our example:
L
VBAT(MIN)
= 1.3H and L
VBAT(MAX)
= 1.6H
We will select an inductor value of 2.2H to reduce the
ripple current, which can be calculated as follows:
(
)
P
P
)
MIN
(
VBAT
_
ON
OUT
)
MIN
(
BAT
)
MIN
(
VBAT
_
RIPPLE
A
L
t
V
V
I
-
-
=
and
(
)
P
P
)
MAX
(
VBAT
_
ON
OUT
)
MAX
(
BAT
)
MAX
(
VBAT
_
RIPPLE
A
L
t
V
V
I
-
-
=
For our example:
I
RIPPLE_VBAT(MIN)
= 1.74A
P-P
and I
RIPPLE_VBAT(MAX)
= 2.18A
P-P
From this we can calculate the minimum inductor
current rating for normal operation:
)
MIN
(
)
MAX
(
VBAT
_
RIPPLE
)
MAX
(
OUT
)
MIN
(
INDUCTOR
A
2
I
I
I
+
=
For our example:
I
INDUCTOR(MIN)
= 7.1A
(MIN)
Next we will calculate the maximum output capacitor
equivalent series resistance (ESR). This is determined by
calculating the remaining static and transient tolerance
allowances. Then the maximum ESR is the smaller of the
calculated static ESR (R
ESR_ST(MAX)
) and transient ESR
(R
ESR_TR(MAX)
):
(
)
Ohms
I
2
ERR
ERR
R
)
MAX
(
VBAT
_
RIPPLE
DC
ST
)
MAX
(
ST
_
ESR
-
=
Where ERR
ST
is the static output tolerance and ERR
DC
is
the DC error. The DC error will be 0.85% (1% for OUT1)
plus the tolerance of the feedback resistors, thus 1.85%
(2% for OUT1) total for 1% feedback resistors.
For our example:
ERR
ST
= 48mV and ERR
DC
= 22mV, therefore
R
ESR_ST(MAX)
= 24m
(
)
Ohms
2
I
I
ERR
ERR
R
)
MAX
(
VBAT
_
RIPPLE
OUT
DC
TR
)
MAX
(
TR
_
ESR
+
-
=
Where ERR
TR
is the transient output tolerance. Note that
this calculation assumes that the worst case load
transient is full load. For half of full load, divide the I
OUT
term by 2.
For our example:
ERR
TR
= 96mV and ERR
DC
= 22mV, therefore
R
ESR_TR(MAX)
= 10.4m
for a full 6A load transient
We will select a value of 12.5m
maximum for our
design, which would be achieved by using two 25m
output capacitors in parallel.
13
2005 Semtech Corp.
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SC485
POWER MANAGEMENT
Note that for constant-on converters there is a minimum
ESR requirement for stability which can be calculated as
follows:
SW
OUT
)
MIN
(
ESR
f
C
2
3
R
=
This criteria should be checked once the output
capacitance has been determined.
Now that we know the output ESR we can calculate the
output ripple voltage:
P
P
)
MAX
(
VBAT
_
RIPPLE
ESR
)
MAX
(
VBAT
_
RIPPLE
V
I
R
V
-
=
and
P
P
)
MIN
(
VBAT
_
RIPPLE
ESR
)
MIN
(
VBAT
_
RIPPLE
V
I
R
V
-
=
For our example:
V
RIPPLE_VBAT(MAX)
= 27mV
P-P
and V
RIPPLE_VBAT(MIN)
= 22mV
P-P
Note that in order for the device to regulate in a
controlled manner, the ripple content at the feedback
pin, V
FB
, should be approximately 15mV
P-P
at minimum
V
BAT
, and worst case no smaller than 10mV
P-P
. If
V
RIPPLE_VBAT(MIN)
is less than 15mV
P-P
the above component
values should be revisited in order to improve this. Quite
often a small capacitor, C
TOP
, is required in parallel with
the top feedback resistor, R
TOP
, in order to ensure that
V
FB
is large enough. C
TOP
should not be greater than
100pF. The value of C
TOP
can be calculated as follows,
where R
BOT
is the bottom feedback resistor. Firstly
calculating the value of Z
TOP
required:
(
)
Ohms
015
.
0
V
015
.
0
R
Z
)
MIN
(
VBAT
_
RIPPLE
BOT
TOP
-
=
Secondly calculating the value of C
TOP
required to achieve
this:
F
f
2
R
1
Z
1
C
)
MIN
(
VBAT
_
SW
TOP
TOP
TOP
-
=
For our example we will use R
TOP
= 20.0k
and
R
BOT
= 14.3k
, therefore:
Z
TOP
= 6.45k
and C
TOP
= 63pF
We will select a value of C
TOP
= 56pF. Calculating the
value of V
FB
based upon the selected C
TOP
:
P
P
TOP
)
MIN
(
VBAT
_
SW
TOp
BOT
BOT
)
MIN
(
VBAT
_
RIPPLE
)
MIN
(
VBAT
_
FB
V
C
f
2
R
1
1
R
R
V
V
-
+
+
=
For our example:
V
FB_VBAT(MIN)
= 14.6mV
P-P
- good
Next we need to calculate the minimum output
capacitance required to ensure that the output voltage
does not exceed the transient maximum limit, POSLIM
TR
,
starting from the actual static maximum, V
OUT_ST_POS
, when
a load release occurs:
V
ERR
V
V
DC
OUT
POS
_
ST
_
OUT
+
=
For our example:
V
OUT_ST_POS
= 1.222V
V
TOL
V
POSLIM
TR
OUT
TR
=
Where TOL
TR
is the transient tolerance. For our example:
POSLIM
TR
= 1.296V
The minimum output capacitance is calculated as
follows:
(
)
F
V
POSLIM
2
I
I
L
C
2
POS
_
ST
_
OUT
2
TR
2
)
MAX
(
VBAT
_
RIPPLE
OUT
)
MIN
(
OUT
-
+
=
This calculation assumes the absolute worst case
condition of a full-load to no load step transient occurring
when the inductor current is at its highest. The
capacitance required for smaller transient steps my be
calculated by substituting the desired current for the I
OUT
term.
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2005 Semtech Corp.
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SC485
POWER MANAGEMENT
For our example:
C
OUT(MIN)
= 595F.
We will select 440F, using two 220F, 25m
capacitors in parallel. For smaller load release overshoot,
660F may be used.
Next we calculate the RMS input ripple current, which is
largest at the minimum battery voltage:
(
)
RMS
MIN
_
BAT
OUT
OUT
)
MIN
(
BAT
OUT
)
RMS
(
IN
A
V
I
V
V
V
I
-
=
For our example:
I
IN(RMS)
= 2.14A
RMS
Input capacitors should be selected with sufficient ripple
current rating for this RMS current, for example a 10F,
1210 size, 25V ceramic capacitor can handle
approximately 3A
RMS
. Refer to manufacturer's data
sheets.
Finally, we calculate the current limit resistor value. As
described in the current limit section, the current limit
looks at the "valley current", which is the average output
current minus half the ripple current. We use the
maximum room temperature specification for MOSFET
R
DS(ON)
at V
GS
= 4.5V for purposes of this calculation:
A
2
I
I
I
)
MIN
(
VBAT
_
RIPPLE
OUT
VALLEY
-
=
The ripple at low battery voltage is used because we want
to make sure that current limit does not occur under
normal operating conditions.
(
)
Ohms
10
10
4
.
1
R
2
.
1
I
R
6
)
ON
(
DS
VALLEY
ILIM
-
=
For our example:
I
VALLEY
= 5.13A, R
DS(ON)
= 9m
and R
ILIM
= 7.76k
We select the next lowest 1% resistor value: 7.68k
Adding an Additional Output Voltage For Dynamic
Voltage Switching
If we design this output to be capable of dynamically
switching between 1.2V and 1.0V, then we would repeat
these calculations to determine if any components need
changing.
The 1.0V output suggests a value for C
TOP
of 82pF, but
the value of 56pF required by the 1.2V design should
work fine, and can always be increased if necessary.
Also, the current limit resistor required is slightly higher:
R
ILIM
= 7.87k
. The higher value should be used.
Lastly, the bottom feedback resistor, R
BOT
will need to
change to 20.0k
.
The schematic in Figure 8 on Page 17 shows the
complete design.
Dynamically Switching Output Voltages
It is important to note that in order for dynamic output
voltage switching to work, the SC485 must be in
Continuous Conduction Mode (EN/PSV = floating) when
transitioning from V
OUT(HIGH)
to V
OUT(LOW)
. This is because
otherwise the SC485 has no means to discharge the
output voltage and may OVP and latch off when this
transition is initiated (depending upon the difference
between the two voltages). If CCM is on, the SC485 will
actively discharge the output down to the correct voltage.
Dynamically switching output voltages is very easy,
requiring one switch to add or remove an additional
resistor in parallel to the bottom feedback resistor. Ideally,
the resistor will be switched using an open drain output
from another IC, as shown in Figure 4.
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SC485
POWER MANAGEMENT
0402
C15
56p
0402
R11 49k9
0402
0402
OPEN DRAIN SIGNAL
VOUT2
VSSA2
EN/PSV2
8
TON2
9
VOUT2
10
VCCA2
11
FB2
12
PGD2
13
VSSA2
14
PGND2
15
DL2
16
VDDP2
17
ILIM2
18
LX2
19
DH2
20
BST2
21
U1
SC485 OUT2
LOW = 1.2V
H IGH = 1.0V
R9
20k0
R13
20k0
VOUT
Figure 4: Dynamic Voltage Switching Using Direct
Drive Method (V
OUT(HIGH)
/V
OUT(LOW)
< 1.16 only)
Another option is to switch using an external discrete
MOSFET, as shown in Figure 5 below.
0402
0402
C15
56p
0402
R11 49k9
0402
OPEN DRAIN SIGNAL
VOUT2
VSSA2
EN/PSV2
8
TON2
9
VOUT2
10
VCCA2
11
FB2
12
PGD2
13
VSSA2
14
PGND2
15
DL2
16
VDDP2
17
ILIM2
18
LX2
19
DH2
20
BST2
21
U1
SC485 OUT2
LO W = 1. 0V
H I GH = 1.2V
R9
20k0
R13
20k0
VOUT
Q5
R15
R14
pull-up
C21
0402
0402
0402
Figure 5: Dynamic Voltage Switching Using Indirect
Drive Method
The problem with the external MOSFET method is that
the Drain-Gate capacitance, c
DG
, can cause the output
voltage to go even higher when the MOSFET is first turned
off (which should make the output voltage drop). This is
because the gate going low causes the drain to go low
momentarily due to c
DG
, which in turn causes V
FB
to go
low, making the output rise. The extra R15 and C21 in
the gate drive for the MOSFET are there to slow down
the slew rate of the gate voltage, thus avoiding this
problem.
Determining what circuit to use depends upon the ratio
between V
OUT(HIGH)
and V
OUT(LOW)
, since the goal is to avoid
inadvertently tripping the over-voltage protection. If:
16
.
1
V
V
)
LOW
(
OUT
)
HIGH
(
OUT
<
This means that the ratio is less than the worst case OVP
threshold for OUT2 (worst case in this case is the lowest
threshold), then the direct drive (simplest) method may
be used. Of course the indirect drive method may also
be used if desired. If:
16
.
1
V
V
)
LOW
(
OUT
)
HIGH
(
OUT
>
This means that the ratio is greater than the worst case
OVP threshold, therefore we automatically need to slew
the rate of change, and the indirect drive method must
be used.
If using the indirect drive method, the goal is to slow
down the gate drive for the transition from V
OUT(HIGH)
to
V
OUT(LOW)
, which is when the external MOSFET is turned
off. The pullup resistor, pulldown resistor and gate
capacitor can be selected as follows:
1) V
GATE
must be below the gate threshold voltage of the
MOSFET in order to ensure that it can be turned off, see
Figure 6 below:
Q5
R15
R14
pull-up
VPULL-UP
C21
0402
0402
0402
(
)
)
TH
(
GS
PULLUP
V
15
R
14
R
V
15
R
<
+
Figure 6: Ensuring Q3 Will Turn Off
2) the RC time constant of R15 and C21 should be at
least 4 times greater than the typical Over Voltage Fault
Delay Time of 5s to avoid V
OUT
rising prior to falling.
3) V
PULLUP
must be high enough to turn the MOSFET on.
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2005 Semtech Corp.
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SC485
POWER MANAGEMENT
Figure 7 below shows recommended components that
work well.
Q5
R15 1k
R14
10k
VPULL-UP
C21
22n
0402
0402
0402
Figure 7: Recommended Component Values
Please see the example switching waveforms on Pages
26 and 27.
Thermal Considerations
The junction temperature of the device may be calculated
as follows:
C
P
T
T
JA
D
A
J
+
=
Where:
T
A
= ambient temperature (C)
P
D
= power dissipation in (W)
JA
= thermal impedance junction to ambient from
absolute maximum ratings (C/W)
The power dissipation may be calculated as follows:
(
)
W
D
mA
1
VBST
f
Q
V
D
mA
1
VBST
f
Q
V
I
VDDP
I
VCCA
2
P
2
2
2
g
g
1
1
1
g
g
VDDP
VCCA
D
+
+
+
+
+
=
Where:
VCCA = chip supply voltage (V)
I
VCCA
= operating current (A)
VDDP = gate drive supply voltage (V)
I
VDDP
= gate drive operating current (A)
V
g
= gate drive voltage, typically 5V (V)
Q
gx
= FET gate charge, from the FET datasheet (C)
f
x
= switching frequency (kHz)
VBST = boost pin voltage during t
ON
(V)
D
x
= duty cycle
Inserting the following values for VBAT
(MIN)
condition (since
this is the worst case condition for power dissipation in
the controller) as an example (OUT1 = 1.5V, OUT2 = 1.2V):
T
A
= 85C
JA
= 84C/W
VCCA = VDDP = 5V
I
VCCA
= 1100A (data sheet maximum)
I
VDDP
= 150A (data sheet maximum)
V
g
= 5V
Q
gx
= 60nC
f
1
= 250kHz
f
2
= 300kHz
VBAT
(MIN)
= 8V
VBST
(MIN)
= VBAT
(MIN)
+VDDP = 13V
D
1(MIN)
= 1.5/8 = 0.1875
D
2(MIN)
= 1.2/8 = 0.15
gives us:
(
)
W
182
.
0
15
.
0
10
1
13
10
300
10
60
5
1875
.
0
10
1
13
10
250
10
60
5
10
150
5
10
1100
5
2
P
3
3
9
3
3
9
6
6
D
=
+
+
+
+
+
=
-
-
-
-
-
-
and:
C
100
84
182
.
0
85
T
J
=
+
=
As can be seen, the heating effects due to internal power
dissipation are practically negligible, thus requiring no
special consideration thermally during layout.
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SC485
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Layout Guidelines
One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and
maximize heat dissipation. The IC ground references, VSSA1 and VSSA2, should be kept separate from power
ground. All components that are referenced to them should connect to them locally at the chip. VSSA1 and VSSA2
should connect to power ground at their respective output capacitors only.
Feedback traces must be kept far away from noise sources such as switching nodes, inductors and gate drives.
Route feedback traces with their respective VSSAs as a differential pair from the output capacitor back to the chip.
Run them in a "quiet layer" if possible.
Chip decoupling capacitors (VDDP, VCCA) should be located next to the pins and connected directly to them on the
same side.
Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling
(including the chip power ground connections). Power components should be placed to minimize loops and reduce
losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use
"minimum" land patterns for power components. Minimize trace lengths between the gate drivers and the gates of
the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most critical.
Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling
requirement (and to reduce parasitics) if routed on more than one layer
Current sense connections must always be made using Kelvin connections to ensure an accurate signal.
We will examine the SC485 OUT2 reference design used in the Design Procedure section while explaining the layout
guidelines in more detail, using the same generic components for OUT1.
VOUT2
R8
10R
0402
0402
0402
C15
56p
0402
0402
R11 49k9
0402
0402
VOUT SWITCH (1)
0603
R12 0R (2)
0402
7343
+
C16
220u/25m
7343
C13
0u1/25V
C14
10u/25V
0402
0603
1210
0603
0402
0603
N OTES
(1) driv en by an open drain with no pullup. LOW = 1.2V out, F LOATING = 1V out.
(2) R 6 and R 12 aid in k eeping VSSA1 and VSSA2 separate f rom PGN D except where des ired in lay out.
VOUT2
EN/PSV1
22
TON1
23
VOUT1
24
VCCA1
25
FB1
26
PGD1
27
VSSA1
28
PGND1
1
DL1
2
VDDP1
3
ILIM1
4
LX1
5
DH1
6
BST1
7
EN/PSV2
8
TON2
9
VOUT2
10
VCCA2
11
FB2
12
PGD2
13
VSSA2
14
PGND2
15
DL2
16
VDDP2
17
ILIM2
18
LX2
19
DH2
20
BST2
21
U1
SC485
C9
1uF
R4
R3
VOUT
C4
1nF
VBAT
R1
5VSUS
PGOOD
Q2
Q1
C10
1uF
R5
C5 0.1uF
D1
SOD323
C6
2n2/50V
5VSUS
VBAT
L1
+
C3
VOUT1
R2
10R
0402
0402
0402
0402
C7
0402
0603
0402
0402
R6 0R (2)
7343
+
C8
7343
0402
C1
0u1/25V
C2
10u/25V
0603
1210
0603
0402
0603
VOUT1
VSSA2
VSSA2
VSSA1
VSSA1
C19
1uF
R9
20k0
R13
20k0
VOUT
C18
1nF
R7
1M
5VSUS
PGOOD
VBAT
Q3
IRF7811AV
Q4
FDS6676S
C20
1uF
R10 7k87
C11 0.1uF
D2
SOD323
C12
2n2/50V
5VSUS
VBAT
L2
2u2
+
C17
220u/25m
Figure 8: Reference Design and Layout Example
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The layout can be considered in two parts, the control section referenced to VSSA1/2 and the power section.
Looking at the control section first, locate all components referenced to VSSA1/2 on the schematic and place
these components at the chip. Connect VSSA1 and VSSA2 using either a wide (>0.020") trace. Very little current
flows in the chip ground therefore large areas of copper are not needed.
R8
10R
0402
0402
0402
0402
C15
56p
0402
R11 49k9
0402
0402
VOUT SWITCH (1)
0603
0603
VOUT2
EN/PSV1
22
TON1
23
VOUT1
24
VCCA1
25
FB1
26
PGD1
27
VSSA1
28
PGND1
1
DL1
2
VDDP1
3
ILIM1
4
LX1
5
DH1
6
BST1
7
EN/PSV2
8
TON2
9
VOUT2
10
VCCA2
11
FB2
12
PGD2
13
VSSA2
14
PGND2
15
DL2
16
VDDP2
17
ILIM2
18
LX2
19
DH2
20
BST2
21
U1
SC485
C9
1uF
R4
R3
VOUT
VBAT
C4
1nF
R1
PGOOD
5VSUS
C10
1uF
5VSUS
R2
10R
0402
0402
0402
0402
C7
0402
0402
0603
0603
VOUT1
VSSA2
VSSA1
C19
1uF
R9
20k0
R13
20k0
VOUT
C18
1nF
5VSUS
R7
1M
VBAT
PGOOD
C20
1uF
5VSUS
Figure 9: Components Connected to VSSA1 and VSSA2
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Figure 10: Example VSSA 0.020" Traces
In Figure 10, all components referenced to VSSA1 and VSSA2 have been placed and have been connected using
0.020" traces. Note that there are two separate traces, one for VSSA1 and one for VSSA2. Decoupling capacitors
C9 and C19 are as close as possible to their pins, as are VDDP decoupling capacitors C10 and C20. C10 and C20
should connect to the ground plane using two vias each.
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VOUT2
VOUT
VSSA2
VSSA1
VOUT1
VOUT
VOUT2
0402
0402
C15
56p
0402
R12 0R (2)
0402
7343
+
C16
220u/25m
7343
VOUT2
EN/PSV1
22
TON1
23
VOUT1
24
VCCA1
25
FB1
26
PGD1
27
VSSA1
28
PGND1
1
DL1
2
VDDP1
3
ILIM1
4
LX1
5
DH1
6
BST1
7
EN/PSV2
8
TON2
9
VOUT2
10
VCCA2
11
FB2
12
PGD2
13
VSSA2
14
PGND2
15
DL2
16
VDDP2
17
ILIM2
18
LX2
19
DH2
20
BST2
21
U1
SC485
R4
R3
+
C3
VOUT1
0402
0402
C7
0402
0402
R6 0R (2)
7343
7343
+
C8
VOUT1
VSSA2
VSSA2
VSSA1
VSSA1
R9
20k0
R13
20k0
+
C17
220u/25m
Figure 11: Differential Routing of Feedback and Ground Reference Traces
In Figure 11, VOUT1 and VSSA1 are routed as a differential pair from the output capacitors back to the feedback
components and device. Similarly, VOUT2 and VSSA2 are routed as a differential pair from the output capacitors
back to the feedback components and device.
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Next, looking at the power section, the schematic in Figure 12 below shows the power section and input loop for
OUT2:
C12
2n2/50V
VBAT
L2
VOUT2
+
C17
0402
R12 0R (2)
7343
7343
+
C16
0402
C13
0u1/25V
C14
10u/25V
1210
0603
2u2
220u/25m
220u/25m
S
1
S
2
S
3
G
4
D
5
D
6
D
7
D
8
Q3 IRF7811AV
S
1
S
2
S
3
G
4
D
5
D
6
D
7
D
8
Q4 FDS6676S
Figure 12: Power Section and Input Loop
The schematic has been redrawn to emphasize the input loop. The highest di/dts occur in the input loops and thus
these should be kept as small as possible. The input capacitors should be placed with the highest frequency
capacitors closest to the loop to reduce EMI. Use large copper pours to minimize losses and parasitics. Exactly the
same philosophy applies to the OUT1 power section and input loop. Figure 13 below shows an example of the layout
for the power section using these guidelines.
Figure 13: Power Component Placement and Copper Pours
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Key points for the power section:
1) there should be a very small input loop, well decoupled.
2) the phase node should be a large copper pour, but compact since this is the noisiest node.
3) input power ground and output power ground should not connect directly, but through the ground planes instead.
4) The two outputs should not share their input capacitors, and these should have separate PWR_SRC and PGND
(component-side) copper pours.
5) The two output inductors should not be placed adjacent to each other to avoid crosstalk.
6) Notice in Figure 13 placement of 0
resistor at the bottom of the output capacitor to connect to VSSA1/2 for
each output.
Connecting the control and power sections should be accomplished as follows (see Figure 14 below):
1) Route VSSA1/2 and their related feedback traces as differential pairs routed in a "quiet" layer away from noise
sources.
2) Route DL, DH and LX (low side FET gate drive, high side FET gate drive and phase node) to chip using wide traces
with multiple vias if using more than one layer. These connections to be as short as possible for loop minimization,
with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power
ground as its return path. LX is the noisiest node in the circuit, switching between PWR_SRC and ground at high
frequencies, thus should be kept as short as practical. DH has LX as its return path.
3) BST is also a noisy node and should be kept as short as possible.
4) Connect PGND pins on the chip directly to the VDDP decoupling capacitor and then drop vias directly to the
ground plane.
5) Locate the current limit sense resistors between the LX and ILIM pins at the device.
0402
EN/PSV1
22
TON1
23
VOUT1
24
VCCA1
25
FB1
26
PGD1
27
VSSA1
28
PGND1
1
DL1
2
VDDP1
3
ILIM1
4
LX1
5
DH1
6
BST1
7
EN/PSV2
8
TON2
9
VOUT2
10
VCCA2
11
FB2
12
PGD2
13
VSSA2
14
PGND2
15
DL2
16
VDDP2
17
ILIM2
18
LX2
19
DH2
20
BST2
21
U1
SC485
Q2
Q1
R5
L1
0402
Q3
IRF7811AV
Q4
FDS6676S
R10 7k87
L2
2u2
Figure 14: Connecting Control and Power Sections
Phase nodes (black) to be copper islands (preferred) or wide copper traces. Gate drive traces (red) and phase node
traces (blue) to be wide copper traces (L:W < 20:1) and as short as possible, with DL the most critical.
23
2005 Semtech Corp.
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SC485
POWER MANAGEMENT
Typical Characteristics
1.2V Efficiency (Power Save Mode)
vs. Output Current vs. Input Voltage
1.2V Efficiency (Continuous Conduction Mode)
vs. Output Current vs. Input Voltage
1.2V Output Voltage (Power Save Mode)
vs. Output Current vs. Input Voltage
1.2V Output Voltage (Continuous Conduction Mode)
vs. Output Current vs. Input Voltage
1.2V Switching Frequency (Power Save Mode)
vs. Output Current vs. Input Voltage
1.2V Switching Frequency (Continuous Conduction
Mode) vs. Output Current vs. Input Voltage
50
55
60
65
70
75
80
85
90
95
100
0
1
2
3
4
5
6
I
OUT
(A)
E
ffi
cien
cy (
%
)
V
BAT
= 20V
V
BAT
= 8V
1.180
1.184
1.188
1.192
1.196
1.200
1.204
1.208
1.212
1.216
1.220
0
1
2
3
4
5
6
I
OUT
(A)
V
OUT
(V
)
V
BAT
= 20V
V
BAT
= 8V
0
50
100
150
200
250
300
350
400
0
1
2
3
4
5
6
I
OUT
(A)
F
r
eq
ue
ncy (kH
z
)
V
BAT
= 20V
V
BAT
= 8V
50
55
60
65
70
75
80
85
90
95
100
0
1
2
3
4
5
6
I
OUT
(A)
E
ffi
cien
cy (
%
)
V
BAT
= 8V
V
BAT
= 20V
1.180
1.184
1.188
1.192
1.196
1.200
1.204
1.208
1.212
1.216
1.220
0
1
2
3
4
5
6
I
OUT
(A)
V
OUT
(V
)
V
BAT
= 20V
V
BAT
= 8V
0
50
100
150
200
250
300
350
400
0
1
2
3
4
5
6
I
OUT
(A)
F
r
eq
ue
ncy (kH
z
)
V
BAT
= 20V
V
BAT
= 8V
Please refer to Figure 8 on Page 17 for test schematic (OUT2)
24
2005 Semtech Corp.
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SC485
POWER MANAGEMENT
Typical Characteristics (Cont.)
Load Transient Response,
Continuous Conduction Mode, 0A to 6A to 0A
Trace 1: 1.2V, 50mV/div., AC coupled
Trace 2: LX, 20V/div
Trace 3: not connected
Trace 4: load current, 5A/div
Timebase: 40s/div.
Load Transient Response,
Continuous Conduction Mode, 0A to 6A Zoomed
Load Transient Response,
Continuous Conduction Mode, 6A to 0A Zoomed
Trace 1: 1.2V, 50mV/div., AC coupled
Trace 2: LX, 10V/div
Trace 3: not connected
Trace 4: load current, 5A/div
Timebase: 10s/div.
Trace 1: 1.2V, 20mV/div., AC coupled
Trace 2: LX, 10V/div
Trace 3: not connected
Trace 4: load current, 5A/div
Timebase: 10s/div.
Please refer to Figure 8 on Page 17 for test schematic (OUT2)
25
2005 Semtech Corp.
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SC485
POWER MANAGEMENT
Typical Characteristics (Cont.)
Load Transient Response,
Power Save Mode, 0A to 6A to 0A
Trace 1: 1.2V, 50mV/div., AC coupled
Trace 2: LX, 20V/div
Trace 3: not connected
Trace 4: load current, 5A/div
Timebase: 40s/div.
Load Transient Response,
Power Save Mode, 0A to 6A Zoomed
Load Transient Response,
Power Save Mode, 6A to 0A Zoomed
Trace 1: 1.2V, 50mV/div., AC coupled
Trace 2: LX, 10V/div
Trace 3: not connected
Trace 4: load current, 5A/div
Timebase: 10s/div.
Trace 1: 1.2V, 20mV/div., AC coupled
Trace 2: LX, 10V/div
Trace 3: not connected
Trace 4: load current, 5A/div
Timebase: 10s/div.
Please refer to Figure 8 on Page 17 for test schematic (OUT2)
26
2005 Semtech Corp.
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SC485
POWER MANAGEMENT
Typical Characteristics (Cont.)
Dynamic Output Voltage Switching
From 1V to 1.2V to 1V, No Load
Trace 1: toggle signal (for reference only)
Trace 2: LX, 20V/div
Trace 3: VOUT, 50mV/div, offset 1V
Trace 4: not connected
Timebase: 200s/div.
Dynamic Output Voltage Switching
From 1V to 1.2V Zoomed, No Load
Dynamic Output Voltage Switching
From 1.2V to 1V Zoomed, No Load
Trace 1: toggle signal (for reference only)
Trace 2: LX, 20V/div
Trace 3: VOUT, 50mV/div, offset 1V
Trace 4: not connected
Timebase: 10s/div.
Trace 1: toggle signal (for reference only)
Trace 2: LX, 20V/div
Trace 3: VOUT, 50mV/div, offset 1V
Trace 4: not connected
Timebase: 10s/div.
Please refer to Figure 8 on Page 17 for test schematic (OUT2)
27
2005 Semtech Corp.
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SC485
POWER MANAGEMENT
Typical Characteristics (Cont.)
Dynamic Output Voltage Switching
From 1V to 1.2V to 1V, 6A Load
Trace 1: toggle signal (for reference only)
Trace 2: LX, 20V/div
Trace 3: VOUT, 50mV/div, offset 1V
Trace 4: not connected
Timebase: 200s/div.
Dynamic Output Voltage Switching
From 1V to 1.2V Zoomed, 6A Load
Dynamic Output Voltage Switching
From 1.2V to 1V Zoomed, 6A Load
Trace 1: toggle signal (for reference only)
Trace 2: LX, 20V/div
Trace 3: VOUT, 50mV/div, offset 1V
Trace 4: not connected
Timebase: 10s/div.
Trace 1: toggle signal (for reference only)
Trace 2: LX, 20V/div
Trace 3: VOUT, 50mV/div, offset 1V
Trace 4: not connected
Timebase: 10s/div.
Please refer to Figure 8 on Page 17 for test schematic (OUT2)
28
2005 Semtech Corp.
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SC485
POWER MANAGEMENT
Typical Characteristics (Cont.)
Startup (PSV), EN/PSV Going High
Trace 1: 1.2V, 0.5V/div.
Trace 2: LX, 10V/div
Trace 3: EN/PSV, 5V/div
Trace 4: PGD, 5V/div.
Timebase: 1ms/div.
Startup (CCM), EN/PSV 0V to Floating
Trace 1: 1.2V, 0.5V/div.
Trace 2: LX, 10V/div
Trace 3: EN/PSV, 5V/div
Trace 4: PGD, 5V/div.
Timebase: 1ms/div.
Please refer to Figure 8 on Page 17 for test schematic (OUT2)
29
2005 Semtech Corp.
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SC485
POWER MANAGEMENT
N
A
A2
A1
bxN
E1
.378
9.60
.386
9.70 9.80
PLANE
bbb
C A-B D
ccc C
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
3.
OR GATE BURRS.
DATUMS AND TO BE DETERMINED AT DATUM PLANE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
-B-
NOTES:
1.
2.
-A-
-H-
SIDE VIEW
A
B
C
D
e
H
e/2
(.039)
.008
-
.004
.024
-
-
-
-
0
L
(L1)
c
01
GAGE
PLANE
SEE DETAIL
DETAIL
A
A
0.25
.026 BSC
.252 BSC
28
.004
.169 .173
.007
-
28
0.10
0.65 BSC
6.40 BSC
4.40
-
.177 4.30
.012 0.19
4.50
0.30
.382
2X N/2 TIPS
SEATING
aaa C
E/2
INDICATOR
PIN 1
2X
2
1
3
.018
.003
.031
.002
-
8
0
0.20
0.10
-
8
0.45
0.09
0.80
0.05
.030
.007
.047
.042
.006
-
0.60
(1.0)
-
0.75
0.20
-
-
-
1.20
1.05
0.15
D
REFERENCE JEDEC STD MO-153, VARIATION AE.
4.
INCHES
b
N
bbb
aaa
ccc
01
E1
E
L
L1
e
D
c
DIM
A1
A2
A
MIN
MAX
MILLIMETERS
DIMENSIONS
MIN
MAX
NOM
NOM
E
Outline Drawing - TSSOP-28
30
2005 Semtech Corp.
www.semtech.com
SC485
POWER MANAGEMENT
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
Contact Information
(.222)
(5.65)
Z
G
Y
P
(C)
4.10
.161
0.65
.026
0.40
.016
1.55
.061
7.20
.283
X
INCHES
DIMENSIONS
Z
P
Y
X
DIM
C
G
MILLIMETERS
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
NOTES:
1.
Land Pattern - TSSOP-28
PDF 
ZIP