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1
DESCRIPTION
The LH168A is a 384-output TFT-LCD source
driver IC which can simultaneously display 262 144
colors in 64 gray scales.
FEATURES
Number of LCD drive outputs : 384
Built-in 6-bit digital input DAC
2-port input for each circuit of data inputs R, G
and B, and it is possible to sample and hold
display data of two pixels at the same time
Possible to display 262 144 colors in 64 gray scales
with reference voltage input of 10 gray scales : This
reference voltage input corresponds to < correction
and intermediate reference voltage input can be
abbreviated
Cascade connection
Sampling sequence :
Output shift direction can be selected
XO
1
, YO
1
, ZO
1
/XO
128
, YO
128
, ZO
128
or
ZO
128
, YO
128
, XO
128
/ZO
1
, YO
1
, XO
1
Shift clock frequency : 55 MHz (MAX.)
Supply voltages
V
CC
(for logic system) : +2.7 to +3.6 V
V
LS
(for LCD drive system) : +3.0 to +5.5 V
Package : 444-pin TCP (Tape Carrier Package)
PIN CONNECTIONS
LH168A
LH168A
384-output TFT-LCD Source Driver IC
XO
128
YO
128
ZO
128
382
383
384
XO
1
YO
1
ZO
1
1
2
3
CHIP SURFACE
GNDA
V
LS
TESTB
XA
5
XA
0
YA
5
YA
0
ZA
5
ZA
0
SPOI
GNDL
POL
1
POL
2
CK
V
CC
V
1
V
2
V
3
V
4
V
5
V
6
V
7
V
8
V
9
V
10
SPIO
XB
5
XB
0
YB
5
YB
0
ZB
5
ZB
0
LS
LBR
V
LS
GNDA
444
443
442
441
436
435
430
429
424
423
422
421
420
419
418
417
416
415
414
413
412
411
410
409
408
407
406
401
400
395
394
389
388
387
386
385
444-PIN TCP
TOP VIEW
NOTE :
Doesn't prescribe TCP outline.
2
LH168A
PIN DESCRIPTION
PIN NO.
SYMBOL
I/O
DESCRIPTION
1 to 384
XO
1
-ZO
128
O
LCD drive output pins
385, 444
GNDA
Ground pins for analog circuit
386, 443
V
LS
Power supply pins for analog circuit
387
LBR
I
Shift direction selection input pin
388
LS
I
Latch input pin
389 to 394
ZB
0
-ZB
5
I
Data input pins
395 to 400
YB
0
-YB
5
I
Data input pins
401 to 406
XB
0
-XB
5
I
Data input pins
407
SPIO
I/O
Start pulse input/cascade output pin
408 to 417
V
10
-V
1
I
Reference voltage input pins
418
V
CC
Power supply pin for digital circuit
419
CK
I
Shift clock input pin
420, 421
POL
2
, POL
1
I
Input data polarity exchange input pins
422
GNDL
Ground pin for digital circuit
423
SPOI
I/O
Start pulse input/cascade output pin
IC test pin
I
TESTB
442
Data input pins
I
XA
0
-XA
5
436 to 441
Data input pins
I
YA
0
-YA
5
430 to 435
Data input pins
I
ZA
0
-ZA
5
424 to 429
LH168A
3
BLOCK DIAGRAM
POL
1
421
CK 419
395
406
401
YA
0
430
LS
POL
2
441
XA
0
XB
0
XB
5
YB
0
YB
5
ZB
0
ZB
5
436
SPIO 407
LBR 387
V
4
414
V
3
415
V
2
416
V
1
417
V
7
411
V
6
412
V
5
413
V
10
408
1
V
9
409
V
8
410
389
400
ZA
0
424
YA
5
435
394
ZA
5
429
388
420
382
386
423
422
418
444
385
SPOI
442 TESTB
V
LS
443 V
LS
XO
1
2
YO
1
3
ZO
1
XO
128
383
YO
128
384
ZO
128
6 x 2
6 x 2
6 x 2
6 x 2
6 x 2
6 x 2
64
6 x 2
6 x 2
6 x 2
6 x 2
64
2
1
6 x 2
6 x 2
V
CC
GNDL
GNDA GNDA
SHIFT REGISTER
SAMPLING MEMORY
HOLD MEMORY
DATA
LATCH
REFERENCE
VOLTAGE
GENERATION
CIRCUIT
LEVEL SHIFTER
DA CONVERTER
OUTPUT CIRCUIT
XA
5
FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK
FUNCTION
Shift Register
Used as a bi-directional shift register which performs the shifting operation by CK and
selects bits for data sampling.
Data Latch
Used to temporary latch the input data which is sent to the sampling memory.
Sampling Memory
Used to sample the data to be entered by time sharing.
Hold Memory
Used for temporary latch processing of data in the sampling memory by LS input.
Level Shifter
Used to shift the data in the hold memory to the power supply level of the analog circuit
unit and sends the shifted data to DA converter.
Reference Voltage
Generation Circuit
Used to generate a gamma-corrected 64-level voltage by the resistor dividing circuit.
DA Converter
Used to generate an analog signal according to the display data and sends the signal to
the output circuit.
Output Circuit
Used as a voltage follower, configured with an operational amplifier and an output buffer,
which outputs analog signals of 64 gray scales to LCD drive output pin.
INPUT/OUTPUT CIRCUITS
I
V
CC
GNDL
To Internal Circuit
Fig. 1 Input Circuit (1)
Applicable pins
CK, LS, LBR,
XA
0
-XA
5
, XB
0
-XB
5
,
YA
0
-YA
5
, YB
0
-YB
5
,
ZA
0
-ZA
5
, ZB
0
-ZB
5
I
V
CC
GNDL
GNDL
To Internal Circuit
Fig. 2 Input Circuit (2)
Applicable pins
POL
1
, POL
2
LH168A
4
LH168A
5
I
V
CC
V
CC
GNDL
To Internal Circuit
Fig. 3 Input Circuit (3)
Applicable pin
TESTB
O
V
LS
GNDA
From Internal Circuit
Operational Amplifier
+
Fig. 5 Output Circuit
Applicable pins
XO
1
-XO
128
,
YO
1
-YO
128
,
ZO
1
-ZO
128
V
CC
GNDL
Nch Tr
Output Signal
Output Control Signal
V
CC
GNDL
To Internal Circuit
I
O
Pch Tr
Fig. 4 Input/Output Circuit
Applicable pins
SPIO, SPOI
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