PROFET Preliminary BTS 725 L1
Semiconductor Group
1
03.96
Smart Two Channel Highside Power Switch
Features
Overload protection
Current limitation
Short-circuit protection
Thermal shutdown
Overvoltage protection
(including load dump)
Reverse battery protection
1)
Undervoltage and overvoltage shutdown
with auto-restart and hysteresis
Open drain diagnostic output
Open load detection in ON-state
CMOS compatible input
Loss of ground and loss of V
bb
protection
Electrostatic discharge (ESD) protection
Application
C compatible power switch with diagnostic feedback
for 12 V DC grounded loads
Most suitable for resistive and lamp loads
Replaces electromechanical relays and discrete circuits
General Description
N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic
feedback, monolithically integrated in Smart SIPMOS
technology. Fully protected by embedded protection
functions.
Pin Definitions and Functions
Pin
Symbol
Function
1,10,
11,12,
15,16,
19,20
V
bb
Positive power supply voltage. Design the
wiring for the simultaneous max. short circuit
currents from channel 1 to 2 and also for low
thermal resistance
3
IN1
Input 1,2, activates channel 1,2 in case of
7
IN2
logic high signal
17,18
OUT1
Output 1,2, protected high-side power output
13,14
OUT2
of channel 1,2. Design the wiring for the max.
short circuit current
4
ST1
Diagnostic feedback 1,2 of channel 1,2,
8
ST2
open drain, low on failure
2
GND1
Ground 1 of chip 1 (channel 1)
6
GND2
Ground 2 of chip 2 (channel 2)
5,9
N.C.
Not Connected
1
)
With external current limit (e.g. resistor R
GND
=150
) in GND connection, resistor in series with ST
connection, reverse load current limited by connected load.
Product Summary
Overvoltage Protection
V
bb(AZ)
43
V
Operating voltage
V
bb(on)
5.0 ... 24
V
active channels:
one
two parallel
On-state resistance
R
ON
60
30
m
Nominal load current
I
L(NOM)
4.0
6.0
A
Current limitation
I
L(SCr)
17
17
A
Pin configuration
(top view)
V
bb
1
20 V
bb
GND1 2
19 V
bb
IN1 3
18 OUT1
ST1 4
17 OUT1
N.C. 5
16 V
bb
GND2 6
15 V
bb
IN2 7
14 OUT2
ST2 8
13 OUT2
N.C. 9
12 V
bb
V
bb
10
11 V
bb
Preliminary BTS 725 L1
Semiconductor Group
2
Block diagram
Two Channels; Open Load detection in on state;
IN1
ST1
ESD
Logic
Voltage
sensor
Voltage
source
Open load
detection
Charge pump
Level shifter
Temperature
sensor
Rectifier
Gate
protection
Current
limit
3
4
V
Logic
Overvoltage
protection
GND1
R
O1
Signal GND
GND1
1
Chip 1
Chip 1
IN2
ST2
PROFET
7
8
6
GND2
R
O2
Leadframe connected to pin 1, 10, 11, 12, 15, 16, 19, 20
Signal GND
GND2
Chip 2
Chip 2
+ Vbb
OUT1
Leadframe
17,18
Load GND
Load
+ Vbb
OUT2
Leadframe
13,14
Load GND
Load
Logic and protection circuit of chip 2
(equivalent to chip 1)
Maximum Ratings at T
j
= 25C unless otherwise specified
Parameter
Symbol
Values
Unit
Supply voltage (overvoltage protection see page 4)
V
bb
43
V
Supply voltage for full short circuit protection
T
j,start
=
-40 ...+150C
V
bb
24
V
Preliminary BTS 725 L1
Maximum Ratings at T
j
= 25C unless otherwise specified
Parameter
Symbol
Values
Unit
Semiconductor Group
3
Load current (Short-circuit current, see page 5)
I
L
self-limited
A
Load dump protection
2
)
V
LoadDump
=
U
A
+
V
s
,
U
A
= 13.5 V
R
I
3
)
= 2
,
t
d
= 200
ms; IN
= low or high,
each channel loaded with
R
L
=
3.4
,
V
Load
dump
4
)
60
V
Operating temperature range
Storage temperature range
T
j
T
stg
-40 ...+150
-55 ...+150
C
Power dissipation (DC)
5
T
a
= 25C:
(all channels active)
T
a
= 85C:
P
tot
3.7
1.9
W
Electrostatic discharge capability (ESD)
(Human Body Model)
V
ESD
1.0
kV
Input voltage (DC)
V
IN
-10 ... +16
V
Current through input pin (DC)
Current through status pin (DC)
see internal circuit diagram page 8
I
IN
I
ST
2.0
5.0
mA
Thermal resistance
junction - soldering point
5),6)
each channel:
R
thjs
12
K/W
junction - ambient
5)
one channel active:
all channels active:
R
thja
41
34
2
)
Supply voltages higher than V
bb(AZ)
require an external current limit for the GND and status pins, e.g. with a
150
resistor in the GND connection and a 15 k
resistor in series with the status pin. A resistor for input
protection is integrated.
3)
R
I
= internal resistance of the load dump test pulse generator
4)
V
Load dump
is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839
5
)
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm
2
(one layer, 70
m thick) copper area for Vbb
connection. PCB is vertical without blown air. See page 14
6
)
Soldering point: upper side of solder edge of device pin 15. See page 14
Electrical Characteristics
Parameter and Conditions,
each of the two channels
Symbol
Values
Unit
at T
j
= 25 C,
V
bb
= 12 V unless otherwise specified
min
typ
max
Load Switching Capabilities and Characteristics
On-state resistance (Vbb to OUT)
I
L
= 2 A
each channel,
T
j
= 25C:
T
j
= 150C:
two parallel channels,
T
j
= 25C:
R
ON
--
50
100
25
60
120
30
m
Preliminary BTS 725 L1
Parameter and Conditions,
each of the two channels
Symbol
Values
Unit
at T
j
= 25 C,
V
bb
= 12 V unless otherwise specified
min
typ
max
Semiconductor Group
4
Nominal load current
one channel active:
two parallel channels active:
Device on PCB
5)
,
T
a
=
85C,
T
j
150C
I
L(NOM)
3.6
5.5
4.0
6.0
--
A
Output current while GND disconnected or pulled
up; V
bb
=
30 V,
V
IN
= 0, see diagram page 9
I
L(GNDhigh)
--
--
10
mA
Turn-on time
to 90%
V
OUT
:
Turn-off time
to 10%
V
OUT
:
R
L
=
12
,
T
j
=-40...+150C
t
on
t
off
80
80
200
230
400
450
s
Slew rate on
10 to 30%
V
OUT
,
R
L
=
12
,
T
j
=-40...+150C:
d
V/dt
on
0.1
--
1
V/
s
Slew rate off
70 to 40%
V
OUT
,
R
L
=
12
,
T
j
=-40...+150C:
-d
V/dt
off
0.1
--
1
V/
s
Operating Parameters
Operating voltage
7
)
T
j
=-40...+150C:
V
bb(on)
5.0
--
24
V
Undervoltage shutdown
T
j
=-40...+150C:
V
bb(under)
3.5
--
5.0
V
Undervoltage restart
T
j
=-40...+150C:
V
bb(u rst)
--
--
5.0
V
Undervoltage restart of charge pump
see diagram page 13
T
j
=-40...+150C:
V
bb(ucp)
--
5.6
7.0
V
Undervoltage hysteresis
V
bb(under)
=
V
bb(u rst)
-
V
bb(under)
V
bb(under)
--
0.2
--
V
Overvoltage shutdown
T
j
=-40...+150C:
V
bb(over)
24
--
34
V
Overvoltage restart
T
j
=-40...+150C:
V
bb(o rst)
23
--
--
V
Overvoltage hysteresis
T
j
=-40...+150C:
V
bb(over)
--
0.5
--
V
Overvoltage protection
8
)
T
j
=-40...+150C:
I
bb
=
40 mA
V
bb(AZ)
42
47
--
V
Standby current, all channels off
T
j
=25C
:
V
IN
=
0
T
j
=150C:
I
bb(off)
--
--
20
29
50
56
A
Leakage output current (included in
I
bb(off)
)
V
IN
=
0
I
L(off)
--
--
12
A
Operating current
9)
,
V
IN
=
5V, T
j
=-40...+150C
I
GND
=
I
GND1
+
I
GND2
,
one channel on:
two channels on:
I
GND
--
--
1.8
3.6
3.5
7
mA
7)
At supply voltage increase up to
V
bb
=
5.6
V typ without charge pump,
V
OUT
V
bb
- 2 V
8)
see also
V
ON(CL)
in circuit diagram on page 8.
9
)
Add
I
ST
, if
I
ST
> 0
Preliminary BTS 725 L1
Parameter and Conditions,
each of the two channels
Symbol
Values
Unit
at T
j
= 25 C,
V
bb
= 12 V unless otherwise specified
min
typ
max
Semiconductor Group
5
Protection Functions
Initial peak short circuit current limit,
(see timing
diagrams, page 11)
each channel, T
j
=-40C:
T
j
=25C:
T
j
=+150C:
I
L(SCp)
27
20
12
37
30
18
47
40
25
A
two parallel channels
twice the current of one channel
Repetitive short circuit current limit,
T
j
=
T
jt
each channel
two parallel channels
(see timing diagrams, page 11)
I
L(SCr)
--
--
17
17
--
--
A
Initial short circuit shutdown time
T
j,start
=-40C:
T
j,start
= 25C:
(see page 10 and timing diagrams on page 11)
t
off(SC)
--
--
5
4
--
--
ms
Thermal overload trip temperature
T
jt
150
--
--
C
Thermal hysteresis
T
jt
--
10
--
K
Reverse Battery
Reverse battery voltage
10
)
-
V
bb
--
--
32
V
Drain-source diode voltage
(V
out
> V
bb
)
I
L
=
-
4.0
A,
T
j
=
+150C
-
V
ON
--
610
--
mV
Diagnostic Characteristics
Open load detection current,
(on-condition)
each channel,
T
j
= -40C:
T
j
= 25C:
T
j
= +150C:
I
L (OL)
4
10
10
10
--
--
--
800
600
600
mA
two parallel channels
twice the current of one channel
Open load detection voltage
11
)
T
j
=-40..+150C:
V
OUT(OL)
2
3
4
V
Internal output pull down
(OUT to GND), V
OUT
=
5
V
T
j
=-40..+150C:
R
O
4
10
30
k
10
) Requires a 150
resistor in GND connection. The reverse load current through the intrinsic drain-source
diode has to be limited by the connected load. Note that the power dissipation is higher compared to normal
operating conditions due to the voltage drop across the intrinsic drain-source diode. The temperature
protection is not active during reverse current operation! Input and Status currents have to be limited (see
max. ratings page 3 and circuit page 8).
11)
External pull up resistor required for open load detection in off state.
Preliminary BTS 725 L1
Parameter and Conditions,
each of the two channels
Symbol
Values
Unit
at T
j
= 25 C,
V
bb
= 12 V unless otherwise specified
min
typ
max
Semiconductor Group
6
Input and Status Feedback
12
)
Input resistance
(see circuit page 8)
T
j
=-40..+150C:
R
I
2.5
3.5
6
k
Input turn-on threshold voltage
T
j
=-40..+150C:
V
IN(T+)
1.7
--
3.5
V
Input turn-off threshold voltage
T
j
=-40..+150C:
V
IN(T-)
1.5
--
--
V
Input threshold hysteresis
V
IN(T)
--
0.5
--
V
Off state input current
V
IN
= 0.4 V:
T
j
=-40..+150C:
I
IN(off)
1
--
50
A
On state input current
V
IN
= 5 V:
T
j
=-40..+150C:
I
IN(on)
20
50
90
A
Delay time for status with open load after switch
off
(see timing diagrams, page 12
),
T
j
=-40..+150C:
t
d(ST OL4)
100
520
1000
s
Status invalid after positive input slope
(open load)
T
j
=-40..+150C:
t
d(ST)
--
250
600
s
Status output (open drain)
Zener limit voltage
T
j
=-40...+150C,
I
ST
= +1.6 mA:
ST low voltage
T
j
=-40...+25C,
I
ST
= +1.6 mA:
T
j
= +150C,
I
ST
= +1.6 mA:
V
ST(high)
V
ST(low)
5.4
--
--
6.1
--
--
--
0.4
0.6
V
12)
If ground resistors R
GND
are used, add the voltage drop across these resistors.
Preliminary BTS 725 L1
Semiconductor Group
7
Truth Table
Cannel 1
Input 1
Output 1
Status 1
Cannel 2
Input 2
Output 2
Status 2
level
level
BTS 725L1
Normal
operation
L
H
L
H
H
H
Open load
L
H
Z
H
H (L
13)
)
L
Short circuit
to V
bb
L
H
H
H
L
14)
H (L
15)
)
Overtem-
perature
L
H
L
L
H
L
Under-
voltage
L
H
L
L
H
H
Overvoltage
L
H
L
L
H
H
L = "Low" Level
X = don't care
Z = high impedance, potential depends on external circuit
H = "High" Level
Status signal valid after the time delay shown in the timing diagrams
Parallel switching of channel 1 and 2 is easily possible by connecting the inputs and outputs in parallel. The
status outputs ST1 and ST2 have to be configured as a 'Wired OR' function with a single pull-up resistor.
Terms
PROFET
IN1
ST1
OUT1
GND1
Vbb
VST1
V
IN1
I IN1
V
bb
IL1
VOUT1
I
GND1
VON1
2
3
4
Leadframe
17,18
Ibb
I ST1
R
GND1
Chip 1
PROFET
IN2
ST2
OUT2
GND2
Vbb
VST2
V
IN2
I IN2
IL2
VOUT2
I
GND2
VON2
6
7
8
Leadframe
13,14
I ST2
R
GND2
Chip 2
Leadframe (V
bb
) is connected to pin 1,10,11,12,15,16,19,20
External R
GND
optional; two resistors R
GND1
, R
GND2
=
150
or a single resistor R
GND
=
75
for reverse
battery protection up to the max. operating voltage.
13
) With external resistor between output and Vbb
14)
An external short of output to V
bb
in the off state causes an internal current from output to ground. If R
GND
is
used, an offset voltage at the GND and ST pins will occur and the V
ST low
signal may be errorious.
15
) Low resistance to
V
bb
may be detected by no-load-detection
Preliminary BTS 725 L1
Semiconductor Group
8
Input circuit (ESD protection),
IN1 or IN2
IN
GND
I
R
ESD-ZD
I
I
I
ESD zener diodes are not to be used as voltage clamp at
DC conditions. Operation in this mode may result in a drift of
the zener voltage (increase of up to 1 V).
Status output,
ST1 or ST2
ST
GND
ESD-
ZD
+5V
R
ST(ON)
ESD-Zener diode: 6.1
V typ., max 5.0 mA; R
ST(ON)
< 380
at 1.6 mA, ESD zener diodes are not to be used as voltage
clamp at DC conditions. Operation in this mode may resul
t
in
a drift of
the zener voltage (increase of up to 1 V).
overvoltage output clamp,
OUT1 or OUT2
+Vbb
OUT
PROFET
VZ
V
ON
Power GND
V
ON
clamped to
V
ON(CL)
= 47 V typ.
Overvoltage protection of logic part
GND1 or GND2
+ Vbb
IN
ST
ST
R
GND
GND
R
Signal GND
Logic
PROFET
V
Z2
I
R
V
Z1
V
Z1
=
6.1
V typ., V
Z2
=
47
V typ., R
I
=
3.5
k
typ.
,
R
GND
=
150
, R
ST
=
15
k
nominal.
Reverse battery protection
GND
Logic
ST
R
IN
ST
+ 5V
OUT
L
R
Power GND
GND
R
Signal GND
Power
Inverse
I
R
Vbb
-
Diode
R
GND
= 150
,
R
I
= 3.5 k
typ
,
Temperature protection is not active during inverse current
operation.
Preliminary BTS 725 L1
Semiconductor Group
9
Open-load detection,
OUT1 or OUT2
ON-state diagnostic condition:
V
ON
< R
ON
I
L(OL)
; IN high
Open load
detection
Logic
unit
+ Vbb
OUT
ON
V
ON
OFF-state diagnostic condition:
V
OUT
> 3 V typ.; IN low
Open load
detection
Logic
unit
V
OUT
Signal GND
R
EXT
R
O
OFF
GND disconnect
PROFET
V
IN
ST
OUT
GND
bb
V
bb
V
IN
V
ST
V
GND
In case of IN
=
high is
V
OUT
V
IN
-
V
IN(T+)
. Due to V
GND
>
0,
no V
ST
= low signal available.
GND disconnect with GND pull up
PROFET
V
IN
ST
OUT
GND
bb
V
bb
V
GND
V
IN
V
ST
If V
GND
>
V
IN
-
V
IN(T+)
device stays off
Due to V
GND
>
0, no V
ST
= low signal available.
Preliminary BTS 725 L1
Semiconductor Group
10
Typ. on-state resistance
R
ON
= f (Vbb,Tj )
; I
L
=
2
A, IN
= high
R
ON
[mOhm]
0
25
50
75
100
125
150
0
10
20
30
Tj = 150C
85C
25C
-40
C
V
bb
[V]
Typ. open load detection current
I
L(OL)
= f (Vbb,Tj );
IN
= high
I
L(OL)
[mA]
0
50
100
150
200
250
300
350
400
450
500
0
5
10
15
20
25
no load detection not specified
for V
bb
<
6
V
V
bb
[V]
Typ. standby current
I
bb(off)
= f (T
j
)
; V
bb
= 9...24 V, IN1,2
= low
I
bb(off)
[
A]
0
5
10
15
20
25
30
35
40
-50
0
50
100
150
200
T
j
[C]
Typ. initial short circuit shutdown time
t
off(SC)
= f (Tj,start )
; V
bb
=12 V
t
off(SC)
[msec]
0
1
2
3
4
5
6
-50
0
50
100
150
200
T
j,start
[C]
Preliminary BTS 725 L1
Semiconductor Group
11
Figure 1a: V
bb
turn on:
IN2
V
OUT1
t
V
bb
ST open drain
IN1
V
OUT2
Figure 2a: Switching a lamp:
IN
ST
OUT
L
t
V
I
The initial peak current should be limited by the lamp and not by
the initial short circuit current I
L(SCp)
= 28 A typ. of the device.
Figure 3a: Turn on into short circuit:
shut down by overtemperature, restart by cooling
other channel: normal operation
t
I
ST
IN1
L1
L(SCr)
I
I
L(SCp)
t
off(SC)
Heating up of the chip may require several milliseconds, depending
on external conditions (toff(SC) vs. Tj,start see page 10)
Figure 3b: Turn on into short circuit:
shut down by overtemperature, restart by cooling
(two parallel switched channels 1 and 2)
t
ST1/2
IN1/2
L1 L2
L(SCr)
I
I L(SCp)
I + I
t
off(SC)
ST1 and ST2 have to be configured as a 'Wired OR' function
ST1/2 with a single pull-up resistor.
Timing diagrams
Both channels are symmetric and consequently the diagrams are valid for channel 1 and
channel 2
Preliminary BTS 725 L1
Semiconductor Group
12
Figure 4a: Overtemperature:
Reset if
T
j
<
T
jt
IN
ST
OUT
J
t
V
T
Figure 5a: Open load: detection in ON-state, turn
on/off to open load
IN
ST
OUT
L
t
V
I
open
t
d(ST)
t
d(ST OL4)
Figure 5b: Open load: detection in ON-state, open
load occurs in on-state
IN
ST
OUT
L
t
V
I
open
normal
normal
t
d(ST OL1)
t
d(ST OL2)
t
d(ST OL1)
= 20
s typ., t
d(ST OL2)
= 10
s typ
Figure 5c: Open load: detection in ON- and OFF-state
(with R
EXT
), turn on/off to open load
IN
ST
OUT
L
t
V
I
open
t
d(ST)
Preliminary BTS 725 L1
Semiconductor Group
13
Figure 6a: Undervoltage:
IN
V
OUT
t
V
bb
ST
V
V
bb(under)
bb(u rst)
Figure 6b: Undervoltage restart of charge pump
bb(under)
V
V
bb(u rst)
V
bb(over)
V
bb(o rst)
V
bb(u cp)
off-state
on-state
V
ON(CL)
V
bb
V
on
off-state
IN = high, normal load conditions.
Charge pump starts at V
bb(ucp)
= 5.6
V typ.
Figure 7a: Overvoltage:
IN
V
OUT
t
V
bb
ST
ON(CL)
V
V
bb(over)
V
bb(o rst)
Preliminary BTS 725 L1
Semiconductor Group
14
Package and Ordering Code
Standard P-DSO-20-9
Ordering Code
BTS725L1
Q67060-S7006-A2
All dimensions in millimetres
1) Does not include plastic or metal protrusions of 0.15 max per side
2) Does not include dambar protrusion of 0.05 max per side
Definition of soldering point with temperature T
s
:
upper side of solder edge of device pin 15.
Pin 15
Printed circuit board (FR4, 1.5mm thick, one layer
70
m, 6cm
2
active heatsink area) as a reference for
max. power dissipation P
tot
, nominal load current
I
L(NOM)
and thermal resistance R
thja
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