Semiconductor Group
1
The HYB 314175BJ/BJL is the new generation dynamic RAM organized as 262 144 words by
16-bit. The HYB 314175BJ/BJL utilizes CMOS silicon gate process as well as advanced circuit
techniques to provide wide operation margins, both internally and for the system user. Multiplexed
address inputs permit the HYB 314175BJ/BJL to be packed in a standard plastic 400mil wide
P-SOJ-40-1 package. This package size provides high system bit densities and is compatible with
commonly used automatic testing and insertion equipment. System oriented features include Self
Refresh (L-Version), single + 3.3 V (
0.3 V) power supply, direct interfacing with high performance
logic device families.
3.3V 256 K x 16-Bit EDO-DRAM
3.3V 256 K x 16-Bit EDO-DRAM
(Low power version with Self Refresh)
Preliminary Information
262 144 words by 16-bit organization
0 to 70
C operating temperature
Fast access and cycle time
RAS access time:
50 ns (-50 version)
55 ns (-55 version)
60 ns (-60 version)
CAS access time:
13ns (-50 & -55 version)
15 ns (-60 version)
Cycle time:
89 ns (-50 version)
94 ns (-55 version)
104 ns (-60 version)
Hype page mode (EDO) cycle time
20 ns (-50 & -55 version)
25 ns (-60 version)
High data rate
50 MHz (-50 & -55 version)
40 MHz (-60 version)
Single + 3.3 V (
0.3 V) supply with a built-
in VBB generator
Low Power dissipation
max. 450 mW active (-50 version)
max. 432 mW active (-55 version)
max. 378 mW active (-60 version)
Standby power dissipation
7.2 mW standby (TTL)
3.6 mW max. standby (CMOS)
0.72 mW max. standby (CMOS) for
Low Power Version
Output unlatched at cycle end allows two-
dimensional chip selection
Read, write, read-modify write, CAS-
before-RAS refresh, RAS-only refresh,
hidden-refresh and hyper page (EDO)
mode capability
2 CAS / 1 WE control
Self Refresh (L-Version)
All inputs and outputs TTL-compatible
512 refresh cycles / 16 ms
512 refresh cycles / 128 ms
Low Power Version only
Plastic Packages:
P-SOJ-40-1 400mil width
7.96
HYB 314175BJ-50/-55/-60
HYB 314175BJL-50/-55/-60
HYB 314175BJ/BJL-50/-55/-60
3.3V 256K x 16 EDO-DRAM
Semiconductor Group
2
Ordering Information
Truth Table
Pin Names
Type
Ordering Code
Package
Description
HYB 314175BJ-50
Q67100 - Q2148
P-SOJ-40-1
3.3 V 50 ns 256 Kx16 EDO-DRAM
HYB 314175BJ-55
on request
P-SOJ-40-1
3.3 V 55 ns 256 Kx16 EDO-DRAM
HYB 314175BJ-60
Q67100 - Q2149
P-SOJ-40-1
3.3 V 60 ns 256 Kx16 EDO-DRAM
HYB 314175BJL-50
on request
P-SOJ-40-1
3.3 V 50 ns 256 Kx16 EDO- DRAM
HYB 314175BJL-55
on request
P-SOJ-40-1
3.3 V 55 ns 256 Kx16 EDO- DRAM
HYB 314175BJL-60
on request
P-SOJ-40-1
3.3 V 60 ns 256 Kx16 EDO-DRAM
RAS
LCAS
UCAS
WE
OE
I/O1-I/O8
I/O9-I/O16
Operation
H
L
L
L
L
L
L
L
L
H
H
L
H
L
L
H
L
L
H
H
H
L
L
H
L
L
L
H
H
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
H
High-Z
High-Z
Dout
High-Z
Dout
Din
Don't care
Din
High-Z
High-Z
High-Z
High-Z
Dout
Dout
Don't care
Din
Din
High-Z
Standby
Refresh
Lower byte read
Upper byte read
Word read
Lower byte write
Upper byte write
Word write
A0-A8
Address Inputs
RAS
Row Address Strobe
UCAS, LCAS
Column Address Strobe
WE
Read/Write Input
OE
Output Enable
I/O1 I/O16
Data Input/Output
V
CC
Power Supply (+ 3.3 V)
V
SS
Ground (0 V)
N.C.
No Connection
HYB 314175BJ/BJL-50/-55/-60
3.3V 256K x 16 EDO-DRAM
Semiconductor Group
5
Absolute Maximum Ratings
Operating temperature range ........................................................................................ 0 to + 70
C
Storage temperature range..................................................................................... 55 to + 150
C
Input/output voltage ..................................................................................... 1 to (
V
CC
+ 0.5, 4.6) V
Power supply voltage................................................................................................... 1 to + 4.6 V
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under
"
Absolute Maximum Ratings
"
may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
T
A
= 0 to 70
C;
V
SS
= 0 V;
V
CC
= 3.3 V
0.3 V,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
Input high voltage
V
I
H
2.4
V
CC
+ 0.5
V
1
Input low voltage
V
I
L
1.0
0.8
V
1
LVTTL Output high voltage (
I
OUT
= 2.0 mA)
V
OH
2.4
V
1
LVTTL Output low voltage (
I
OUT
= 2 mA)
V
OL
0.4
V
1
LVCMOS Output high voltage (
I
OUT
= 100
A)
V
OH
2.4
V
1
LVCMOS Output low voltage (
I
OUT
= 100
A)
V
OL
0.4
V
1
Input leakage current, any input
(0 V <
V
I
N
< 7 V, all other inputs = 0 V)
I
I
(L)
10
10
A
1
Output leakage current
(DO is disabled, 0 V <
V
OUT
<
V
CC
)
I
O(L)
10
10
A
1
Average
V
CC
supply current:
-50 version
-55 version
-60 version
I
CC1
125
120
105
mA
2, 3, 4
Standby
V
CC
supply current
(RAS = LCAS = UCAS = WE =
V
I
H
)
I
CC2
2
mA
Average
V
CC
supply current during
RAS-only refresh cycles:
-50 version
-55 version
-60 version
I
CC3
125
120
105
mA
2, 4
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