Semiconductor Group 1 6.97
4 194 304 words by 16-bit organization
0 to 70 C operating temperature
Hyper Page Mode - EDO - operation
Performance:
Single + 3.3 V (
0.3V) power supply
Low power dissipation:
7.2 mW standby (TTL)
3.24 mW standby (MOS)
720
A standby for L-version
Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh and Self Refresh (L-version only
2 CAS / 1 WE byte control
8192 refresh cycles/128 ms , 13 R/ 9C addresses (HYB 3164165AT)
4096 refresh cycles/ 64 ms , 12 R/ 10C addresses (HYB 3165165AT)
2048 refresh cycles/ 32 ms , 11 R/ 11C addresses (HYB 3166165AT)
256ms refresh period for L-versions
Plastic Package: P-TSOPII-50 400 mil
-40
-50
-60
t
RAC
RAS access time
40
50
60
ns
t
CAC
CAS access time
10
13
15
ns
t
AA
Access time from address
20
25
30
ns
t
RC
Read/write cycle time
69
84
104
ns
t
HPC
Hyper page mode (EDO)
cycle time
16
20
25
ns
-40
-50
-60
HYB3166165AT(L)
1008
612
450
mW
HYB3165165AT(L)
756
504
360
mW
HYB3164165AT(L)
612
324
324
mW
HYB 3164165AT(L) -40/-50/-60
HYB 3165165AT(L) -40/-50/-60
HYB 3166165AT(L) -40/-50/-60
4M x 16-Bit Dynamic RAM
(8k, 4k & 2k Refresh, EDO-Version)
Advanced Information
Semiconductor Group
2
HYB3164(5/6)165AT(L)-40/-50/-60
4M x 16 EDO-DRAM
This device is a 64 MBit dynamic RAM organized 4 194 304 x 16 bits. The device is fabricated on
an advanced first generation 64Mbit 0,35
m CMOS silicon gate process technology. The circuit
and process design allow this device to achieve high performance and low power dissipation. The
HYB3164(5)165AT operates with a single 3.3 +/-0.3V power supply and interfaces with either
LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB3164(5/6)165AT to be
packaged in 400mil wide TSOPII-50 package. These packages provide high system bit densities
and are compatible with commonly used automatic testing and insertion equipment. The
HYB3164(5/6)165ATL parts have a very low power ,,sleep mode" supported by Self Refresh.
Ordering Information
Type
Ordering
Code
Package
Descriptions
8k-refresh versions:
HYB 3164165AT-40
P-TSOPII-50 400 mil
EDO-DRAM (access time 40 ns)
HYB 3164165AT-50
P-TSOPII-50 400 mil
EDO-DRAM (access time 50 ns)
HYB 3164165AT-60
P-TSOPII-50 400 mil
EDO-DRAM (access time 60 ns)
HYB 3164165ATL-50
P-TSOPII-50 400 mil
EDO-DRAM (access time 50 ns)
HYB 3164165ATL-60
P-TSOPII-50 400 mil
EDO-DRAM (access time 60 ns)
4k-refresh versions:
HYB 3165165AT-40
P-TSOPII-50 400 mil
EDO-DRAM (access time 40 ns)
HYB 3165165AT-50
P-TSOPII-50 400 mil
EDO-DRAM (access time 50 ns)
HYB 3165165AT-60
P-TSOPII-50 400 mil
EDO-DRAM (access time 60 ns)
HYB 3165165ATL-50
P-TSOPII-50 400 mil
EDO-DRAM (access time 50 ns)
HYB 3165165ATL-60
P-TSOPII-50 400 mil
EDO-DRAM (access time 60 ns)
2k-refresh versions:
HYB 3166165AT-40
P-TSOPII-50 400 mil
EDO-DRAM (access time 40 ns)
HYB 3166165AT-50
P-TSOPII-50 400 mil
EDO-DRAM (access time 50 ns)
HYB 3166165AT-60
P-TSOPII-50 400 mil
EDO-DRAM (access time 60 ns)
HYB 3166165ATL-50
P-TSOPII-50 400 mil
EDO-DRAM (access time 50 ns)
HYB 3166165ATL-60
P-TSOPII-50 400 mil
EDO-DRAM (access time 60 ns)
Semiconductor Group
3
HYB3164(5/6)165AT(L)-40/-50/-60
4M x 16 EDO-DRAM
Pin Names
A0-A12
Address Inputs for 8k-refresh version HYB 3164165T(L)
A0-A11
Address Inputs for 4k-refresh version HYB 3165165T(L)
A0-A10
Address Inputs for 2k-refresh version HYB 3166165T(L)
RAS
Row Address Strobe
OE
Output Enable
I/O1-I/O16
Data Input/Output
UCAS, LCAS
Column Address Strobe
WE
Read/Write Input
Vcc
Power Supply ( + 3.3V)
Vss
Ground
P-TSOPII-50 (400 mil)
* Pin 33 is A12 for HYB 3164165AT(L) and N.C. for HYB 3165(6)165AT(L)
Pin Configuration
** Pin 32 is A11 for HYB 3164(5)165AT(L) and N.C. for HYB 3166165AT(L)
O
VCC
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
N.C.
VCC
WE
RAS
N.C.
N.C.
N.C.
N.C.
A0
A1
A2
A3
A4
A5
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
I/O16
I/O15
I/O14
I/O13
VSS
I/O12
I/O11
I/O10
I/O9
N.C.
LCAS
UCAS
OE
N.C.
N.C.
A12/N.C. *
A11/N.C.**
A10
A9
A8
A7
A6
VSS
.
VSS
.
27
26
Semiconductor Group
4
HYB3164(5/6)165AT(L)-40/-50/-60
4M x 16 EDO-DRAM
TRUTH TABLE
FUNCTION
RAS LCAS UCAS
WE
OE
ROW
ADD
COL
ADD
I/O1-
I/O16
Standby
H
H - X
H - X
X
X
X
X
High Impedance
Read:Word
L
L
H
H
L
ROW
COL
Data Out
Read:Lower Byte
L
L
H
H
L
ROW
COL
Lower Byte:Data Out
Upper-Byte:High-Z
Read:Upper Byte
L
H
L
H
L
ROW
COL
Lower Byte:High-Z
Upper Byte:Data Out
Write:Word
(Early-Write)
L
L
L
L
X
ROW
COL
Data In
Write:Lower Byte
(Early-Write)
L
L
H
L
X
ROW
COL
Lower Byte:Data Out
Upper-Byte:High-Z
Write:Upper Byte
(Early Write)
L
H
L
L
X
ROW
COL
Lower Byte:High-Z
Upper Byte:Data Out
Read-Modify-
Write
L
L
L
H - L
L - H ROW
COL
Data Out, Data In
Hyper Page Mode
Read (Word)
1st
Cycle
L
H - L
H - L
H
L
ROW
COL
Data Out
Hyper Page Mode
Read (Word)
2nd
Cycle
L
H - L
H - L
H
L
n/a
COL
Data Out
Hyper Page Mode
Early Write(Word)
1st
Cycle
L
H - L
H - L
L
X
ROW
COL
Data In
Hyper Page Mode
Early Write(Word)
2nd
Cycle
L
H - L
H - L
L
X
n/a
COL
Data In
Hyper Page Mode
RMW
1st
Cycle
L
H - L
H - L
H - L
L - H ROW
COL
Data Out, Data In
Hyper Page Mode
RMW
2st
Cycle
L
H - L
H - L
H - L
L - H n/a
COL
Data Out, Data In
RAS only refresh
L
H
H
X
X
ROW
n/a
High Impedance
CAS-before-RAS
refresh
H - L L
L
H
X
X
n/a
High Impedance
Test Mode Entry
H - L L
L
L
X
X
n/a
High Impedance
Hidden Refresh
(Read)
L-H-
L
L
L
H
L
ROW
COL
Data Out
Hidden Refresh
(Write)
L-H-
L
L
L
L
X
ROW
COL
Data In
Self Refresh
(L-version only)
H-L
L
H
X
X
X
X
High Impedance
Semiconductor Group
5
HYB3164(5/6)165AT(L)-40/-50/-60
4M x 16 EDO-DRAM
Block Diagram for HYB 3164165AT(L)
No. 2 Clock
Generator
Column
Address
Buffer(9)
Refresh
Controller
Refresh
Counter (13)
Address
Buffers(13)
Row
No. 1 Clock
Generator
&
Data in
Buffer
Data out
Buffer
Column
Decoder
Sense Amplifier
I/O Gating
Memory Array
8192x512x16
Row
Decoder
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
WE
UCAS
8192
512
x16
.
RAS
9
13
16
I/O1
I
/O2
OE
13
13
A10
A11
16
16
9
I
/O16
LCAS
.
A12
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